Enables large FPGA Interchange devices for placement

[clavin-xlnx]

This adds an option (--skip_route_resources) to DeviceResourcesExample that will skip adding wires and nodes to the device model FPGA Interchange file. Currently there are a couple of issues (#410, also see #176 (comment)) that would prevent large designs from being written out with routing.

This also fixes a performance bug that caused the Cell <-> BEL pin map: phase to take almost 20 minutes, with this change it now takes about 2 minutes.

The output from a run with the following parameters:

java -Xmx32000m com.xilinx.rapidwright.interchange.DeviceResourcesExample xcvu19p --skip_route_resources

            Prims&Macros:     0.812s     65.209MBs          |   1652.207MBs (peak)
    Cell <-> BEL pin map:   140.047s      0.565MBs          |   5249.344MBs (peak)
                Packages:     0.032s      0.179MBs          |   5253.449MBs (peak)
               Constants:    73.127s   2530.729MBs          |   8781.207MBs (peak)
              Wire Types:     0.011s     -0.373MBs          |   8781.207MBs (peak)
                 Strings:     0.699s     94.670MBs          |   8781.207MBs (peak)
              Write File:     5.147s      0.010MBs          |   8781.207MBs (peak)
             Verify file:   779.180s   3381.796MBs          |  24665.059MBs (peak)
------------------------------------------------------------------------------
                 *Total*:  1004.774s   6878.560MBs          |  24665.059MBs (peak)