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Tests for Versal BEL flags and site unrouting #1125

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merged 6 commits into from
Jan 4, 2025
Merged

Tests for Versal BEL flags and site unrouting #1125

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0caa24f
Tests for Versal BEL flags and site unrouter
clavin-xlnx Dec 16, 2024
8bf0927
Merge branch '2024.2.1' into versal_site_routing
clavin-xlnx Dec 18, 2024
be41b42
rc2 compiled with this PR
clavin-xlnx Dec 18, 2024
7d0d323
Merge branch '2024.2.1' into versal_site_routing
clavin-xlnx Jan 3, 2025
1d5f94b
Merge branch '2024.2.1' into versal_site_routing
clavin-xlnx Jan 4, 2025
524d8a5
rc4, compiled with EDIFNet.getPortInsts() API change
clavin-xlnx Jan 4, 2025
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4 changes: 2 additions & 2 deletions .classpath
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@
<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.1-rc1.jar">
<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.1-rc2.jar">
<attributes>
<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.1-rc1-javadoc.jar!/"/>
<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.1-rc2-javadoc.jar!/"/>
</attributes>
</classpathentry>
<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>
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2 changes: 1 addition & 1 deletion .github/workflows/build.yml
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Expand Up @@ -5,7 +5,7 @@ on:
pull_request:

env:
RAPIDWRIGHT_VERSION: v2024.2.1-rc1-beta
RAPIDWRIGHT_VERSION: v2024.2.1-rc2-beta

jobs:
build:
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3 changes: 1 addition & 2 deletions src/com/xilinx/rapidwright/edif/EDIFNet.java
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,6 @@
import java.io.OutputStream;
import java.nio.charset.StandardCharsets;
import java.util.ArrayList;
import java.util.Collection;
import java.util.Collections;
import java.util.Comparator;
import java.util.List;
Expand Down Expand Up @@ -241,7 +240,7 @@ public EDIFPortInst createPortInst(EDIFPort port, int index, EDIFCellInst cellIn
* Gets the sorted ArrayList of EDIFPortInsts on this net as a collection.
* @return The collection of EDIFPortInsts on this net.
*/
public Collection<EDIFPortInst> getPortInsts() {
public List<EDIFPortInst> getPortInsts() {
return portInsts == null ? Collections.emptyList() : portInsts;
}

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32 changes: 32 additions & 0 deletions test/src/com/xilinx/rapidwright/device/TestBEL.java
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Expand Up @@ -84,4 +84,36 @@ public void testDIFFsAreNotFF(String partName, String siteName, String belName)
Assertions.assertNotNull(b);
Assertions.assertFalse(b.isFF());
}


@Test
public void testIMRFlags() {
Device d = Device.getDevice("xcv80");
String[] siteNames = new String[] { "IRI_QUAD_X34Y8", "IRI_QUAD_X34Y9", "SLICE_X48Y0",
"SLICE_X49Y0" };

for (String siteName : siteNames) {
Site s = d.getSite(siteName);
for (BEL bel : s.getBELs()) {
Assertions.assertEquals(bel.isCEIMR(), bel.getBELType().endsWith("_IMC_FF")
&& (bel.getName().contains("CE") || bel.getName().contains("WE"))
&& bel.getName().contains("IMR"));

Assertions.assertEquals(bel.isSRIMR(), bel.getBELType().endsWith("_IMC_FF_T")
&& (bel.getName().contains("SR") || bel.getName().contains("RST"))
&& bel.getName().contains("IMR"));

Assertions.assertEquals(bel.isIMR(), bel.getBELType().startsWith("SLICE_IMI_FF")
&& bel.getName().contains("IMR"));

Assertions.assertEquals(bel.isSliceFFClkMod(),
bel.getBELType().equals("SLICE_FF_CLK_MOD")
&& bel.getName().contains("CLK_MOD"));

Assertions.assertEquals(bel.isSliceIMRClkMod(),
bel.getBELType().equals("SLICE_IMR_CLK_MOD")
&& bel.getName().contains("CLK_MOD"));
}
}
}
}
103 changes: 103 additions & 0 deletions test/src/com/xilinx/rapidwright/eco/TestECOTools.java
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Expand Up @@ -27,6 +27,7 @@
import com.xilinx.rapidwright.design.DesignTools;
import com.xilinx.rapidwright.design.Net;
import com.xilinx.rapidwright.design.PinType;
import com.xilinx.rapidwright.design.SiteInst;
import com.xilinx.rapidwright.design.SitePinInst;
import com.xilinx.rapidwright.design.Unisim;
import com.xilinx.rapidwright.device.BEL;
Expand Down Expand Up @@ -488,4 +489,106 @@ public void testCreateNet() {
Assertions.assertNotNull(design.getNet(netName));
}
}

@Test
public void testRemoveCellVersal() {
Design d = RapidWrightDCP.loadDCP("picoblaze_2022.2.dcp");

SiteInst si = d.getSiteInst("SLICE_X145Y0");

Assertions.assertNotNull(si.getUsedSitePIP("OUTMUXB2"));
Assertions.assertNotNull(si.getUsedSitePIP("OUTMUXA2"));
Assertions.assertNotNull(si.getUsedSitePIP("FFMUXB2"));
Assertions.assertNotNull(si.getUsedSitePIP("FFMUXA2"));
Assertions.assertEquals("in_port[0]", si.getNetFromSiteWire("BFF2_Q").getName());
Assertions.assertEquals("in_port[0]", si.getNetFromSiteWire("BQ2").getName());

Assertions.assertEquals("in_port[1]", si.getNetFromSiteWire("AFF2_Q").getName());
Assertions.assertEquals("in_port[1]", si.getNetFromSiteWire("AQ2").getName());
Assertions.assertEquals("processor/D[0]", si.getNetFromSiteWire("FFMUXB2_OUT2").getName());
Assertions.assertEquals("processor/D[1]", si.getNetFromSiteWire("FFMUXA2_OUT2").getName());

Assertions.assertEquals(Net.GND_NET, si.getNetFromSiteWire("SR_IMR_Q").getName());
Assertions.assertEquals(Net.VCC_NET, si.getNetFromSiteWire("CE1_IMR_Q").getName());

Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("FF_CLK_MOD_CLK_OUT").getName());

Cell rt = si.getCell("SR_IMR");
Assertions.assertNotNull(rt);
Assertions.assertTrue(rt.isFFRoutethruCell());
Assertions.assertEquals(Net.GND_NET, si.getNetFromSiteWire("RST").getName());
Assertions.assertNotNull(si.getUsedSitePIP("RSTINV"));

rt = si.getCell("CE1_IMR");
Assertions.assertNotNull(rt);
Assertions.assertTrue(rt.isFFRoutethruCell());
Assertions.assertEquals(Net.VCC_NET, si.getNetFromSiteWire("CKEN1").getName());

Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("CLKINV_OUT").getName());
Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("CLK").getName());
Assertions.assertNotNull(si.getUsedSitePIP("CLKINV"));

Cell cell = d.getCell("in_port_reg[0]");
ECOTools.removeCell(d, Collections.singletonList(cell.getEDIFHierCellInst()), null);

Assertions.assertNull(si.getUsedSitePIP("OUTMUXB2"));
Assertions.assertNotNull(si.getUsedSitePIP("OUTMUXA2"));
Assertions.assertNotNull(si.getUsedSitePIP("FFMUXA2"));
Assertions.assertNull(si.getNetFromSiteWire("BFF2_Q"));
Assertions.assertNull(si.getNetFromSiteWire("BQ2"));

Assertions.assertEquals("in_port[1]", si.getNetFromSiteWire("AFF2_Q").getName());
Assertions.assertEquals("in_port[1]", si.getNetFromSiteWire("AQ2").getName());
Assertions.assertEquals("processor/D[1]", si.getNetFromSiteWire("FFMUXA2_OUT2").getName());

Assertions.assertEquals(Net.GND_NET, si.getNetFromSiteWire("SR_IMR_Q").getName());
Assertions.assertEquals(Net.VCC_NET, si.getNetFromSiteWire("CE1_IMR_Q").getName());

Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("FF_CLK_MOD_CLK_OUT").getName());

rt = si.getCell("SR_IMR");
Assertions.assertNotNull(rt);
Assertions.assertTrue(rt.isFFRoutethruCell());
Assertions.assertEquals(Net.GND_NET, si.getNetFromSiteWire("RST").getName());
Assertions.assertNotNull(si.getUsedSitePIP("RSTINV"));

rt = si.getCell("CE1_IMR");
Assertions.assertNotNull(rt);
Assertions.assertTrue(rt.isFFRoutethruCell());
Assertions.assertEquals(Net.VCC_NET, si.getNetFromSiteWire("CKEN1").getName());

Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("CLKINV_OUT").getName());
Assertions.assertEquals("clk_IBUF", si.getNetFromSiteWire("CLK").getName());
Assertions.assertNotNull(si.getUsedSitePIP("CLKINV"));

cell = d.getCell("in_port_reg[1]");
ECOTools.removeCell(d, Collections.singletonList(cell.getEDIFHierCellInst()), null);

Assertions.assertNull(si.getUsedSitePIP("OUTMUXB2"));
Assertions.assertNull(si.getUsedSitePIP("OUTMUXA2"));
Assertions.assertNull(si.getNetFromSiteWire("BFF2_Q"));
Assertions.assertNull(si.getNetFromSiteWire("BQ2"));

Assertions.assertNull(si.getNetFromSiteWire("AFF2_Q"));
Assertions.assertNull(si.getNetFromSiteWire("AQ2"));

Assertions.assertNull(si.getNetFromSiteWire("SR_IMR_Q"));
Assertions.assertNull(si.getNetFromSiteWire("CE1_IMR_Q"));

Assertions.assertNull(si.getNetFromSiteWire("FF_CLK_MOD_CLK_OUT"));

rt = si.getCell("SR_IMR");
Assertions.assertNull(rt);
Assertions.assertNull(si.getNetFromSiteWire("RST"));
Assertions.assertNull(si.getUsedSitePIP("RSTINV"));

rt = si.getCell("CE1_IMR");
Assertions.assertNull(rt);
Assertions.assertNull(si.getNetFromSiteWire("CKEN1"));

Assertions.assertNull(si.getNetFromSiteWire("CLKINV_OUT"));
Assertions.assertNull(si.getNetFromSiteWire("CLK"));
Assertions.assertNull(si.getUsedSitePIP("CLKINV"));

}
}
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