Merge branch 'xcvp1902_slr' of github.com:Xilinx/RapidWright into xcv…

…p1902_slr

Signed-off-by: Chris Lavin <[email protected]>

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.1.3.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.0-rc1.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.1.3-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.0-rc1-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2024.1.3-beta
+  RAPIDWRIGHT_VERSION: v2024.2.0-rc1-beta
 
 jobs:
   build:
@@ -15,25 +15,23 @@ jobs:
         single_threaded: [multi-threaded, single-threaded]
     runs-on: ${{ matrix.os }}
     steps:
-      - uses: actions/checkout@v2
-
-      - uses: gradle/wrapper-validation-action@e6e38bacfdf1a337459f332974bb2327a31aaf4b
+      - uses: actions/checkout@v4
 
       - name: Setup JDK 1.11
-        uses: actions/setup-java@v2
+        uses: actions/setup-java@v4
         with:
           distribution: 'temurin'
           java-version: '11'
           cache: 'gradle'
 
       - name: Setup Python 3.7
-        uses: actions/setup-python@v2
+        uses: actions/setup-python@v5
         with:
           python-version: 3.7
 
       - name: Cache Jars & Data
         id: cache-rapidwright
-        uses: actions/cache@v2
+        uses: actions/cache@v4
         with:
           path: |
               data

common.gradle

@@ -65,11 +65,7 @@ configurations.testFixturesImplementation.canBeResolved = true
 configurations.api.canBeResolved = true
 
 tasks.withType(Test) {
-  if (System.getenv("GITHUB_ACTION")) {
-    maxHeapSize = "5G"
-  } else {
-    maxHeapSize = "10G"
-  }
+  maxHeapSize = "10G"
   //Propagate JVM settings to test JVM
   jvmArgs applicationDefaultJvmArgs
 

src/com/xilinx/rapidwright/MainEntrypoint.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021-2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Jakob Wenzel, Xilinx Research Labs.
@@ -103,6 +103,7 @@
 import com.xilinx.rapidwright.util.PartPrinter;
 import com.xilinx.rapidwright.util.PerformanceExplorer;
 import com.xilinx.rapidwright.util.ReplaceEDIFInDCP;
+import com.xilinx.rapidwright.util.ReportRouteStatus;
 import com.xilinx.rapidwright.util.StringTools;
 import com.xilinx.rapidwright.util.Unzip;
 import com.xilinx.rapidwright.util.performance_evaluation.PerformanceEvaluation;
@@ -186,6 +187,7 @@ private static void addFunction(String name, MainStyleFunction<?> func) {
         addFunction("RelocationTools", RelocationTools::main);
         addFunction("ReplaceEDIFInDCP", ReplaceEDIFInDCP::main);
         addFunction("ReportDevicePerformance", ReportDevicePerformance::main);
+        addFunction("ReportRouteStatus", ReportRouteStatus::main);
         addFunction("ReportTimingExample", ReportTimingExample::main);
         addFunction("Router", Router::main);
         addFunction("RouteThruHelper", RouteThruHelper::main);

src/com/xilinx/rapidwright/design/ModuleInst.java

@@ -39,9 +39,6 @@
 import com.xilinx.rapidwright.device.Site;
 import com.xilinx.rapidwright.device.SiteTypeEnum;
 import com.xilinx.rapidwright.device.Tile;
-import com.xilinx.rapidwright.edif.EDIFNet;
-import com.xilinx.rapidwright.edif.EDIFPortInst;
-import com.xilinx.rapidwright.edif.EDIFTools;
 import com.xilinx.rapidwright.util.MessageGenerator;
 import com.xilinx.rapidwright.util.Utils;
 
@@ -356,6 +353,10 @@ public boolean place(Site newAnchorSite, boolean skipIncompatible, boolean allow
                         }
                     }
                 }
+                if (existingSiteInst != null) {
+                    unplace();
+                    return false;
+                }
             }
 
             if (newSite == null || existingSiteInst != null) {

src/com/xilinx/rapidwright/design/NetTools.java

@@ -22,9 +22,16 @@
 
 package com.xilinx.rapidwright.design;
 
+import java.util.ArrayList;
+import java.util.Collections;
 import java.util.EnumSet;
+import java.util.HashMap;
+import java.util.List;
+import java.util.Map;
 import java.util.Set;
 
+import com.xilinx.rapidwright.device.Node;
+import com.xilinx.rapidwright.device.PIP;
 import com.xilinx.rapidwright.device.SiteTypeEnum;
 
 public class NetTools {
@@ -46,4 +53,109 @@ public static boolean isGlobalClock(Net net) {
 
         return clkSrcSiteTypeEnums.contains(srcSpi.getSiteTypeEnum());
     }
+
+    public static class NodeTree extends Node {
+        public List<NodeTree> fanouts = Collections.emptyList();
+        public NodeTree(Node node) {
+            super(node);
+        }
+
+        public void addFanout(NodeTree node) {
+            if (fanouts.isEmpty()) {
+                fanouts = new ArrayList<>(1);
+            }
+            fanouts.add(node);
+        }
+
+        private void buildString(StringBuilder sb,
+                                 boolean subtreeStart,
+                                 boolean branchStart,
+                                 boolean branchEndIfNoFanouts,
+                                 boolean subTreeEndIfNoFanouts) {
+            // Adopt the same spacing as Vivado's report_route_status
+            sb.append("    ");
+            sb.append(subtreeStart ? "[" : " ");
+            sb.append(branchStart ? "{" : " ");
+            sb.append("   ");
+            boolean branchEnd = branchEndIfNoFanouts && fanouts.isEmpty();
+            sb.append(branchEnd ? "}" : " ");
+            boolean subtreeEnd = subTreeEndIfNoFanouts && branchEnd;
+            sb.append(subtreeEnd ? "]" : " ");
+            sb.append(String.format("  %30s", super.toString()));
+            sb.append("\n");
+
+            subtreeStart = false;
+            for (int i = 0; i < fanouts.size(); i++) {
+                NodeTree fanout = fanouts.get(i);
+                boolean lastFanout = (i == fanouts.size() - 1);
+                branchStart = !lastFanout && (fanouts.size() > 1);
+                branchEndIfNoFanouts = lastFanout || branchStart;
+                fanout.buildString(sb, subtreeStart, branchStart, branchEndIfNoFanouts,
+                        subTreeEndIfNoFanouts && !branchStart && lastFanout);
+            }
+        }
+
+        @Override
+        public String toString() {
+            StringBuilder sb = new StringBuilder();
+            boolean subtreeStart = true;
+            boolean branchStart = true;
+            boolean branchEndIfNoFanouts = true;
+            boolean subTreeEndIfNoFanouts = true;
+            buildString(sb, branchStart, subtreeStart, branchEndIfNoFanouts, subTreeEndIfNoFanouts);
+            return sb.toString();
+        }
+    }
+
+    /**
+     * Compute the node routing tree of the given Net by examining its PIPs.
+     * Note that this method: (a) assumes that no loops are present, (b) only discovers subtrees that start at an
+     * output SitePinInst or a node tied to VCC/GND (i.e. gaps and islands will be ignored).
+     * @param net Net to analyze
+     * @return A list of NodeTree objects, corresponding to the root of each subtree.
+     */
+    public static List<NodeTree> getNodeTrees(Net net) {
+        List<NodeTree> subtrees = new ArrayList<>();
+        Map<Node, NodeTree> nodeMap = new HashMap<>();
+        for (PIP pip : net.getPIPs()) {
+            if (pip.isEndWireNull()) {
+                continue;
+            }
+            boolean isReversed = pip.isReversed();
+            NodeTree startNode = nodeMap.computeIfAbsent(isReversed ? pip.getEndNode() : pip.getStartNode(), NodeTree::new);
+            NodeTree endNode = nodeMap.computeIfAbsent(isReversed ? pip.getStartNode() : pip.getEndNode(), NodeTree::new);
+            startNode.addFanout(endNode);
+            if (!pip.isBidirectional()) {
+                if ((net.getType() == NetType.GND && startNode.isTiedToGnd()) ||
+                    (net.getType() == NetType.VCC && startNode.isTiedToVcc())) {
+                    subtrees.add(startNode);
+                }
+            }
+        }
+
+        for (SitePinInst spi : net.getPins()) {
+            if (!spi.isOutPin()) {
+                continue;
+            }
+            Node node = spi.getConnectedNode();
+            NodeTree nodeTree = nodeMap.computeIfAbsent(node, NodeTree::new);
+            subtrees.add(nodeTree);
+        }
+
+        return subtrees;
+    }
+
+    /**
+     * Checks if the provided net drives a clock site pin input.
+     * 
+     * @param net The net to examine.
+     * @return True if the net has a site pin clock input, false otherwise.
+     */
+    public static boolean hasClockSinks(Net net) {
+        for (SitePinInst sink : net.getPins()) { 
+            if (sink.isOutPin()) continue;
+            if (sink.getName().contains("CLK")) return true;
+        }
+        return false;
+    }
 }

src/com/xilinx/rapidwright/design/Unisim.java

@@ -33,12 +33,32 @@
 import com.xilinx.rapidwright.edif.EDIFLibrary;
 
 /**
- * Generated on: Wed May 01 19:57:08 MDT 2024
+ * Generated on: Thu Nov 21 13:34:09 MST 2024
  * by: com.xilinx.rapidwright.release.UnisimParser
  *
  * Enumerates supported Unisim primitives that map to Xilinx devices.
  */
 public enum Unisim {
+    AIE2PS_NOC_M_AXI,
+    AIE2PS_NOC_M_AXIS,
+    AIE2PS_NOC_S_AXI,
+    AIE2PS_NOC_S_AXIS,
+    AIE2PS_PL_M_AXIS128,
+    AIE2PS_PL_M_AXIS32,
+    AIE2PS_PL_M_AXIS64,
+    AIE2PS_PL_M_EVENTS,
+    AIE2PS_PL_S_AXIS128,
+    AIE2PS_PL_S_AXIS32,
+    AIE2PS_PL_S_AXIS64,
+    AIE2PS_PL_S_EVENTS,
+    AIE2P_PL_M_AXIS128,
+    AIE2P_PL_M_AXIS32,
+    AIE2P_PL_M_AXIS64,
+    AIE2P_PL_M_EVENTS,
+    AIE2P_PL_S_AXIS128,
+    AIE2P_PL_S_AXIS32,
+    AIE2P_PL_S_AXIS64,
+    AIE2P_PL_S_EVENTS,
     AIE_ML_NOC_M_AXI,
     AIE_ML_NOC_M_AXIS,
     AIE_ML_NOC_S_AXI,
@@ -85,6 +105,8 @@ public enum Unisim {
     AND5B4,
     AND5B5,
     AUTOBUF,
+    AXI32,
+    BFR_FT,
     BFR_MATMULX,
     BIBUF,
     BITSLICE_CONTROL,
@@ -157,8 +179,10 @@ public enum Unisim {
     DDRMC,
     DDRMC5,
     DDRMC5C,
+    DDRMC5E,
     DDRMC_RIU,
     DFE_CFR,
+    DFE_CHANNELIZER,
     DFE_DUC_DDC,
     DFE_FFT,
     DFE_FIR,
@@ -258,6 +282,7 @@ public enum Unisim {
     FRAME_ECCE3,
     FRAME_ECCE4,
     FRAME_ECC_VIRTEX6,
+    FUSE_CLK,
     GND,
     GTF_CHANNEL,
     GTF_COMMON,
@@ -769,6 +794,7 @@ public enum Unisim {
     NOC2_NMU256,
     NOC2_NMU512,
     NOC2_NPS5555,
+    NOC2_NPS6X,
     NOC2_NPS7575,
     NOC2_NSU128,
     NOC2_NSU256,
@@ -1193,6 +1219,7 @@ public enum Unisim {
     PLLE4_BASE,
     PLL_ADV,
     PLL_BASE,
+    PS11,
     PS7,
     PS8,
     PS9,
@@ -1290,9 +1317,11 @@ public enum Unisim {
     RAMS64E1,
     RAMS64E5,
     RFADC,
+    RFADCE5,
     RFADC_13B4W_M0,
     RFADC_13B4W_M1,
     RFDAC,
+    RFDACE5,
     RIU_OR,
     ROM128X1,
     ROM16X1,
@@ -1301,8 +1330,10 @@ public enum Unisim {
     ROM64X1,
     RXTX_BITSLICE,
     RX_BITSLICE,
+    SDFEC_LD,
     SIM_CONFIGE2,
     SIM_CONFIGE3,
+    SIM_CONFIGE4,
     SRL16,
     SRL16E,
     SRL16E_1,

src/com/xilinx/rapidwright/design/blocks/PBlock.java

@@ -67,6 +67,9 @@ public class PBlock extends ArrayList<PBlockRange> {
         pblockTypes.add(SiteTypeEnum.SLICEM);
         pblockTypes.add(SiteTypeEnum.DSP48E1);
         pblockTypes.add(SiteTypeEnum.DSP48E2);
+        pblockTypes.add(SiteTypeEnum.DSP58_PRIMARY);
+        pblockTypes.add(SiteTypeEnum.DSP58);
+        pblockTypes.add(SiteTypeEnum.DSPFP);
         pblockTypes.add(SiteTypeEnum.RAMB180);
         pblockTypes.add(SiteTypeEnum.RAMB181);
         pblockTypes.add(SiteTypeEnum.RAMB18E1);

src/com/xilinx/rapidwright/design/tools/Edge.java

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Author: Chris Lavin, AMD Research and Advanced Development.
+ *
+ * This file is part of RapidWright.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+package com.xilinx.rapidwright.design.tools;
+
+/**
+ * Describes the edge types of rectangles when composed of tiles.
+ */
+public enum Edge {
+    NORTH,
+    EAST,
+    SOUTH,
+    WEST,
+    NORTH_EAST,
+    SOUTH_EAST,
+    SOUTH_WEST,
+    NORTH_WEST,
+    INTERNAL,
+    EXTERNAL;
+
+    public boolean isEdgeCrossing() {
+        return this != INTERNAL && this != EXTERNAL;
+    }
+}