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Fix tests caused by createA1A6ToStaticNets()
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Signed-off-by: Eddie Hung <[email protected]>
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eddieh-xlnx committed Dec 5, 2024
1 parent 675291a commit 8ea2765
Showing 1 changed file with 12 additions and 10 deletions.
22 changes: 12 additions & 10 deletions src/com/xilinx/rapidwright/design/DesignTools.java
Original file line number Diff line number Diff line change
Expand Up @@ -3312,8 +3312,8 @@ public static void createA1A6ToStaticNets(Design design) {
BEL lut6Bel = (fiveOrSix == '5') ? si.getBEL(belName.charAt(0) + "6LUT") : bel;
Net a6Net = si.getNetFromSiteWire(lut6Bel.getPin("A6").getSiteWireName());

boolean expectGndNet = false;
if ("SRL16E".equals(cell.getType())) {
// SRL16s require A1 to be VCC
String pinName = belName.charAt(0) + "1";
SitePinInst spi = si.getSitePinInst(pinName);
if (spi == null) {
Expand All @@ -3322,22 +3322,24 @@ public static void createA1A6ToStaticNets(Design design) {

// SRL16Es that have been transformed from SRLC32E require GND on their A6 pin
if ("SRLC32E".equals(cell.getPropertyValueString("XILINX_LEGACY_PRIM"))) {
expectGndNet = true;
staticNet = gndNet;
assert(a6Net.isGNDNet());
// Expect sitewire to be VCC or GND
if (!a6Net.isStaticNet()) {
throw new RuntimeException("ERROR: Site pin " + si.getSiteName() + "/" + belName.charAt(0) + "6 is not a static net");
}
}

// [A-H]6 input already has a (static) net
spi = si.getSitePinInst(belName.charAt(0) + "6");
if (spi != null) {
assert(LUTTools.getCompanionLUT(cell) != null ? a6Net.isVCCNet() : a6Net.isGNDNet());
// [A-H]6 input already has this static net
assert(a6Net == staticNet);
continue;
}
} else {
// Tie A6 to staticNet only if sitewire says so
if (a6Net != staticNet) {
continue;
}
}

// Tie A6 to staticNet only if sitewire says so
if (a6Net != staticNet && !expectGndNet) {
continue;
}

if (cell.getLogicalPinMapping("O5") != null) {
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