Merge pull request #1127 from Xilinx/2024.2.1

2024.2.1
Xilinx · Jan 15, 2025 · 5dc47ce · 5dc47ce
2 parents 6d7db5c + 3681eb8
commit 5dc47ce
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diff --git a/.classpath b/.classpath
@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.0.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.1.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.0-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.1-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2024.2.0-beta
+  RAPIDWRIGHT_VERSION: v2024.2.1-beta
 
 jobs:
   build:
@@ -24,10 +24,10 @@ jobs:
           java-version: '11'
           cache: 'gradle'
 
-      - name: Setup Python 3.7
+      - name: Setup Python 3.12
         uses: actions/setup-python@v5
         with:
-          python-version: 3.7
+          python-version: 3.12
 
       - name: Cache Jars & Data
         id: cache-rapidwright

diff --git a/RELEASE_NOTES.TXT b/RELEASE_NOTES.TXT
@@ -1,3 +1,27 @@
+============= RapidWright 2024.2.1-beta released on 2025-1-15 ================
+Notes: 
+  - Adds an Override Flag for Advanced Flow Settings in Designs (#1135)
+  - Test for SiteInst.isEmpty() (#1128)
+  - Tests for Versal BEL flags and site unrouting (#1125)
+  - [LUTTools] Versal pin swapping fixes (#1130)
+  - [DesignTools] foreachConnectedBELPin() to walk through Versal IMRs (#1129)
+  - [DesignTools] updatePinsIsRouted() to return num unrouted sinks (#1131)
+  - [TestDesign] Add testPlaceCellPinMappings() (#1122)
+  - [RWRoute] Small cleanup; enable CUFR by default (#1126)
+  - RWRoute preprocessing fixes (#1119)
+  - Enables setting Advanced Flow Flags for Designs
+  - Corrects and Adds BEL flags; fixes unroute site net for Versal
+  - [Cell] Fixes to P2L and L2P
+
+API Additions:
+  - com.xilinx.rapidwright.design.Cell "public void fixCell(boolean isFixed)"
+  - com.xilinx.rapidwright.design.Cell "public boolean isCellFixed()"
+  - com.xilinx.rapidwright.design.Design "public boolean isAdvancedFlow()"
+  - com.xilinx.rapidwright.design.Design "public void setAdvancedFlow(boolean val)"
+  - com.xilinx.rapidwright.design.SiteInst "public boolean isEmpty()"
+  - com.xilinx.rapidwright.device.BEL "public boolean isCEIMR()"
+  - com.xilinx.rapidwright.device.BEL "public boolean isSliceIMRClkMod()"
+
 ============= RapidWright 2024.2.0-beta released on 2024-12-04 ================
 Notes: 
   - Remove reliance on gap routing test (#1117)

diff --git a/build.gradle b/build.gradle
@@ -212,8 +212,6 @@ task testPython(type:Test) {
       args = ['-m', 'pytest', '--junitxml', '$buildDir/test-results/testPython/testPython.xml', '--rootdir', 'python/test']
       // Enable verbose flag which prints out a pass/fail for every test
       args += ['-v']
-      // Prevent python/tests/... with the same namespace as in Java from clobbering
-      args += ['--import-mode=importlib']
       // Workaround from https://github.com/jpype-project/jpype/issues/842#issuecomment-847027355
       args += ['-p', 'no:faulthandler']
       if (!filter.commandLineIncludePatterns.isEmpty()) {

diff --git a/python/test/com/__init__.py b/python/test/com/__init__.py
diff --git a/python/test/com/xilinx/__init__.py b/python/test/com/xilinx/__init__.py
diff --git a/python/test/com/xilinx/rapidwright/__init__.py b/python/test/com/xilinx/rapidwright/__init__.py
diff --git a/python/test/com/xilinx/rapidwright/design/__init__.py b/python/test/com/xilinx/rapidwright/design/__init__.py
diff --git a/python/test/com/xilinx/rapidwright/util/__init__.py b/python/test/com/xilinx/rapidwright/util/__init__.py
diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java
@@ -2003,7 +2003,8 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
     }
 
     /**
-     * Looks in the site instance for BEL pins connected to this site pin.
+     * Looks in the site instance for used BEL pins connected to this site pin.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The BELPin to examine for connected BEL pins.
      * @param si The SiteInst to examine for connected cells.
      * @param action Perform this action on each connected BELPin.
@@ -2020,21 +2021,31 @@ private static void foreachConnectedBELPin(BELPin pin, SiteInst si, Consumer<BEL
                     p = pip.getInputPin().getSiteConns().get(0);
                     action.accept(p);
                 } else {
-                    for (BELPin snk : pip.getOutputPin().getSiteConns()) {
-                        action.accept(snk);
-                    }
+                    // Walk through any used SitePIPs
+                    foreachConnectedBELPin(pip.getOutputPin(), si, action);
                 }
             } else {
                 Cell c = si.getCell(p.getBELName());
-                if (c != null && c.getLogicalPinMapping(p.getName()) != null) {
+                if (c == null) {
+                    continue;
+                }
+                if (c.getLogicalPinMapping(p.getName()) == null) {
+                    continue;
+                }
+                BEL bel = c.getBEL();
+                if ((bel.isIMR() || bel.isSRIMR() || bel.isCEIMR()) && c.isRoutethru()) {
+                    // Walk through IMR registers
+                    foreachConnectedBELPin(bel.getPin("Q"), si, action);
+                } else {
                     action.accept(p);
                 }
             }
         }
     }
 
     /**
-     * Looks in the site instance for cells connected to this BEL pin and SiteInst.
+     * Looks in the site instance for cells connected (i.e. with a logical pin mapping) to this BEL pin and SiteInst.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The BELPin to examine for connected cells.
      * @param si The SiteInst to examine for connected cells.
      * @return Set of connected cells to this pin.
@@ -2051,7 +2062,8 @@ public static Set<Cell> getConnectedCells(BELPin pin, SiteInst si) {
     }
 
     /**
-     * Looks in the site instance for cells connected to this site pin.
+     * Looks in the site instance for cells connected (i.e. with a logical pin mapping) to this site pin.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The SitePinInst to examine for connected cells.
      * @return Set of connected cells to this pin.
      */
@@ -2061,6 +2073,7 @@ public static Set<Cell> getConnectedCells(SitePinInst pin) {
 
     /**
      * Looks in the site instance for BEL pins connected to this BEL pin and SiteInst.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The SitePinInst to examine for connected BEL pins.
      * @param si The SiteInst to examine for connected cells.
      * @return Set of BEL pins to this site pin.
@@ -2297,8 +2310,7 @@ public static List<String> getAllRoutedSitePinsFromPhysicalPin(Cell cell, Net ne
                     } else if (bel.isLUT() ||
                             bel.getBELType().endsWith("MUX") || // F[789]MUX
                             // Versal
-                            bel.isSliceFFClkMod() ||
-                            bel.getName().endsWith("_IMR")) {
+                            bel.isSliceFFClkMod() || bel.isIMR() || bel.isSRIMR() || bel.isCEIMR()) {
                         Cell possibleRouteThru = inst.getCell(bel);
                         if (possibleRouteThru == null) {
                             BELPin clkBelPin = bel.isSliceFFClkMod() ? bel.getPin("CLK") : null;

diff --git a/src/com/xilinx/rapidwright/design/tools/LUTTools.java b/src/com/xilinx/rapidwright/design/tools/LUTTools.java
@@ -595,7 +595,7 @@ public static void swapSingleLutPins(String key, Collection<PinSwap> pinSwaps) {
             String oldPhysicalPin = oPins[i];
             String newPhysicalPin = ePins[i];
             Cell c = emptySlots.get(newPhysicalPin).getCell();
-            String newNetPinName = c.getSiteWireNameFromPhysicalPin(newPhysicalPin);
+            String newNetPinName = c.getBELName().substring(0, 1) + newPhysicalPin.charAt(1);
             // Handles special cases
             if (c.getLogicalPinMapping(oldPhysicalPin) == null) {
                 Cell neighborLUT = emptySlots.get(newPhysicalPin).checkForCompanionCell();
@@ -636,13 +636,14 @@ public static void swapSingleLutPins(String key, Collection<PinSwap> pinSwaps) {
         Queue<SitePinInst> q = new LinkedList<>();
         for (PinSwap ps : copyOnWritePinSwaps) {
             Cell cell = ps.getCell();
-            String oldSitePinName = cell.getSiteWireNameFromPhysicalPin(ps.getOldPhysicalName());
+            String oldSitePinName = cell.getBELName().substring(0, 1) + ps.getOldPhysicalName().charAt(1);
             SiteInst si = cell.getSiteInst();
             SitePinInst pinToMove = si.getSitePinInst(oldSitePinName);
             q.add(pinToMove);
             if (pinToMove == null) {
                 continue;
             }
+            si.unrouteIntraSiteNet(pinToMove.getBELPin(), cell.getBEL().getPin(ps.getOldPhysicalName()));
             pinToMove.setSiteInst(null,true);
             // Removes pin mappings to prepare for new pin mappings
             cell.removePinMapping(ps.getOldPhysicalName());
@@ -672,7 +673,9 @@ public static void swapSingleLutPins(String key, Collection<PinSwap> pinSwaps) {
                 continue;
             }
             pinToMove.setPinName(ps.getNewNetPinName());
-            pinToMove.setSiteInst(cell.getSiteInst());
+            SiteInst si = cell.getSiteInst();
+            pinToMove.setSiteInst(si);
+            si.routeIntraSiteNet(pinToMove.getNet(), pinToMove.getBELPin(), cell.getBEL().getPin(ps.getNewPhysicalName()));
         }
 
         assert(q.isEmpty());

diff --git a/src/com/xilinx/rapidwright/edif/EDIFNet.java b/src/com/xilinx/rapidwright/edif/EDIFNet.java
@@ -30,7 +30,6 @@
 import java.io.OutputStream;
 import java.nio.charset.StandardCharsets;
 import java.util.ArrayList;
-import java.util.Collection;
 import java.util.Collections;
 import java.util.Comparator;
 import java.util.List;
@@ -241,7 +240,7 @@ public EDIFPortInst createPortInst(EDIFPort port, int index, EDIFCellInst cellIn
      * Gets the sorted ArrayList of EDIFPortInsts on this net as a collection.
      * @return The collection of EDIFPortInsts on this net.
      */
-    public Collection<EDIFPortInst> getPortInsts() {
+    public List<EDIFPortInst> getPortInsts() {
         return portInsts == null ? Collections.emptyList() : portInsts;
     }
 

diff --git a/src/com/xilinx/rapidwright/rwroute/RouterHelper.java b/src/com/xilinx/rapidwright/rwroute/RouterHelper.java
@@ -360,20 +360,19 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
             SiteInst si = spi.getSiteInst();
             String siteWireName = spi.getSiteWireName();
             if (invertLutInputs && spi.isLUTInputPin()) {
-                BELPin spiBelPin;
-                if (isVersal) {
-                    // Walk through IMR before checking for connected cells
-                    spiBelPin = si.getBELPin(spi.getSiteWireName() + "_IMR", "Q");
-                } else {
-                    spiBelPin = spi.getBELPin();
-                }
-                Collection<Cell> connectedCells = DesignTools.getConnectedCells(spiBelPin, si);
+                Collection<Cell> connectedCells = DesignTools.getConnectedCells(spi);
                 if (connectedCells.isEmpty()) {
-                    for (BELPin belPin : si.getSiteWirePins(spiBelPin.getSiteWireName())) {
+                    for (BELPin belPin : si.getSiteWirePins(spi.getSiteWireName())) {
                         if (belPin.isSitePort()) {
                             continue;
                         }
                         BEL bel = belPin.getBEL();
+                        if (isVersal && bel.isIMR()) {
+                            // Since DesignTools.getConnectedCells() will only return cells
+                            // for which a logical pin mapping exists, for the purpose of
+                            // identifying SRL16s walk through this IMR
+                            bel = si.getBEL(bel.getName().substring(0,1) + "6LUT");
+                        }
                         Cell cell = si.getCell(bel);
                         if (cell == null) {
                             continue;
@@ -411,7 +410,7 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
                 toInvertPins.add(spi);
                 // Re-paint the intra-site routing from GND to VCC
                 // (no intra site routing will occur during Net.addPin() later)
-                si.routeIntraSiteNet(vccNet, spi.getBELPin(), spiBelPin);
+                si.routeIntraSiteNet(vccNet, spi.getBELPin(), spi.getBELPin());
 
                 for (Cell cell : connectedCells) {
                     // Find the logical pin name

diff --git a/src/com/xilinx/rapidwright/util/Params.java b/src/com/xilinx/rapidwright/util/Params.java
@@ -36,6 +36,8 @@ public class Params {
 
     public static String RW_WRITE_DCP_2024_1_NAME = "RW_WRITE_DCP_2024_1";
 
+    public static String RW_DISABLE_WRITING_ADV_FLOW_DCPS_NAME = "RW_DISABLE_WRITING_ADV_FLOW_DCPS";
+
     /**
      * Flag to have RapidWright decompress gzipped EDIF files to disk prior to
      * parsing. This is a tradeoff where pre-decompression improves runtime over the
@@ -60,6 +62,14 @@ public class Params {
      */
     public static boolean RW_WRITE_DCP_2024_1 = isParamSet(RW_WRITE_DCP_2024_1_NAME);
 
+    /**
+     * Flag to disable RapidWright from writing any DCPs that target Vivado's
+     * Advanced Flow (starting in Vivado 2024.2). By default, RapidWright writes
+     * DCPs targeting Versal devices with the Advanced Flow compatibility flag set
+     * to true.
+     */
+    public static boolean RW_DISABLE_WRITING_ADV_FLOW_DCPS = isParamSet(RW_DISABLE_WRITING_ADV_FLOW_DCPS_NAME);
+
     /**
      * Checks if the named RapidWright parameter is set via an environment variable
      * or by a JVM parameter of the same name.

diff --git a/src/com/xilinx/rapidwright/util/VivadoTools.java b/src/com/xilinx/rapidwright/util/VivadoTools.java
@@ -22,15 +22,16 @@
 
 package com.xilinx.rapidwright.util;
 
-import com.xilinx.rapidwright.design.Design;
-import com.xilinx.rapidwright.edif.EDIFTools;
-
 import java.io.File;
 import java.nio.file.FileSystems;
+import java.nio.file.Files;
 import java.nio.file.Path;
 import java.util.ArrayList;
 import java.util.List;
 
+import com.xilinx.rapidwright.design.Design;
+import com.xilinx.rapidwright.edif.EDIFTools;
+
 /**
  * Utility methods to provide access to vivado and parse logs
  *
@@ -115,6 +116,11 @@ public static List<String> runTcl(Path outputLog, Path tclScript, boolean verbos
                 + tclScript.toString();
         Integer exitCode = FileTools.runCommand(vivadoCmd, verbose, environ, runDir);
         if (exitCode != 0) {
+            if (Files.exists(outputLog)) {
+                for (String l : FileTools.getLinesFromTextFile(outputLog.toString())) {
+                    System.out.println("FAILED OUTPUT> " + l);
+                }
+            }
             throw new RuntimeException("Vivado exited with code: " + exitCode);
         }
         return FileTools.getLinesFromTextFile(outputLog.toString());

diff --git a/test/src/com/xilinx/rapidwright/design/TestDCPWrite.java b/test/src/com/xilinx/rapidwright/design/TestDCPWrite.java
@@ -24,6 +24,7 @@
 
 import java.nio.file.Path;
 
+import org.junit.jupiter.api.Assertions;
 import org.junit.jupiter.api.Test;
 import org.junit.jupiter.api.io.TempDir;
 
@@ -53,4 +54,35 @@ public void testNewPhysDBWrite(@TempDir Path dir) {
             VivadoToolsHelper.assertFullyRouted(dcp);
         }
     }
+
+    @Test
+    public void testAdvancedFlowFlags(@TempDir Path tempDir) {
+        Design design = RapidWrightDCP.loadDCP("picoblaze_2022.2.dcp");
+
+        // Should be true since it is targeting Versal
+        Assertions.assertTrue(design.isAdvancedFlow());
+        Path defaultDCPPath = tempDir.resolve("default.dcp");
+        design.writeCheckpoint(defaultDCPPath);
+
+        Design defaultDCP = Design.readCheckpoint(defaultDCPPath);
+        Assertions.assertTrue(defaultDCP.isAdvancedFlow());
+
+        design.setAdvancedFlow(false);
+        Assertions.assertFalse(design.isAdvancedFlow());
+        Path setFalseDCPPath = tempDir.resolve("false.dcp");
+        design.writeCheckpoint(setFalseDCPPath);
+
+        Design falseDCP = Design.readCheckpoint(setFalseDCPPath);
+        // Write DCP should revert flag to default case (true)
+        Assertions.assertTrue(falseDCP.isAdvancedFlow());
+
+        falseDCP.setAdvancedFlow(true);
+
+        Path overrideDCPPath = tempDir.resolve("override.dcp");
+        Params.RW_DISABLE_WRITING_ADV_FLOW_DCPS = true;
+        Assertions.assertTrue(falseDCP.isAdvancedFlow());
+        falseDCP.writeCheckpoint(overrideDCPPath);
+        // Return to default for other tests
+        Params.RW_DISABLE_WRITING_ADV_FLOW_DCPS = false;
+    }
 }
diff --git a/test/src/com/xilinx/rapidwright/design/TestDesign.java b/test/src/com/xilinx/rapidwright/design/TestDesign.java
@@ -515,4 +515,36 @@ public void testNetOrder(String dcpFileName) {
             Assertions.assertTrue(Arrays.equals(nets1, nets2));
         }
     }
+
+    @Test
+    public void testPlaceCellPinMappings() {
+        final EDIFNetlist netlist = TestEDIF.createEmptyNetlist();
+        final Design design = new Design(netlist);
+
+        final Cell myCell = design.createCell("myCell", Unisim.FDRE);
+        Assertions.assertTrue(myCell.getPinMappingsL2P().isEmpty());
+
+        final Site site = design.getDevice().getSite(SITE);
+        design.createSiteInst(site);
+        BEL bel = site.getBEL("AFF");
+        Assertions.assertNotNull(bel);
+        design.placeCell(myCell, site, bel);
+
+        // Check that L2P and P2L are consistent
+        for (String logPin : new String[]{"CE", "C", "D", "R", "Q"}) {
+            String physPin = myCell.getPhysicalPinMapping(logPin);
+            Assertions.assertEquals(logPin, myCell.getLogicalPinMapping(physPin));
+        }
+
+        // Move the Cell to another BEL
+        myCell.unplace();
+        bel = site.getBEL("BFF");
+        design.placeCell(myCell, site, bel);
+
+        // Check that L2P and P2L remain consistent
+        for (String logPin : new String[]{"CE", "C", "D", "R", "Q"}) {
+            String physPin = myCell.getPhysicalPinMapping(logPin);
+            Assertions.assertEquals(logPin, myCell.getLogicalPinMapping(physPin));
+        }
+    }
 }