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Pump LLVM to 23b82c987d690939f3e7b1431d6004f409c10425
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@hanchenye
hanchenye committed Dec 27, 2023
1 parent cd98fe3 commit e0b5521
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Showing 13 changed files with 201 additions and 75 deletions.
2 changes: 1 addition & 1 deletion CMakeLists.txt
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Expand Up @@ -40,7 +40,7 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
else ()
set(LLVM_SOURCE_DIR ${LLVM_MAIN_SRC_DIR})
set(MLIR_MAIN_SRC_DIR ${LLVM_MAIN_SRC_DIR}/../mlir)
set(MLIR_INCLUDE_DIRS ${MLIR_MAIN_SRC_DIR}/include)
set(MLIR_INCLUDE_DIR ${MLIR_MAIN_SRC_DIR}/include)
set(MLIR_CMAKE_DIR ${MLIR_MAIN_SRC_DIR}/cmake/modules)
set(MLIR_TABLEGEN_EXE $<TARGET_FILE:mlir-tblgen>)
set(MLIR_TABLEGEN_OUTPUT_DIR ${LLVM_BINARY_DIR}/tools/mlir/include)
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5 changes: 5 additions & 0 deletions include/scalehls/Utils/Utils.h
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Expand Up @@ -55,6 +55,11 @@ getEvenlyDistributedFactors(unsigned maxFactor, FactorList &factors,
const SmallVectorImpl<FactorList> &constrFactors,
bool powerOf2Constr = false);

/// Compose any affine.apply ops feeding into `operands` of the integer set
/// `set` by composing the maps of such affine.apply ops with the integer
/// set constraints.
void composeSetAndOperands(IntegerSet &set, SmallVectorImpl<Value> &operands);

/// Return a pair which indicates whether the if statement is always true or
/// false, respectively. The returned result is one-hot.
std::pair<bool, bool> ifAlwaysTrueOrFalse(affine::AffineIfOp ifOp);
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6 changes: 3 additions & 3 deletions include/scalehls/Utils/Visitor.h
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Expand Up @@ -58,7 +58,7 @@ class HLSVisitorBase {

// Float binary expressions.
arith::CmpFOp, arith::AddFOp, arith::SubFOp, arith::MulFOp,
arith::DivFOp, arith::RemFOp, arith::MaxFOp, arith::MinFOp,
arith::DivFOp, arith::RemFOp, arith::MaximumFOp, arith::MinimumFOp,
math::PowFOp,

// Integer binary expressions.
Expand Down Expand Up @@ -171,8 +171,8 @@ class HLSVisitorBase {
HANDLE(arith::MulFOp);
HANDLE(arith::DivFOp);
HANDLE(arith::RemFOp);
HANDLE(arith::MaxFOp);
HANDLE(arith::MinFOp);
HANDLE(arith::MaximumFOp);
HANDLE(arith::MinimumFOp);
HANDLE(math::PowFOp);

// Integer binary expressions.
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13 changes: 12 additions & 1 deletion lib/Dialect/HLS/IR/HLS.cpp
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Expand Up @@ -8,6 +8,7 @@
#include "mlir/IR/DialectImplementation.h"
#include "mlir/IR/IntegerSet.h"
#include "scalehls/Dialect/HLS/Utils/Utils.h"
#include "scalehls/Utils/Utils.h"
#include "llvm/ADT/TypeSwitch.h"

using namespace mlir;
Expand Down Expand Up @@ -145,7 +146,7 @@ struct AlwaysTrueOrFalseSelect : public OpRewritePattern<AffineSelectOp> {
else if (set.getNumInputs() == 0) {
SmallVector<bool, 4> flagList;
for (auto expr : llvm::enumerate(set.getConstraints())) {
auto constValue = expr.value().cast<AffineConstantExpr>().getValue();
auto constValue = cast<AffineConstantExpr>(expr.value()).getValue();
flagList.push_back(set.isEq(expr.index()) ? constValue == 0
: constValue >= 0);
}
Expand Down Expand Up @@ -262,6 +263,16 @@ ParseResult AffineSelectOp::parse(OpAsmParser &parser, OperationState &result) {
return success();
}

/// Prints dimension and symbol list.
static void printDimAndSymbolList(Operation::operand_iterator begin,
Operation::operand_iterator end,
unsigned numDims, OpAsmPrinter &printer) {
OperandRange operands(begin, end);
printer << '(' << operands.take_front(numDims) << ')';
if (operands.size() > numDims)
printer << '[' << operands.drop_front(numDims) << ']';
}

void AffineSelectOp::print(OpAsmPrinter &p) {
auto conditionAttr =
(*this)->getAttrOfType<IntegerSetAttr>(getConditionAttrStrName());
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26 changes: 12 additions & 14 deletions lib/Dialect/HLS/Transforms/BufferizableOpInterfaceImpl.cpp
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Expand Up @@ -20,13 +20,13 @@ struct DispatchOrTaskOpInterface
: public BufferizableOpInterface::ExternalModel<
DispatchOrTaskOpInterface<OpType>, OpType> {
AliasingOpOperandList
getAliasingOpOperands(Operation *op, OpResult opResult,
getAliasingOpOperands(Operation *op, Value value,
const AnalysisState &state) const {
// Dispatch/task do not have tensor OpOperands. The yielded value can be any
// SSA value that is in scope. To allow for use-def chain traversal in the
// analysis, the yielded value is aliasing with the result.
size_t resultNum = std::distance(op->getOpResults().begin(),
llvm::find(op->getOpResults(), opResult));
llvm::find(op->getOpResults(), value));
OpOperand *operand =
&cast<OpType>(op).getYieldOp()->getOpOperand(resultNum);
return {{operand, BufferRelation::Equivalent}};
Expand Down Expand Up @@ -63,7 +63,7 @@ struct DispatchOrTaskOpInterface

FailureOr<BaseMemRefType>
getBufferType(Operation *op, Value value, const BufferizationOptions &options,
const DenseMap<Value, BaseMemRefType> &fixedTypes) const {
SmallVector<Value> &invocationStack) const {
assert(value.getDefiningOp() == op && "invalid value");
auto yieldedValue = cast<OpType>(op).getYieldOp().getOperand(
value.cast<OpResult>().getResultNumber());
Expand All @@ -73,7 +73,7 @@ struct DispatchOrTaskOpInterface
return bufferType;

auto maybeBufferType =
bufferization::getBufferType(yieldedValue, options, fixedTypes);
bufferization::getBufferType(yieldedValue, options, invocationStack);
if (failed(maybeBufferType))
return failure();
return *maybeBufferType;
Expand All @@ -94,8 +94,8 @@ struct YieldOpInterface
return false;
}

AliasingOpResultList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
AliasingValueList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
if (isa<DispatchOp, TaskOp>(op->getParentOp()))
return {{op->getParentOp()->getResult(opOperand.getOperandNumber()),
BufferRelation::Equivalent}};
Expand Down Expand Up @@ -172,19 +172,17 @@ struct AllocTensorOpInterface
return false;
}

bool bufferizesToAllocation(Operation *op, OpResult opResult) const {
return true;
}
bool bufferizesToAllocation(Operation *op, Value value) const { return true; }

AliasingOpResultList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
AliasingValueList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
// This is a new allocation. It does not alias with any other buffer.
return {};
}

FailureOr<BaseMemRefType>
getBufferType(Operation *op, Value value, const BufferizationOptions &options,
const DenseMap<Value, BaseMemRefType> &fixedTypes) const {
SmallVector<Value> &invocationStack) const {
auto allocTensor = cast<AllocTensorOp>(op);
assert(value == allocTensor.getResult() && "invalid value");

Expand Down Expand Up @@ -256,8 +254,8 @@ struct InstanceOpInterface
return success();
}

AliasingOpResultList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
AliasingValueList getAliasingOpResults(Operation *op, OpOperand &opOperand,
const AnalysisState &state) const {
// Output operands alias with their respective tied OpResults.
auto instance = cast<InstanceOp>(op);
if (instance.getPortKind(opOperand) == PortKind::OUTPUT)
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4 changes: 2 additions & 2 deletions lib/Dialect/HLS/Transforms/SimplifyDesignSpace.cpp
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Expand Up @@ -24,10 +24,10 @@ struct ConstantizeParamOpPattern : public OpRewritePattern<ParamOp> {
constValue = op.getCandidates().value()[0];

} else if (op.isRangeConstrained())
if (auto constLb = op.getLowerBound().dyn_cast<AffineConstantExpr>()) {
if (auto constLb = dyn_cast<AffineConstantExpr>(op.getLowerBound())) {
auto ub = op.getUpperBound();
auto diff = simplifyAffineExpr(ub - constLb, 0, op.getNumOperands());
if (auto constDiff = diff.dyn_cast<AffineConstantExpr>())
if (auto constDiff = dyn_cast<AffineConstantExpr>(diff))
if (constDiff.getValue() <= op.getStepAttr().getInt())
constValue =
Builder(op.getContext()).getIndexAttr(constLb.getValue());
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4 changes: 2 additions & 2 deletions lib/Dialect/HLS/Utils/Matchers.cpp
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Expand Up @@ -370,14 +370,14 @@ FailureOr<IPMatchingResult> IPMatcher::match() {
// to generate corresponding buffer-level hls.instance.
//
Value matchedPort;
if (auto ipInputIndex = getIndex(ipLinalgOp.getDpsInputOperands())) {
if (auto ipInputIndex = getIndex(ipLinalgOp.getDpsInputs())) {
// When the argument is "input" port, the "mapLhsArgIndexToRhs" is used
// for the step 3) mapping.
auto payloadInputIndex =
linalgMatchingResult->mapLhsArgIndexToRhs(ipInputIndex.value());
matchedPort = payload.getDpsInputOperand(payloadInputIndex)->get();

} else if (auto ipInitIndex = getIndex(ipLinalgOp.getDpsInitOperands())) {
} else if (auto ipInitIndex = getIndex(ipLinalgOp.getDpsInits())) {
// When the argument is "initiation" port, the "mapLhsResIndexToRhs" is
// used for the step 3) mapping.
auto payloadInitIndex =
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2 changes: 1 addition & 1 deletion lib/Transforms/ComprehensiveBufferize.cpp
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Expand Up @@ -114,7 +114,7 @@ struct ComprehensiveBufferize
OneShotBufferizationOptions options = getBufferizationOptions();
options.allocationFn = allocationFn;
options.memCpyFn = memCpyFn;
options.allowReturnAllocs = true;
options.allowReturnAllocsFromLoops = true;
options.bufferizeFunctionBoundaries = true;

if (failed(runScaleHLSOneShotBufferize(moduleOp, options)))
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28 changes: 17 additions & 11 deletions lib/Translation/EmitHLSCpp.cpp
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Expand Up @@ -413,7 +413,7 @@ class AffineExprEmitter : public ScaleHLSEmitterBase,
/// Affine expression emitters.
void emitAffineBinary(AffineBinaryOpExpr expr, const char *syntax) {
os << "(";
if (auto constRHS = expr.getRHS().dyn_cast<AffineConstantExpr>()) {
if (auto constRHS = dyn_cast<AffineConstantExpr>(expr.getRHS())) {
if ((unsigned)*syntax == (unsigned)*"*" && constRHS.getValue() == -1) {
os << "-";
visit(expr.getLHS());
Expand All @@ -428,8 +428,8 @@ class AffineExprEmitter : public ScaleHLSEmitterBase,
return;
}
}
if (auto binaryRHS = expr.getRHS().dyn_cast<AffineBinaryOpExpr>()) {
if (auto constRHS = binaryRHS.getRHS().dyn_cast<AffineConstantExpr>()) {
if (auto binaryRHS = dyn_cast<AffineBinaryOpExpr>(expr.getRHS())) {
if (auto constRHS = dyn_cast<AffineConstantExpr>(binaryRHS.getRHS())) {
if ((unsigned)*syntax == (unsigned)*"+" && constRHS.getValue() == -1 &&
binaryRHS.getKind() == AffineExprKind::Mul) {
visit(expr.getLHS());
Expand Down Expand Up @@ -593,8 +593,12 @@ class ExprVisitor : public HLSVisitorBase<ExprVisitor, bool> {
bool visitOp(arith::MulFOp op) { return emitter.emitBinary(op, "*"), true; }
bool visitOp(arith::DivFOp op) { return emitter.emitBinary(op, "/"), true; }
bool visitOp(arith::RemFOp op) { return emitter.emitBinary(op, "%"), true; }
bool visitOp(arith::MaxFOp op) { return emitter.emitMaxMin(op, "max"), true; }
bool visitOp(arith::MinFOp op) { return emitter.emitMaxMin(op, "min"), true; }
bool visitOp(arith::MaximumFOp op) {
return emitter.emitMaxMin(op, "max"), true;
}
bool visitOp(arith::MinimumFOp op) {
return emitter.emitMaxMin(op, "min"), true;
}
bool visitOp(math::PowFOp op) { return emitter.emitMaxMin(op, "pow"), true; }

/// Integer binary expressions.
Expand Down Expand Up @@ -1228,7 +1232,8 @@ void ModuleEmitter::emitAffineYield(affine::AffineYieldOp op) {
os << " = ";
emitValue(op.getOperand(resultIdx++), rank);
break;
case (arith::AtomicRMWKind::maxf):
case (arith::AtomicRMWKind::maximumf):
case (arith::AtomicRMWKind::maxnumf):
case (arith::AtomicRMWKind::maxs):
case (arith::AtomicRMWKind::maxu):
os << " = max(";
Expand All @@ -1237,7 +1242,8 @@ void ModuleEmitter::emitAffineYield(affine::AffineYieldOp op) {
emitValue(op.getOperand(resultIdx++), rank);
os << ")";
break;
case (arith::AtomicRMWKind::minf):
case (arith::AtomicRMWKind::minimumf):
case (arith::AtomicRMWKind::minnumf):
case (arith::AtomicRMWKind::mins):
case (arith::AtomicRMWKind::minu):
os << " = min(";
Expand Down Expand Up @@ -1283,7 +1289,7 @@ ModuleEmitter::getTransferIndices(TransferOpType op) {
// Construct the physical indices.
for (unsigned i = 0, e = op.getPermutationMap().getNumResults(); i < e; ++i) {
auto expr = op.getPermutationMap().getResult(i);
if (auto dimExpr = expr.template dyn_cast<AffineDimExpr>())
if (auto dimExpr = dyn_cast<AffineDimExpr>(expr))
indices[dimExpr.getPosition()] += " + iv" + std::to_string(i);
}
return indices;
Expand All @@ -1304,7 +1310,7 @@ getTransferCondition(TransferOpType op,
SmallString<16> condition;
for (auto i : outOfBoundDims) {
auto expr = op.getPermutationMap().getResult(i);
if (auto dimExpr = expr.template dyn_cast<AffineDimExpr>()) {
if (auto dimExpr = dyn_cast<AffineDimExpr>(expr)) {
auto pos = dimExpr.getPosition();
condition += indices[pos];
condition += " < " + std::to_string(op.getShapedType().getDimSize(pos));
Expand All @@ -1320,7 +1326,7 @@ void ModuleEmitter::emitInsert(vector::InsertOp op) {
addAlias(op.getDest(), op.getResult());
indent();
emitValue(op.getDest());
os << "[" << op.getPosition()[0].cast<IntegerAttr>().getInt() << "] = ";
os << "[" << op.getStaticPosition()[0] << "] = ";
emitValue(op.getSource());
os << ";";
emitInfoAndNewLine(op);
Expand All @@ -1331,7 +1337,7 @@ void ModuleEmitter::emitExtract(vector::ExtractOp op) {
emitValue(op.getResult());
os << " = ";
emitValue(op.getVector());
os << "[" << op.getPosition()[0].cast<IntegerAttr>().getInt() << "];";
os << "[" << op.getStaticPosition()[0] << "];";
emitInfoAndNewLine(op);
}

Expand Down
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