feat: update project tt_um_factory_test from TinyTapeout/tt07-factory…

…-test

Commit: 621f231073d8c253b949dd9cddae0c090b094966
Workflow: https://github.com/TinyTapeout/tt07-factory-test/actions/runs/9024281373

projects/tt_um_factory_test/commit_id.json

@@ -1,9 +1,9 @@
 {
-  "app": "Tiny Tapeout tt07 ef33610c",
+  "app": "Tiny Tapeout tt07 68e6da5b",
   "repo": "https://github.com/TinyTapeout/tt07-factory-test",
-  "commit": "1d902b7d845bbf74325c8afa446bc7cee048e99b",
-  "workflow_url": "https://github.com/TinyTapeout/tt07-factory-test/actions/runs/8767662707",
+  "commit": "621f231073d8c253b949dd9cddae0c090b094966",
+  "workflow_url": "https://github.com/TinyTapeout/tt07-factory-test/actions/runs/9024281373",
   "sort_id": 1713709204861,
-  "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
+  "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
 }

projects/tt_um_factory_test/docs/info.md

@@ -10,10 +10,10 @@ You can also include images in this folder and reference them in the markdown. E
 ## How it works
 
 If `sel` is high, then a counter is output on the output pins and the bidirectional pins (`data_o = counter_o = counter`).
-If `sel` is low, the bidirectional pins are mirrored to the output pins (`data_o` = `data_i`).
+If `sel` is low, the input pins and the bidirectional pins are xored, and the result appears on the output pins (`data_o = in_a ^ in_b`).
 
 ## How to test
 
 Set `sel` high and observe that the counter is output on the output pins (`data_o`) and the bidirectional pins (`counter_o`).
 
-Set `sel` low and observe that the bidirectional pins are mirrored to the output pins (`data_o` = `data_i`).
+Set `sel` low and observe that the xor of the input pins (`in_a`) and the bidirectional pins (`in_b`) is output on `data_o`.

projects/tt_um_factory_test/info.yaml

@@ -1,11 +1,11 @@
 # Tiny Tapeout project information
 project:
   title:        "TinyTapeout 7 Factory Test"      # Project title
-  author:       "Sylvain Munaut"      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  author:       "Tiny Tapeout"             # Your name
+  discord:      ""                         # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "Factory test module"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     0         # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
@@ -20,14 +20,14 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "sel"
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "sel / in_a[0]"
+  ui[1]: "in_a[1]"
+  ui[2]: "in_a[2]"
+  ui[3]: "in_a[3]"
+  ui[4]: "in_a[4]"
+  ui[5]: "in_a[5]"
+  ui[6]: "in_a[6]"
+  ui[7]: "in_a[7]"
 
   # Outputs
   uo[0]: "data_o[0]"
@@ -40,14 +40,14 @@ pinout:
   uo[7]: "data_o[7]"
 
   # Bidirectional pins
-  uio[0]: "data_i[0] / counter_o[0]"
-  uio[1]: "data_i[1] / counter_o[1]"
-  uio[2]: "data_i[2] / counter_o[2]"
-  uio[3]: "data_i[3] / counter_o[3]"
-  uio[4]: "data_i[4] / counter_o[4]"
-  uio[5]: "data_i[5] / counter_o[5]"
-  uio[6]: "data_i[6] / counter_o[6]"
-  uio[7]: "data_i[7] / counter_o[7]"
+  uio[0]: "in_b[0] / counter_o[0]"
+  uio[1]: "in_b[1] / counter_o[1]"
+  uio[2]: "in_b[2] / counter_o[2]"
+  uio[3]: "in_b[3] / counter_o[3]"
+  uio[4]: "in_b[4] / counter_o[4]"
+  uio[5]: "in_b[5] / counter_o[5]"
+  uio[6]: "in_b[6] / counter_o[6]"
+  uio[7]: "in_b[7] / counter_o[7]"
 
 # Do not change!
 yaml_version: 6

projects/tt_um_factory_test/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_factory_test,wokwi,flow completed,0h0m51s0ms,0h0m35s0ms,10136.610317509825,0.01795472,5068.305158754913,4.09,6.736459999999999,480.95,68,0,0,0,0,0,0,0,0,0,0,-1,-1,1691,549,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1249435.0,0.0,4.87,1.2,0.2,1.34,-1,20,76,10,52,0,0,0,41,8,9,3,0,2,4,3,8,17,24,3,1187,225,0,242,91,1745,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_factory_test,wokwi,flow completed,0h0m51s0ms,0h0m35s0ms,11696.088827895952,0.01795472,5848.044413947976,4.53,7.214379999999999,480.86,75,0,0,0,0,0,0,0,0,0,0,-1,-1,2292,634,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1773485.0,0.0,5.67,1.66,1.84,1.76,-1,28,84,11,53,0,0,0,48,8,9,3,0,2,11,3,8,24,24,4,1186,225,0,243,105,1759,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_factory_test/stats/synthesis-stats.txt

@@ -3,31 +3,33 @@
 
 === tt_um_factory_test ===
 
-   Number of wires:                 52
-   Number of wire bits:             87
+   Number of wires:                 59
+   Number of wire bits:             94
    Number of public wires:          17
    Number of public wire bits:      52
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 68
+   Number of cells:                 75
+     sky130_fd_sc_hd__a21o_2         7
      sky130_fd_sc_hd__a21oi_2        1
      sky130_fd_sc_hd__a31o_2         1
      sky130_fd_sc_hd__and2_2         9
      sky130_fd_sc_hd__and2b_2        1
      sky130_fd_sc_hd__and3_2         1
      sky130_fd_sc_hd__and4_2         2
-     sky130_fd_sc_hd__buf_1         19
+     sky130_fd_sc_hd__buf_1         12
      sky130_fd_sc_hd__buf_2          8
      sky130_fd_sc_hd__conb_1         1
      sky130_fd_sc_hd__dfrtp_2        9
      sky130_fd_sc_hd__inv_2          1
-     sky130_fd_sc_hd__mux2_2         8
-     sky130_fd_sc_hd__nand2_2        1
+     sky130_fd_sc_hd__mux2_2         1
+     sky130_fd_sc_hd__nand2_2        8
      sky130_fd_sc_hd__nor2_2         1
+     sky130_fd_sc_hd__o21ba_2        7
      sky130_fd_sc_hd__or2_2          1
      sky130_fd_sc_hd__xnor2_2        1
      sky130_fd_sc_hd__xor2_2         3
 
-   Chip area for module '\tt_um_factory_test': 650.624000
+   Chip area for module '\tt_um_factory_test': 720.691200