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feat: update project tt_um_devinatkin_fastreadout from devinatkin/tt0…
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…6-fastreadout

Commit: d23213b49321c50eeb193d5cbd4fcb3beb60141f
Workflow: https://github.com/devinatkin/tt06-fastreadout/actions/runs/8715895237
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 17, 2024
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6 changes: 3 additions & 3 deletions projects/tt_um_devinatkin_fastreadout/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt06 ef272636",
"app": "Tiny Tapeout tt06 eed83093",
"repo": "https://github.com/devinatkin/tt06-fastreadout",
"commit": "07d47833a916afcd51ec9ab5df01667bd04eaca7",
"workflow_url": "https://github.com/devinatkin/tt06-fastreadout/actions/runs/8576064085",
"commit": "d23213b49321c50eeb193d5cbd4fcb3beb60141f",
"workflow_url": "https://github.com/devinatkin/tt06-fastreadout/actions/runs/8715895237",
"sort_id": 1712354785013,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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6 changes: 3 additions & 3 deletions projects/tt_um_devinatkin_fastreadout/docs/info.md
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Expand Up @@ -10,12 +10,12 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

This project simulates an image sensor. Provide an input which represents the the pixel values for current row and column (512 bits each). Then the internals will simulate those light levels. The output will then be a series of packets representing the widths of the pixel outputs. This can then be re-recovered back into
This project simulates an image sensor with the intention of validating a readout method. Light levels are fed in, and then the ouput is used to re-recover those light levels. This is done by using a set of frequency modules to convert the light levels into frequencies, and then a set of frequency counters to measure the frequency of the output. The design is validated through the testbenches both simulating a full 1MP sensor (These are run in the long testbenches action) and a smaller number of pixels in the actual manufactured hardware and shorter testbenches. I cannot unfortunately think of any way to make this design more useful to anyone else, but I wish anyone who tries the best of luck.

## How to test

Test Code will be provided in this repository. I will try and write this code both for an FPGA and for a Pi Pico. I'll extend this with instructions for how to verify that the code is indeed functional.
There are testbenches provided in this repository which should verify the functionaltiy of the design. The test directory also includes a top level testbench which can be used to verify the design once it is fabricated.

## External hardware

This design will need to be hooked up to an external FPGA in order to drive it and verify its functionality. For this reason the top level testbench will mostly be synthesizable components which can be used on that device and will be targetted towards the Basys 3.
The top level test under the test directory will have a circuit python equivalent written which will allow the design to be tested from the external RP2040 microcontroller. This will allow the design to be tested in the actual hardware as well as in simulation.
2 changes: 1 addition & 1 deletion projects/tt_um_devinatkin_fastreadout/stats/metrics.csv
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@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_devinatkin_fastreadout,wokwi,flow completed,0h9m13s0ms,0h7m37s0ms,168063.2058601738,0.0756025088,84031.6029300869,79.78,88.6734,739.96,5074,0,0,0,0,0,0,0,4,1,0,-1,-1,134342,42580,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,70683477.0,0.0,64.51,48.09,13.65,4.05,-1,2866,5235,247,2080,0,0,0,4107,129,0,360,168,392,560,264,168,1187,1184,11,906,1037,15,1803,6353,10114,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,161.0,6.211180124223603,160,1,50,153.18,153.6,0.3,1,10,0.8,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_devinatkin_fastreadout,wokwi,flow completed,0h7m39s0ms,0h6m7s0ms,149730.48090171316,0.0756025088,74865.24045085658,72.34,79.5814,701.89,4542,0,0,0,0,0,0,0,0,0,0,-1,-1,108955,36498,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,62873031.0,0.0,55.28,38.93,7.42,1.98,-1,2584,4612,262,1650,0,0,0,3706,152,0,320,168,280,504,288,128,1051,1064,9,1681,1037,2,1749,5660,10129,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,41.0,24.390243902439025,40,1,50,153.18,153.6,0.3,1,10,0.75,0,sky130_fd_sc_hd,AREA 0
116 changes: 56 additions & 60 deletions projects/tt_um_devinatkin_fastreadout/stats/synthesis-stats.txt
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Expand Up @@ -3,72 +3,68 @@

=== tt_um_devinatkin_fastreadout ===

Number of wires: 5058
Number of wire bits: 5093
Number of public wires: 1192
Number of public wire bits: 1227
Number of wires: 4526
Number of wire bits: 4561
Number of public wires: 1072
Number of public wire bits: 1107
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 5074
sky130_fd_sc_hd__a2111o_2 6
sky130_fd_sc_hd__a2111oi_2 3
sky130_fd_sc_hd__a211o_2 5
sky130_fd_sc_hd__a211oi_2 57
sky130_fd_sc_hd__a21bo_2 32
sky130_fd_sc_hd__a21boi_2 29
sky130_fd_sc_hd__a21o_2 144
sky130_fd_sc_hd__a21oi_2 95
sky130_fd_sc_hd__a221o_2 15
sky130_fd_sc_hd__a221oi_2 2
sky130_fd_sc_hd__a22o_2 430
sky130_fd_sc_hd__a2bb2o_2 12
sky130_fd_sc_hd__a311oi_2 2
sky130_fd_sc_hd__a31o_2 61
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__a32o_2 90
sky130_fd_sc_hd__a41o_2 3
sky130_fd_sc_hd__and2_2 182
sky130_fd_sc_hd__and2b_2 21
sky130_fd_sc_hd__and3_2 240
sky130_fd_sc_hd__and3b_2 137
sky130_fd_sc_hd__and4_2 45
sky130_fd_sc_hd__and4b_2 2
sky130_fd_sc_hd__buf_1 505
Number of cells: 4542
sky130_fd_sc_hd__a211o_2 25
sky130_fd_sc_hd__a211oi_2 41
sky130_fd_sc_hd__a21bo_2 14
sky130_fd_sc_hd__a21boi_2 51
sky130_fd_sc_hd__a21o_2 119
sky130_fd_sc_hd__a21oi_2 98
sky130_fd_sc_hd__a221o_2 17
sky130_fd_sc_hd__a22o_2 393
sky130_fd_sc_hd__a22oi_2 10
sky130_fd_sc_hd__a2bb2o_2 8
sky130_fd_sc_hd__a311o_2 10
sky130_fd_sc_hd__a31o_2 81
sky130_fd_sc_hd__a32o_2 110
sky130_fd_sc_hd__a41o_2 6
sky130_fd_sc_hd__and2_2 239
sky130_fd_sc_hd__and2b_2 24
sky130_fd_sc_hd__and3_2 172
sky130_fd_sc_hd__and3b_2 112
sky130_fd_sc_hd__and4_2 25
sky130_fd_sc_hd__buf_1 441
sky130_fd_sc_hd__buf_2 16
sky130_fd_sc_hd__conb_1 8
sky130_fd_sc_hd__dfxtp_2 1184
sky130_fd_sc_hd__inv_2 101
sky130_fd_sc_hd__mux2_2 50
sky130_fd_sc_hd__nand2_2 368
sky130_fd_sc_hd__nand3_2 30
sky130_fd_sc_hd__nand4_2 3
sky130_fd_sc_hd__nor2_2 194
sky130_fd_sc_hd__nor2b_2 1
sky130_fd_sc_hd__nor3_2 3
sky130_fd_sc_hd__nor4_2 2
sky130_fd_sc_hd__o2111a_2 3
sky130_fd_sc_hd__o211a_2 83
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o21a_2 85
sky130_fd_sc_hd__o21ai_2 105
sky130_fd_sc_hd__o221a_2 21
sky130_fd_sc_hd__o22a_2 7
sky130_fd_sc_hd__o22ai_2 5
sky130_fd_sc_hd__o2bb2a_2 2
sky130_fd_sc_hd__o311a_2 73
sky130_fd_sc_hd__o311ai_2 1
sky130_fd_sc_hd__o31a_2 12
sky130_fd_sc_hd__o31ai_2 2
sky130_fd_sc_hd__or2_2 354
sky130_fd_sc_hd__or2b_2 17
sky130_fd_sc_hd__or3_2 49
sky130_fd_sc_hd__or3b_2 6
sky130_fd_sc_hd__or4_2 25
sky130_fd_sc_hd__dfxtp_2 1064
sky130_fd_sc_hd__inv_2 103
sky130_fd_sc_hd__mux2_2 56
sky130_fd_sc_hd__mux4_2 24
sky130_fd_sc_hd__nand2_2 292
sky130_fd_sc_hd__nand3_2 35
sky130_fd_sc_hd__nand4_2 4
sky130_fd_sc_hd__nor2_2 204
sky130_fd_sc_hd__nor3_2 12
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__o2111a_2 9
sky130_fd_sc_hd__o211a_2 37
sky130_fd_sc_hd__o211ai_2 3
sky130_fd_sc_hd__o21a_2 77
sky130_fd_sc_hd__o21ai_2 154
sky130_fd_sc_hd__o21ba_2 5
sky130_fd_sc_hd__o221a_2 14
sky130_fd_sc_hd__o221ai_2 2
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o22ai_2 3
sky130_fd_sc_hd__o2bb2a_2 10
sky130_fd_sc_hd__o311a_2 8
sky130_fd_sc_hd__o31a_2 29
sky130_fd_sc_hd__o41a_2 8
sky130_fd_sc_hd__or2_2 200
sky130_fd_sc_hd__or2b_2 11
sky130_fd_sc_hd__or3_2 25
sky130_fd_sc_hd__or4_2 7
sky130_fd_sc_hd__or4b_2 2
sky130_fd_sc_hd__or4bb_2 4
sky130_fd_sc_hd__xnor2_2 96
sky130_fd_sc_hd__xor2_2 42
sky130_fd_sc_hd__xnor2_2 69
sky130_fd_sc_hd__xor2_2 49

Chip area for module '\tt_um_devinatkin_fastreadout': 56369.062400
Chip area for module '\tt_um_devinatkin_fastreadout': 51112.771200

Binary file modified projects/tt_um_devinatkin_fastreadout/tt_um_devinatkin_fastreadout.gds
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114 changes: 57 additions & 57 deletions projects/tt_um_devinatkin_fastreadout/tt_um_devinatkin_fastreadout.lef
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Expand Up @@ -64,7 +64,7 @@ MACRO tt_um_devinatkin_fastreadout
PIN ui_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 147.510 224.760 147.810 225.760 ;
Expand All @@ -73,7 +73,7 @@ MACRO tt_um_devinatkin_fastreadout
PIN ui_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.159000 ;
PORT
LAYER met4 ;
RECT 143.830 224.760 144.130 225.760 ;
Expand All @@ -82,7 +82,7 @@ MACRO tt_um_devinatkin_fastreadout
PIN ui_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.159000 ;
PORT
LAYER met4 ;
RECT 140.150 224.760 140.450 225.760 ;
Expand Down Expand Up @@ -277,7 +277,7 @@ MACRO tt_um_devinatkin_fastreadout
PIN uio_out[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 51.830 224.760 52.130 225.760 ;
Expand Down Expand Up @@ -404,61 +404,61 @@ MACRO tt_um_devinatkin_fastreadout
LAYER li1 ;
RECT 2.760 2.635 332.120 223.125 ;
LAYER met1 ;
RECT 2.460 1.060 332.420 224.700 ;
RECT 2.460 1.740 332.420 224.700 ;
LAYER met2 ;
RECT 3.320 1.030 331.100 224.730 ;
RECT 4.230 1.710 330.640 224.730 ;
LAYER met3 ;
RECT 3.950 2.555 330.215 224.900 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.905 ;
RECT 8.370 224.360 10.950 224.905 ;
RECT 12.050 224.360 14.630 224.905 ;
RECT 15.730 224.360 18.310 224.905 ;
RECT 19.410 224.360 21.990 224.905 ;
RECT 23.090 224.360 25.670 224.905 ;
RECT 26.770 224.360 29.350 224.905 ;
RECT 30.450 224.360 33.030 224.905 ;
RECT 34.130 224.360 36.710 224.905 ;
RECT 37.810 224.360 40.390 224.905 ;
RECT 41.490 224.360 44.070 224.905 ;
RECT 45.170 224.360 47.750 224.905 ;
RECT 48.850 224.360 51.430 224.905 ;
RECT 52.530 224.360 55.110 224.905 ;
RECT 56.210 224.360 58.790 224.905 ;
RECT 59.890 224.360 62.470 224.905 ;
RECT 63.570 224.360 66.150 224.905 ;
RECT 67.250 224.360 69.830 224.905 ;
RECT 70.930 224.360 73.510 224.905 ;
RECT 74.610 224.360 77.190 224.905 ;
RECT 78.290 224.360 80.870 224.905 ;
RECT 81.970 224.360 84.550 224.905 ;
RECT 85.650 224.360 88.230 224.905 ;
RECT 89.330 224.360 91.910 224.905 ;
RECT 93.010 224.360 95.590 224.905 ;
RECT 96.690 224.360 99.270 224.905 ;
RECT 100.370 224.360 102.950 224.905 ;
RECT 104.050 224.360 106.630 224.905 ;
RECT 107.730 224.360 110.310 224.905 ;
RECT 111.410 224.360 113.990 224.905 ;
RECT 115.090 224.360 117.670 224.905 ;
RECT 118.770 224.360 121.350 224.905 ;
RECT 122.450 224.360 125.030 224.905 ;
RECT 126.130 224.360 128.710 224.905 ;
RECT 129.810 224.360 132.390 224.905 ;
RECT 133.490 224.360 136.070 224.905 ;
RECT 137.170 224.360 139.750 224.905 ;
RECT 140.850 224.360 143.430 224.905 ;
RECT 144.530 224.360 147.110 224.905 ;
RECT 148.210 224.360 150.790 224.905 ;
RECT 151.890 224.360 154.470 224.905 ;
RECT 155.570 224.360 158.150 224.905 ;
RECT 159.250 224.360 323.545 224.905 ;
RECT 3.975 223.680 323.545 224.360 ;
RECT 3.975 34.175 17.880 223.680 ;
RECT 20.280 34.175 94.680 223.680 ;
RECT 97.080 34.175 171.480 223.680 ;
RECT 173.880 34.175 248.280 223.680 ;
RECT 250.680 34.175 323.545 223.680 ;
RECT 3.950 2.555 327.070 224.225 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.760 ;
RECT 8.370 224.360 10.950 224.760 ;
RECT 12.050 224.360 14.630 224.760 ;
RECT 15.730 224.360 18.310 224.760 ;
RECT 19.410 224.360 21.990 224.760 ;
RECT 23.090 224.360 25.670 224.760 ;
RECT 26.770 224.360 29.350 224.760 ;
RECT 30.450 224.360 33.030 224.760 ;
RECT 34.130 224.360 36.710 224.760 ;
RECT 37.810 224.360 40.390 224.760 ;
RECT 41.490 224.360 44.070 224.760 ;
RECT 45.170 224.360 47.750 224.760 ;
RECT 48.850 224.360 51.430 224.760 ;
RECT 52.530 224.360 55.110 224.760 ;
RECT 56.210 224.360 58.790 224.760 ;
RECT 59.890 224.360 62.470 224.760 ;
RECT 63.570 224.360 66.150 224.760 ;
RECT 67.250 224.360 69.830 224.760 ;
RECT 70.930 224.360 73.510 224.760 ;
RECT 74.610 224.360 77.190 224.760 ;
RECT 78.290 224.360 80.870 224.760 ;
RECT 81.970 224.360 84.550 224.760 ;
RECT 85.650 224.360 88.230 224.760 ;
RECT 89.330 224.360 91.910 224.760 ;
RECT 93.010 224.360 95.590 224.760 ;
RECT 96.690 224.360 99.270 224.760 ;
RECT 100.370 224.360 102.950 224.760 ;
RECT 104.050 224.360 106.630 224.760 ;
RECT 107.730 224.360 110.310 224.760 ;
RECT 111.410 224.360 113.990 224.760 ;
RECT 115.090 224.360 117.670 224.760 ;
RECT 118.770 224.360 121.350 224.760 ;
RECT 122.450 224.360 125.030 224.760 ;
RECT 126.130 224.360 128.710 224.760 ;
RECT 129.810 224.360 132.390 224.760 ;
RECT 133.490 224.360 136.070 224.760 ;
RECT 137.170 224.360 139.750 224.760 ;
RECT 140.850 224.360 143.430 224.760 ;
RECT 144.530 224.360 147.110 224.760 ;
RECT 148.210 224.360 150.790 224.760 ;
RECT 151.890 224.360 154.470 224.760 ;
RECT 155.570 224.360 158.150 224.760 ;
RECT 159.250 224.360 261.905 224.760 ;
RECT 3.975 223.680 261.905 224.360 ;
RECT 3.975 39.615 17.880 223.680 ;
RECT 20.280 39.615 94.680 223.680 ;
RECT 97.080 39.615 171.480 223.680 ;
RECT 173.880 39.615 248.280 223.680 ;
RECT 250.680 39.615 261.905 223.680 ;
END
END tt_um_devinatkin_fastreadout
END LIBRARY
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