feat: update project tt_um_toivoh_retro_console from toivoh/tt06-retr…

…o-console

Commit: 7c88f17702e6267ea4456c2a439b454f4d8fc267
Workflow: https://github.com/toivoh/tt06-retro-console/actions/runs/8716562047

projects/tt_um_toivoh_retro_console/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt06 d5153c3f",
+  "app": "Tiny Tapeout tt06 eed83093",
   "repo": "https://github.com/toivoh/tt06-retro-console",
-  "commit": "ad26dcfc42597acdae97d6b4df9269ce35f185ea",
-  "workflow_url": "https://github.com/toivoh/tt06-retro-console/actions/runs/8694143321",
+  "commit": "7c88f17702e6267ea4456c2a439b454f4d8fc267",
+  "workflow_url": "https://github.com/toivoh/tt06-retro-console/actions/runs/8716562047",
   "sort_id": 1711967951372,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_toivoh_retro_console/docs/info.md

@@ -140,6 +140,97 @@ To choose which steps, the phase value is bit reversed and compared to the manti
 
 Each time a voice is switched in, five sweep values are read from memory to decide if the two frequencies and 3 control periods for the state variable filters (see https://github.com/toivoh/tt05-synth) should be swept up or down. A similar approach is used as above, with a clock divider for the exponent part of the sweep rate, and bit reversing the swept value to decide whether to take a small or a big step.
 
+## IO interfaces
+AnemoneGrafx-8 has four interfaces:
+- VGA output `uo` / `(R1, G1, B1, vsync, R0, G0, B0, hsync)`
+- Read-only memory interface `(addr_out[3:0], data_in[3:0])` for the PPU
+- Memory/host interface `(tx_out[1:0], rx_in[1:0])` for the synth, system control, and vblank events
+	- `rx_in[1:0] = uio[7:6]` can be remapped to `rx_in_alt[1:0] = ui[5:4]` to free up `uio[7:6]` for use as outputs
+- Additional video outputs `(Gm1_active_out, RBm1_pixelclk_out)`. Can output either
+	- Additional lower `RGB` bits to avoid having to dither the VGA output
+	- Active signal and pixel clock, useful for e g HDMI output
+
+Additionally
+- `data_in[0]` is sampled into `cfg[0]` as long as `rst_n` is high to choose the output mode
+	- `cfg[0] = 0`: `uio[7:6]` is used to input `rx_in[1:0]`,
+	- `cfg[0] = 1`: `uio[7:6]` is used to output `{RBm1_pixelclk_out, Gm1_active_out}`.
+- When the PPU is in reset (due to `rst_n` or `ppu_rst_n`), `addr_out` loops back the values from `data_in`, delayed by two register stages.
+
+### VGA output
+The VGA output follows the [Tiny VGA pinout](https://tinytapeout.com/specs/pinouts/#vga-output), giving two bits per channel.
+The PPU works with 8 bit color:
+
+	R = {R1, R0, RBm1}
+	G = {G1, G0, Gm1}
+	B = {B1, B0, RBm1}
+
+where the least significant bit it is identical between the red and blue channel.
+By default, dithering is used to reduce the output to 6 bit color (two bits per channel).
+Dithering can be disabled, and the low order color bits `{RBm1, Gm1}` be output on `{RBm1_pixelclk_out, Gm1_active_out}`.
+
+The other output option for `(Gm1_active_out, RBm1_pixelclk_out)` is to output the `active` and `pixelclk` signals:
+- `active` is high when the current RGB output pixel is in the active display area.
+- `pixelclk` has one period per VGA pixel (two clock cycles), and is high during the second clock cycle that the VGA pixel is valid.
+
+### Read-only memory interface
+The PPU uses the read-only memory interface to read video RAM. The interface handles only reads, but video RAM may be updated by means external to the console (and needs to, to make the output image change!).
+
+Each read sends a 16 bit word address and receives the 16 bit word at that address, allowing the PPU to access 128 kB of data.
+A read occurs during a _serial cycle_, or 4 clock cycles. As soon as one serial cycle is finished, the next one begins.
+
+The address `addr[15:0]` for one read is sent during the serial cycle in order of lowest bits to highest:
+
+	addr_out[3:0] = addr[3:0]   // cycle 0
+	addr_out[3:0] = addr[7:4]   // cycle 1
+	addr_out[3:0] = addr[11:8]  // cycle 2
+	addr_out[3:0] = addr[15:12] // cycle 3
+
+The corresponding `data[15:0]` should be sent in the same order to `data_out[3:0]` with a specific delay that is approximately three serial cycles (TODO: describe the exact delay needed!).
+The `data_in` to `addr_out` loopback function has been provided to help calibrate the required data delay.
+
+To respond correctly to reads requests, one must know when a serial cycle starts.
+This accomplished by an initial synchronization step:
+- After reset, `addr_pins` start at zero.
+- During the first serial cycle, a fixed address of `0x8421` is transmitted, and the corresponding data is discarded
+
+### Memory / host interface
+The memory / host interface is used to send a number of types messages and responses.
+It uses start bits to allow each side to initiate a message when appropriate, subsequent bits are sent on subsequent clock cycles.
+`tx_out` and `rx_in` are expected to remain low when no messages are sent.
+
+`tx_out[1:0]` is used for messages from the console:
+- a message is initiated with one cycle of `tx_out[1:0] = 1` (low bit set, high bit clear),
+- during the next cycle, `tx_out[1:0]` contains the 2 bit _tx header_, specifying the message type,
+- during the following 8 cycles, a 16 bit payload is sent through `tx_out[1:0]`, from lowest bits to highest.
+
+`rx_in[1:0]` is used for messages to the console:
+- a message is initiated with one cycle when `rx_in[1:0] != 0`, specifying the _rx header_, i e, the message type
+- during the following 8 cycles, a 16 bit payload is sent through `rx_in[1:0]`, from lowest bits to highest.
+
+TX message types:
+- 0: Context switch: Store payload into state vector, return the replaced state value (rx header=1), increment state pointer.
+- 1: Sample out: Payload is the next output sample from the synth, 16 bit signed.
+- 2: Read: Payload is address, return corresponding data (rx header=2).
+- 3: Vblank event. Payload should be ignored.
+
+The state pointer should wrap after 36 words.
+
+RX message types:
+- 1: Context switch response.
+- 2: Read response.
+- 3: Write register. Top byte of payload is register address, bottom is data value.
+
+Available registers:
+- 0: `sample_credits` (initial value 1)
+- 1: `sbio_credits` (initial value 1)
+- 2: `ppu_ctrl` (initial value `0b01011`)
+
+## Using the PPU
+The PPU is almost completely controlled through the VRAM (video RAM) contents.
+The copper is restarted when a new frame begins, and starts to read instructions at address `0xfffe`.
+
+
+
 ## How to test
 
 TODO

projects/tt_um_toivoh_retro_console/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_toivoh_retro_console,wokwi,flow completed,0h10m32s0ms,0h8m29s0ms,132546.6696614924,0.1148576576,66273.3348307462,64.61,70.2225,801.73,6601,0,0,0,0,0,0,0,1,1,0,-1,-1,185565,51404,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,119432348.0,0.0,54.36,46.51,13.37,5.98,-1,5112,8935,604,4381,0,0,0,5893,223,68,182,302,853,401,79,905,1196,1196,25,3317,1577,44,2525,7612,15075,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.84,47.98464491362764,19.84,1,50,153.18,153.6,0.3,1,10,0.68,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_toivoh_retro_console,wokwi,flow completed,0h11m2s0ms,0h8m48s0ms,132041.69680019663,0.1148576576,66020.84840009832,64.3,69.7091,780.58,6582,0,0,0,0,0,0,0,4,4,0,-1,-1,186063,51385,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,119673838.0,0.0,54.31,46.97,12.75,7.24,-1,5137,9005,609,4431,0,0,0,5913,224,68,180,307,851,405,75,905,1196,1196,25,3320,1577,27,2516,7583,15023,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.84,47.98464491362764,19.84,1,50,153.18,153.6,0.3,1,10,0.68,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_toivoh_retro_console/stats/synthesis-stats.txt

@@ -3,86 +3,89 @@
 
 === tt_um_toivoh_retro_console ===
 
-   Number of wires:               6585
-   Number of wire bits:           6620
+   Number of wires:               6566
+   Number of wire bits:           6601
    Number of public wires:        1228
    Number of public wire bits:    1263
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               6601
-     sky130_fd_sc_hd__a2111o_2       9
-     sky130_fd_sc_hd__a2111oi_2      2
-     sky130_fd_sc_hd__a211o_2       59
-     sky130_fd_sc_hd__a211oi_2       7
-     sky130_fd_sc_hd__a21bo_2       27
-     sky130_fd_sc_hd__a21boi_2       2
-     sky130_fd_sc_hd__a21o_2       152
-     sky130_fd_sc_hd__a21oi_2      136
-     sky130_fd_sc_hd__a221o_2      136
-     sky130_fd_sc_hd__a221oi_2       4
-     sky130_fd_sc_hd__a22o_2       165
-     sky130_fd_sc_hd__a22oi_2       23
-     sky130_fd_sc_hd__a2bb2o_2      18
-     sky130_fd_sc_hd__a311o_2       11
-     sky130_fd_sc_hd__a311oi_2       2
-     sky130_fd_sc_hd__a31o_2        64
-     sky130_fd_sc_hd__a31oi_2        5
-     sky130_fd_sc_hd__a32o_2        22
-     sky130_fd_sc_hd__a32oi_2        4
-     sky130_fd_sc_hd__a41o_2         1
-     sky130_fd_sc_hd__and2_2       217
-     sky130_fd_sc_hd__and2b_2       49
-     sky130_fd_sc_hd__and3_2       131
-     sky130_fd_sc_hd__and3b_2       31
-     sky130_fd_sc_hd__and4_2        21
-     sky130_fd_sc_hd__and4b_2        8
-     sky130_fd_sc_hd__and4bb_2       9
-     sky130_fd_sc_hd__buf_1       1164
+   Number of cells:               6582
+     sky130_fd_sc_hd__a2111o_2       6
+     sky130_fd_sc_hd__a2111oi_2      1
+     sky130_fd_sc_hd__a211o_2       48
+     sky130_fd_sc_hd__a211oi_2       8
+     sky130_fd_sc_hd__a21bo_2       24
+     sky130_fd_sc_hd__a21boi_2       4
+     sky130_fd_sc_hd__a21o_2       159
+     sky130_fd_sc_hd__a21oi_2      145
+     sky130_fd_sc_hd__a221o_2      130
+     sky130_fd_sc_hd__a221oi_2       2
+     sky130_fd_sc_hd__a22o_2       187
+     sky130_fd_sc_hd__a22oi_2        4
+     sky130_fd_sc_hd__a2bb2o_2      15
+     sky130_fd_sc_hd__a2bb2oi_2      1
+     sky130_fd_sc_hd__a311o_2        8
+     sky130_fd_sc_hd__a311oi_2       3
+     sky130_fd_sc_hd__a31o_2        63
+     sky130_fd_sc_hd__a31oi_2        6
+     sky130_fd_sc_hd__a32o_2        30
+     sky130_fd_sc_hd__a41o_2         5
+     sky130_fd_sc_hd__and2_2       226
+     sky130_fd_sc_hd__and2b_2       38
+     sky130_fd_sc_hd__and3_2       135
+     sky130_fd_sc_hd__and3b_2       26
+     sky130_fd_sc_hd__and4_2        24
+     sky130_fd_sc_hd__and4b_2        7
+     sky130_fd_sc_hd__and4bb_2       5
+     sky130_fd_sc_hd__buf_1       1145
      sky130_fd_sc_hd__buf_2          2
      sky130_fd_sc_hd__conb_1         6
      sky130_fd_sc_hd__dfxtp_2     1206
-     sky130_fd_sc_hd__inv_2        149
-     sky130_fd_sc_hd__mux2_2      1119
-     sky130_fd_sc_hd__mux4_2        15
-     sky130_fd_sc_hd__nand2_2      196
-     sky130_fd_sc_hd__nand2b_2       5
-     sky130_fd_sc_hd__nand3_2       19
+     sky130_fd_sc_hd__inv_2        160
+     sky130_fd_sc_hd__mux2_2      1089
+     sky130_fd_sc_hd__mux4_2        19
+     sky130_fd_sc_hd__nand2_2      213
+     sky130_fd_sc_hd__nand2b_2       7
+     sky130_fd_sc_hd__nand3_2       17
      sky130_fd_sc_hd__nand3b_2       9
-     sky130_fd_sc_hd__nand4_2        3
-     sky130_fd_sc_hd__nor2_2       346
+     sky130_fd_sc_hd__nand4_2        2
+     sky130_fd_sc_hd__nand4b_2       1
+     sky130_fd_sc_hd__nor2_2       335
      sky130_fd_sc_hd__nor2b_2        7
-     sky130_fd_sc_hd__nor3_2        36
-     sky130_fd_sc_hd__nor3b_2        4
+     sky130_fd_sc_hd__nor3_2        29
+     sky130_fd_sc_hd__nor3b_2        6
      sky130_fd_sc_hd__nor4_2         4
-     sky130_fd_sc_hd__nor4b_2        1
-     sky130_fd_sc_hd__o2111a_2       9
+     sky130_fd_sc_hd__nor4b_2        2
+     sky130_fd_sc_hd__o2111a_2       8
      sky130_fd_sc_hd__o2111ai_2      2
-     sky130_fd_sc_hd__o211a_2       53
-     sky130_fd_sc_hd__o211ai_2       7
+     sky130_fd_sc_hd__o211a_2       56
+     sky130_fd_sc_hd__o211ai_2       3
      sky130_fd_sc_hd__o21a_2       103
-     sky130_fd_sc_hd__o21ai_2       95
-     sky130_fd_sc_hd__o21ba_2       14
-     sky130_fd_sc_hd__o21bai_2       6
-     sky130_fd_sc_hd__o221a_2       35
+     sky130_fd_sc_hd__o21ai_2       81
+     sky130_fd_sc_hd__o21ba_2       12
+     sky130_fd_sc_hd__o21bai_2       8
+     sky130_fd_sc_hd__o221a_2       45
      sky130_fd_sc_hd__o221ai_2       3
-     sky130_fd_sc_hd__o22a_2        41
+     sky130_fd_sc_hd__o22a_2        39
      sky130_fd_sc_hd__o22ai_2        4
-     sky130_fd_sc_hd__o2bb2a_2      13
-     sky130_fd_sc_hd__o311a_2       14
-     sky130_fd_sc_hd__o31a_2        26
-     sky130_fd_sc_hd__o31ai_2        7
+     sky130_fd_sc_hd__o2bb2a_2      16
+     sky130_fd_sc_hd__o2bb2ai_2      1
+     sky130_fd_sc_hd__o311a_2       15
+     sky130_fd_sc_hd__o311ai_2       1
+     sky130_fd_sc_hd__o31a_2        25
+     sky130_fd_sc_hd__o31ai_2       10
      sky130_fd_sc_hd__o32a_2        11
-     sky130_fd_sc_hd__o41a_2         4
-     sky130_fd_sc_hd__or2_2        199
-     sky130_fd_sc_hd__or2b_2        28
+     sky130_fd_sc_hd__o41a_2         2
+     sky130_fd_sc_hd__or2_2        212
+     sky130_fd_sc_hd__or2b_2        43
      sky130_fd_sc_hd__or3_2         51
      sky130_fd_sc_hd__or3b_2        46
-     sky130_fd_sc_hd__or4_2         53
-     sky130_fd_sc_hd__or4b_2        10
-     sky130_fd_sc_hd__or4bb_2        3
-     sky130_fd_sc_hd__xnor2_2      103
-     sky130_fd_sc_hd__xor2_2        55
+     sky130_fd_sc_hd__or4_2         48
+     sky130_fd_sc_hd__or4b_2        15
+     sky130_fd_sc_hd__or4bb_2        1
+     sky130_fd_sc_hd__xnor2_2      116
+     sky130_fd_sc_hd__xor2_2        36
 
-   Chip area for module '\tt_um_toivoh_retro_console': 69963.350400
+   Chip area for module '\tt_um_toivoh_retro_console': 69631.782400
 

projects/tt_um_toivoh_retro_console/tt_um_toivoh_retro_console.lef

@@ -283,7 +283,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uio_out[1]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 55.510 224.760 55.810 225.760 ;
@@ -292,7 +292,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uio_out[2]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 51.830 224.760 52.130 225.760 ;
@@ -301,7 +301,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uio_out[3]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 48.150 224.760 48.450 225.760 ;
@@ -310,7 +310,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uio_out[4]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 44.470 224.760 44.770 225.760 ;
@@ -337,7 +337,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uio_out[7]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 33.430 224.760 33.730 225.760 ;
@@ -355,7 +355,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uo_out[1]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 84.950 224.760 85.250 225.760 ;
@@ -373,7 +373,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uo_out[3]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 77.590 224.760 77.890 225.760 ;
@@ -391,7 +391,7 @@ MACRO tt_um_toivoh_retro_console
   PIN uo_out[5]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 70.230 224.760 70.530 225.760 ;
@@ -461,11 +461,11 @@ MACRO tt_um_toivoh_retro_console
       LAYER li1 ;
         RECT 2.760 2.635 506.000 223.125 ;
       LAYER met1 ;
-        RECT 2.760 2.480 506.000 223.680 ;
+        RECT 2.760 2.480 506.390 224.020 ;
       LAYER met2 ;
-        RECT 4.700 2.535 504.520 224.925 ;
+        RECT 4.700 2.535 506.360 224.925 ;
       LAYER met3 ;
-        RECT 6.510 2.555 502.715 224.905 ;
+        RECT 6.510 2.555 503.175 224.905 ;
       LAYER met4 ;
         RECT 4.690 224.360 7.270 224.905 ;
         RECT 8.370 224.360 10.950 224.905 ;
@@ -509,15 +509,16 @@ MACRO tt_um_toivoh_retro_console
         RECT 148.210 224.360 150.790 224.905 ;
         RECT 151.890 224.360 154.470 224.905 ;
         RECT 155.570 224.360 158.150 224.905 ;
-        RECT 159.250 224.360 467.985 224.905 ;
-        RECT 3.990 223.680 467.985 224.360 ;
-        RECT 3.990 17.175 17.880 223.680 ;
-        RECT 20.280 17.175 94.680 223.680 ;
-        RECT 97.080 17.175 171.480 223.680 ;
-        RECT 173.880 17.175 248.280 223.680 ;
-        RECT 250.680 17.175 325.080 223.680 ;
-        RECT 327.480 17.175 401.880 223.680 ;
-        RECT 404.280 17.175 467.985 223.680 ;
+        RECT 159.250 224.360 496.505 224.905 ;
+        RECT 3.990 223.680 496.505 224.360 ;
+        RECT 3.990 19.215 17.880 223.680 ;
+        RECT 20.280 19.215 94.680 223.680 ;
+        RECT 97.080 19.215 171.480 223.680 ;
+        RECT 173.880 19.215 248.280 223.680 ;
+        RECT 250.680 19.215 325.080 223.680 ;
+        RECT 327.480 19.215 401.880 223.680 ;
+        RECT 404.280 19.215 478.680 223.680 ;
+        RECT 481.080 19.215 496.505 223.680 ;
   END
 END tt_um_toivoh_retro_console
 END LIBRARY