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synth: .sdc file is generated as part of synth
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just like the other stages

Signed-off-by: Øyvind Harboe <[email protected]>
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oharboe committed Oct 16, 2024
1 parent b6c618b commit ca29fc0
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Expand Up @@ -633,7 +633,6 @@ def _yosys_impl(ctx):
"do-yosys-keep-hierarchy",
"do-yosys",
"do-synth",
"/".join([_work_home(ctx), _artifact_name(ctx, "results", "1_synth.sdc")]),
],
command = " && ".join(commands),
env = _verilog_arguments([]) |
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