MDLL integration

MDLL will be provided as a hard macro while its simulation model and testbenches are/will be checked into this repository.

Enabling simulation

To simulate it properly, it is necessary to provide additional information to an RTL simulator, since the simulation model contains both behavioral model as well as gate-level structural model for some modules. To enable it, it is necessary to add SIMULATION text macro to run the simulation. There are multiple ways to provide this text macro. One is to add the following statement in some Verilog file (e.g., testbench):

`define SIMULATION

Another way is to add the macro text in the simulation argument. For example, one can add this xrun(or irun) argument:

+define+SIMULATION

Instantiation at the upper level

There are some pin naming rules for the integration, while there is an exception (rstn pin).

1. pins ending with "_jtag" : These pins are from JTAG registers.
2. pins ending with "_2jtag" : These pins are delivered to JTAG registers for read.
3. rstn : This reset pin is from JTAG register.
4. All other inputs : These inputs are fed from chip inputs.
5. clk_* : These output clock pins are 4 GHz, 4 phase clocks. Since the PI only needs one of them, three others can be remained unconnected.
6. jm_clk_fb_out : This pin is a clock output of which frequency is equal to the reference clock frequency to this MDLL. This pin is intended to measure the generated clock jitter on sampling oscilloscope. This will be fed into the core and muxed with other signals and the mux output will drive a digital output pad.