Verilator-compatible testbench, phase 2/2

.buildkite/ci.yml

@@ -58,10 +58,14 @@ steps:
   - docker run -id --name $CONTAINER --rm -v /cad:/cad $IMAGE bash
   - docker exec $CONTAINER /bin/bash -c "rm -rf /aha/garnet"
   - docker cp . $CONTAINER:/aha/garnet
+
+  # For quick test of verilator-compatible code, remove "echo if TEST" below
   - docker exec $CONTAINER /bin/bash -c "
       source /aha/bin/activate;
       source /cad/modules/tcl/init/sh;
       module load base incisive xcelium/19.03.003 vcs/Q-2020.03-SP2;
+      echo if TEST cp garnet/tests/test_app/dev/verilator-test.regress.py aha/util/regress.py;
+      echo aha regress pr;
       pwd; aha regress pr;
     "
 

tests/test_app/dev/README.txt

@@ -31,7 +31,9 @@ dev/README
 ------------------------------------------------------------------------
 VCS FULL GARNET RUN SEQUENCE (e.g. pointwise should finish within 8000ns)
 # Output to logs vcs.log<i>, simv.log<i>
-APP=+APP0=vfiles/pointwise
+# <generate top.sv, see below>
+head tb/top.sv
+APP=+APP0=pointwise; test -f pointwise/bin/design_meta.json || echo FAIL
 ivcs=$i; (vcs.sh |& tee vcs.log$ivcs; echo -n run | simv -lca -l simv.log$ivcs +vcs+initmem+0 +vcs+initreg+0 -sv_lib libcgra -exitstatus -ucli $APP) |& less
 # simv.log* should end with "PASS PASS PASS"
 # Check output file hw_output.txt vs. gold copy
@@ -50,17 +52,20 @@ gtkwave simv3.vcd
 
 ------------------------------------------------------------------------
 VERILATOR FULL GARNET RUN SEQUENCE (e.g. pointwise should finish within 8000ns)
+# <generate top.sv, see below>
 iver=$i; rmo; verilator.sh |& tee ver.log$iver
 make -C obj_dir/ -f Vtop.mk >& make-vtop.log$iver &
 tail -f make-vtop.log$iver | awk '{printf("%3d  %s %s\n", NR, $1, $NF)}' # Counts to 245 ish?
+APP=+APP0=pointwise; test -f pointwise/bin/design_meta.json || echo FAIL
 alias vtop='(echo Vtop 8000 "$APP"; obj_dir/Vtop 8000 "$APP")'
 vtop |& tee vtop.log$iver | less
 # vtop.log* should end with "PASS PASS PASS"
 
 # TRACE
+# <generate top.sv, see below>
 iver=$i; rmo; verilator.sh --trace |& tee ver.log$iver
 make -C obj_dir/ -f Vtop.mk >& make-vtop.log$iver &
-tail -f make-vtop.log$iver | awk '{printf("%3d  %s %s\n", NR, $1, $NF)}' # Counts to >> 245 ish?
+tail -f make-vtop.log$iver | awk '{printf("%3d  %s %s\n", NR, $1, $NF)}' # Counts to 1000 ish?
 alias vtop='(echo Vtop 8000 +trace "$APP"; obj_dir/Vtop 8000 +trace "$APP")'
 vtop |& tee vtop.log$iver | less
 gtkwave obj_dir/logs/vlt_dump.vcd
@@ -69,3 +74,26 @@ gtkwave obj_dir/logs/vlt_dump.vcd
 VERILATOR STUB RUN SEQUENCE
 # same as non-stub above except do this first:
 cp vfiles/garnet_stub.v vfiles/garnet.v
+
+------------------------------------------------------------------------
+GENERATE TOP.SV
+# Find or install Genesis2.pl
+source /home/steveri/bin/setup_genesis.sh
+
+# Clean up previous build
+cd $GARNET/tests/test_app
+ls -l genesis_clean.cmd
+cat genesis_clean.cmd
+genesis_clean.cmd
+
+# Generate top.sv from top.svp
+ls -l tb/top.*
+parms='-parameter top.using_matrix_unit=0 top.oc_0=0 top.mu_datawidth=0'
+Genesis2.pl -parse -generate -top top -input $gtb/top.svp $parms
+ls -l genesis_verif/top.sv
+ls -l tb/top.*
+mv genesis_verif/top.sv tb/top.sv
+ls -ld genesis*
+cat genesis_clean.cmd
+source genesis_clean.cmd
+ls -ld genesis*

tests/test_app/dev/pointwise/bin/design_meta.json

@@ -0,0 +1,90 @@
+{
+  "IOs": {
+    "inputs": [
+      {
+        "bitwidth": 16,
+        "datafile": "hw_input_stencil.raw",
+        "name": "hw_input_stencil",
+        "shape": [
+          64,
+          64
+        ],
+        "io_tiles": [
+          {
+            "name": "io16in_hw_input_stencil_op_hcompute_hw_input_global_wrapper_stencil_read_0",
+            "addr": {
+              "cycle_starting_addr": [
+                0
+              ],
+              "cycle_stride": [
+                1
+              ],
+              "dimensionality": 1,
+              "extent": [
+                4096
+              ],
+              "read_data_starting_addr": [
+                0
+              ],
+              "read_data_stride": [
+                1
+              ]
+            },
+            "mode": "STATIC",
+            "x_pos": 0,
+            "y_pos": 0
+          }
+        ]
+      }
+    ],
+    "outputs": [
+      {
+        "bitwidth": 16,
+        "datafile": "hw_output.raw",
+        "name": "hw_output_stencil",
+        "shape": [
+          64,
+          64
+        ],
+        "io_tiles": [
+          {
+            "name": "io16_hw_output_stencil_op_hcompute_hw_output_stencil_write_0",
+            "addr": {
+              "cycle_starting_addr": [
+                4
+              ],
+              "cycle_stride": [
+                1
+              ],
+              "dimensionality": 1,
+              "extent": [
+                4096
+              ],
+              "write_data_starting_addr": [
+                0
+              ],
+              "write_data_stride": [
+                1
+              ]
+            },
+            "mode": "VALID",
+            "x_pos": 1,
+            "y_pos": 0,
+            "valid_name": "hw_output_stencil"
+          }
+        ]
+      }
+    ]
+  },
+  "testing": {
+    "interleaved_input": [
+      "input.pgm"
+    ],
+    "interleaved_output": [
+      "gold.pgm"
+    ],
+    "bitstream": "pointwise.bs",
+    "coreir": "design_top.json",
+    "placement": "design.place"
+  }
+}

tests/test_app/dev/pointwise/bin/pointwise.bs

@@ -0,0 +1,67 @@
+000A0708 02800000
+000A0707 01000000
+000A0706 01000000
+000A0705 01000000
+000A0704 01000000
+000A0703 01000000
+010A0702 01000200
+000C0602 00800002
+010C0601 01000200
+010C0501 00040400
+010C0401 00040400
+010A0301 00040400
+010C0201 00040400
+000C0101 00800000
+010D0101 09002000
+000D0101 01000000
+010D0201 08000080
+010D0202 00001040
+000D0202 00000040
+010B0303 08000080
+010B0304 01000200
+010D0404 08000080
+010D0505 08000080
+000D0505 00000040
+010D0506 01001240
+010D0507 00041040
+000D0507 00800000
+00030608 0000000B
+000D0608 01800000
+010D0607 01000200
+010D0406 00040400
+000B0306 00800000
+000B0305 01000002
+010D0204 00040400
+000D0104 00800000
+000D0103 01000000
+000D0102 01000000
+020D0001 00008000
+010C0101 00040000
+010D0102 01000000
+010D0103 01000000
+010D0104 00040000
+020D0202 00008000
+020D0203 00008000
+020B0304 00008000
+010B0305 01000000
+010B0306 00040000
+020D0405 00008000
+020D0506 00008000
+020D0507 00008000
+020D0508 00008000
+010C0602 00040000
+010D0608 08000000
+010A0703 01000000
+010A0704 01000000
+010A0705 01000000
+010A0706 01000000
+010A0707 01000000
+28000708 000103E0
+27000708 7C000000
+26000708 00001000
+25000708 40001000
+24000708 10000000
+2E000708 00000300
+02000608 40004000
+01000608 00000835
+00000608 7FD00099

tests/test_app/dev/vcs.sh

@@ -50,7 +50,7 @@ WAVEFORM_ARGS="-debug_access+all -kdb +vpi +memcbk +vcsd"
 WAVEFORM_ARGS="-debug_access+all +vpi +memcbk +vcsd"
 
 
-/bin/rm -rf deleteme/{simv,csrc,simv.daidir}
+test -d deleteme && /bin/rm -rf deleteme/{simv,csrc,simv.daidir}
 mv simv csrc/ simv.daidir/ deleteme
 
 # //  $WAVEFORM_ARGS
@@ -70,6 +70,7 @@ test -e vfiles/garnet.v || (cd vfiles; gunzip -c garnet.v.gz > garnet.v)
 test -d tb || ln -s ../tb
 test -e libcgra.so || ln -s vfiles/libcgra.so
 
+set -x
 /bin/bash \
 vcs -sverilog -timescale=1ps/1ps -full64 -ldflags "-Wl,--no-as-needed" \
   -CFLAGS "-m64" -top top +vcs+lic+wait +vcs+initreg+random +overlap \

tests/test_app/dev/vfiles/global_buffer_param.svh

@@ -3,6 +3,7 @@
 package global_buffer_param;
 localparam int NUM_PRR = 4;
 localparam int NUM_CGRA_COLS = 8;
+localparam int NUM_CGRA_COLS_INCLUDING_IO = 8;
 localparam int NUM_GLB_TILES = 4;
 localparam int NUM_COLS_PER_GROUP = 4;
 localparam int BANKS_PER_TILE = 2;

tests/test_app/tb/CGRA.cpp

@@ -0,0 +1,96 @@
+// DESCRIPTION: Verilator: Verilog example module
+// See /usr/local/share/verilator/examples/make_tracing_c/sim_main.cpp
+//======================================================================
+
+// For std::unique_ptr
+#include <memory>
+
+// Include common routines
+#include <verilated.h>
+
+// Include model header, generated from Verilating "top.v"
+#include "Vtop.h"
+
+// Legacy function required only so linking works on Cygwin and MSVC++
+double sc_time_stamp() { return 0; }
+
+int main(int argc, char** argv) {
+
+    // '5000' means 5ns. Why? Maybe b/c timescale = 1ps/1ps
+    int ns = 1000;
+
+    // Sets MAX_NS if ANY cmd-line arg is found to be an integer (I'm so clever haha)
+    // E.g. "vtop 300" will run for 300ns and then end abruptly
+    int MAX_NS = 300*ns;
+    for (int i=1; i<argc; i++) {
+        int maybe_integer = atoi(argv[i]);
+        if (maybe_integer > 0) MAX_NS = maybe_integer;
+    }
+    // Create logs/ directory in case we have traces to put under it
+    Verilated::mkdir("logs");
+
+    // Construct a VerilatedContext to hold simulation time, etc.
+    // Multiple modules (made later below with Vtop) may share the same
+    // context to share time, or modules may have different contexts if
+    // they should be independent from each other.
+
+    // Using unique_ptr is similar to
+    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash
+
+    // Set debug level, 0 is off, 9 is highest presently used
+    // May be overridden by commandArgs argument parsing
+    contextp->debug(0);
+
+    // Randomization reset policy
+    // May be overridden by commandArgs argument parsing
+    contextp->randReset(0);  // 0: init to zero; 1: init to 1; 2: init to random
+
+    // Verilator must compute traced signals
+    contextp->traceEverOn(true);
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
+    // Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
+    // "TOP" will be the hierarchical name of the module.
+    const std::unique_ptr<Vtop> top{new Vtop{contextp.get(), "TOP"}};
+    /*
+    // Set Vtop's input signals
+    top->reset_l = !0;
+    top->clk = 0;
+    top->in_small = 1;
+    top->in_quad = 0x1234;
+    top->in_wide[0] = 0x11111111;
+    top->in_wide[1] = 0x22222222;
+    top->in_wide[2] = 0x3;
+    */
+
+    // Simulate until $finish                                             <
+    int i=-1;
+    while (!contextp->gotFinish()) {
+        i++; if (i > MAX_NS*ns) break;  // (Note "i" starts at -1)
+        top->eval();
+        contextp->timeInc(1);  // 1ps maybe
+    }
+
+    // Final model cleanup
+    top->final();
+
+    // Coverage analysis (calling write only after the test is known to pass)
+#if VM_COVERAGE
+    Verilated::mkdir("logs");
+    contextp->coveragep()->write("logs/coverage.dat");
+#endif
+
+    // Final simulation summary
+    contextp->statsPrintSummary();
+
+    // Return good completion status
+    // Don't use exit() or destructor won't get called
+    return 0;
+}