Fix feq nv

SpinalHDL · Apr 26, 2024 · 7b07ad3 · 7b07ad3
1 parent 2f4413e
commit 7b07ad3
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuCmpPlugin.scala
@@ -89,7 +89,7 @@ class FpuCmpPlugin(val layer : LaneLayer,
     val RS2_FP = fup(RS2)
 
     val onCmp = new layer.Execute(cmpAt) {
-      val signalQuiet = SEL_CMP && !LESS
+      val signalQuiet = SEL_CMP && LESS
       val rs1NanNv = RS1_FP.isNan && (!RS1_FP.quiet || signalQuiet)
       val rs2NanNv = RS2_FP.isNan && (!RS2_FP.quiet || signalQuiet)
       val NV = insert(rs1NanNv || rs2NanNv)