MicroSoC add XIP

SpinalHDL · Oct 31, 2024 · 09d76cc · 09d76cc
1 parent e1c584a
commit 09d76cc
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Showing 4 changed files with 48 additions and 11 deletions.
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
diff --git a/src/main/scala/spinal/lib/misc/Elf.scala b/src/main/scala/spinal/lib/misc/Elf.scala
@@ -67,6 +67,25 @@ class Elf(val f : File, addressWidth : Int){
     initContent
   }
 
+  def load(func : (Long, Byte) => Unit) : Unit = {
+    foreachSection { section =>
+      if ((section.header.sh_flags & ElfSectionHeader.FLAG_ALLOC) != 0) {
+        val data = getData(section)
+        val memoryAddress = (section.header.sh_addr) & ((BigInt(1) << addressWidth) - 1).toLong
+        for((byte, i) <- data.zipWithIndex){
+          func(memoryAddress+i, byte)
+        }
+      }
+    }
+  }
+
+  def loadArray(array : Array[Byte], offset : Long, allowOverflow: Boolean = false) : Unit = {
+    load{(address, data) =>
+      if(address > offset && address  < offset + array.size) array(address - offset toInt) = data
+      else assert(!allowOverflow)
+    }
+  }
+
   def init[T <: Data](ram: Mem[T], offset: BigInt, allowOverflow: Boolean = false): Unit = {
     val initContent = getMemInit(ram, offset, allowOverflow)
     ram.initBigInt(initContent)

diff --git a/src/main/scala/vexiiriscv/soc/micro/MicroSoc.scala b/src/main/scala/vexiiriscv/soc/micro/MicroSoc.scala
@@ -5,9 +5,12 @@ import spinal.core.fiber.Fiber
 import spinal.lib._
 import spinal.lib.bus.tilelink
 import spinal.lib.bus.tilelink.fabric.Node
+import spinal.lib.com.spi.ddr.{SpiXdrMasterCtrl, SpiXdrParameter}
+import spinal.lib.com.spi.xdr.TilelinkSpiXdrMasterFiber
 import spinal.lib.com.uart.TilelinkUartFiber
 import spinal.lib.misc.{Elf, TilelinkClintFiber}
 import spinal.lib.misc.plic.TilelinkPlicFiber
+import spinal.lib.system.tag.MemoryConnection
 import vexiiriscv.soc.TilelinkVexiiRiscvFiber
 
 
@@ -53,9 +56,18 @@ class MicroSoc(p : MicroSocParam) extends Component {
       uart.node at 0x10001000 of bus32
       plic.mapUpInterrupt(1, uart.interrupt)
 
+      val spi = new TilelinkSpiXdrMasterFiber(SpiXdrMasterCtrl.MemoryMappingParameters(
+        SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
+        xipEnableInit = true,
+        xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, lengthWidth = 6)
+      ))
+      plic.mapUpInterrupt(2, spi.interrupt)
+      spi.ctrl at 0x10002000 of bus32
+      spi.xip at 0x20000000 of bus32
+
       val demo = p.demoPeripheral.map(new PeripheralDemoFiber(_){
-        node at 0x10002000 of bus32
-        plic.mapUpInterrupt(2, interrupt)
+        node at 0x10003000 of bus32
+        plic.mapUpInterrupt(3, interrupt)
       })
 
       val cpuPlic = cpu.bind(plic)
@@ -64,6 +76,7 @@ class MicroSoc(p : MicroSocParam) extends Component {
 
     val patcher = Fiber patch new Area{
       p.ramElf.foreach(new Elf(_, p.vexii.xlen).init(ram.thread.logic.mem, 0x80000000l))
+      println(MemoryConnection.getMemoryTransfers(cpu.dBus).mkString("\n"))
     }
   }
 }
diff --git a/src/main/scala/vexiiriscv/soc/micro/MicroSocSim.scala b/src/main/scala/vexiiriscv/soc/micro/MicroSocSim.scala
@@ -4,6 +4,7 @@ import rvls.spinal.RvlsBackend
 import spinal.core._
 import spinal.core.sim._
 import spinal.core.fiber._
+import spinal.lib.com.spi.sim.FlashModel
 import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
 import spinal.lib.misc.Elf
 import vexiiriscv.test.VexiiRiscvProbe
@@ -18,15 +19,15 @@ import java.io.File
 object MicroSocSim extends App{
   var traceKonata = false
   var withRvlsCheck = false
-  var elf: File = null
+  var elfFile: File = null
   val sim = SimConfig
   var speedPrinterPeriod = Option.empty[Double]
   sim.withTimeSpec(1 ns, 1 ps)
   val p = new MicroSocParam()
 
   assert(new scopt.OptionParser[Unit]("VexiiRiscv") {
     help("help").text("prints this usage text")
-    opt[String]("load-elf") action { (v, c) => elf = new File(v) }
+    opt[String]("load-elf") action { (v, c) => elfFile = new File(v) }
     opt[Unit]("trace-konata") action { (v, c) => traceKonata = true }
     opt[Unit]("check-rvls") action { (v, c) => withRvlsCheck = true }
     opt[Double]("speed-printer") action { (v, c) => speedPrinterPeriod = Some(v) }
@@ -35,12 +36,12 @@ object MicroSocSim extends App{
   }.parse(args, Unit).nonEmpty)
   p.legalize()
 
-
-  sim.compile(new MicroSoc(p){
+  class MicroSocSim extends MicroSoc(p){
     Fiber patch{
       system.ram.thread.logic.mem.simPublic()
     }
-  }).doSimUntilVoid("test", seed = 42){dut =>
+  }
+  sim.compile(new MicroSocSim).doSimUntilVoid("test", seed = 42){dut =>
     dut.socCtrl.systemClkCd.forkStimulus()
     dut.socCtrl.asyncReset #= true
     delayed(100 ns)(dut.socCtrl.asyncReset #= false)
@@ -57,6 +58,8 @@ object MicroSocSim extends App{
       baudPeriod = uartBaudPeriod
     )
 
+    val flash = new FlashModel(dut.system.peripheral.spi.logic.spi, dut.socCtrl.system.cd)
+
     val konata = traceKonata.option(
       new vexiiriscv.test.konata.Backend(new File(currentTestPath, "konata.log")).spinalSimFlusher(hzToLong(1000 Hz))
     )
@@ -75,9 +78,11 @@ object MicroSocSim extends App{
     }
 
 
-    if(elf != null) {
-      new Elf(elf, p.vexii.xlen).load(dut.system.ram.thread.logic.mem, 0x80000000l)
-      probe.backends.foreach(_.loadElf(0, elf))
+    if(elfFile != null) {
+      val elf = new Elf(elfFile, p.vexii.xlen)
+      elf.load(dut.system.ram.thread.logic.mem, 0x80000000l, true)
+      elf.loadArray(flash.content, 0x20000000l, true)
+      probe.backends.foreach(_.loadElf(0, elfFile))
     }
   }
 }