[AMDGPU] Correct assert that incorrectly chained multiple == operator…

…s. (llvm#70291) Change-Id: I19593c4b93f4f3e1820e692a52d26e7e8866c5cf
ROCm · Mar 13, 2024 · f94d08e · f94d08e
1 parent dd8a974
commit f94d08e
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1127,8 +1127,8 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
   unsigned MFMACount = 0;
   unsigned DSRCount = 0;
 
-  assert((IsPostRA ||
-          DSWCount == DSWWithPermCount == DSWWithSharedVMEMCount == 0) &&
+  assert((IsPostRA || (DSWCount == 0 && DSWWithPermCount == 0 &&
+                       DSWWithSharedVMEMCount == 0)) &&
          "DSWCounters should be zero in pre-RA scheduling!");
   SmallVector<SUnit *, 6> DSWithPerms;
   for (auto &SU : DAG->SUnits) {