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replace panics
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@Qazalin
Qazalin committed Jun 28, 2024
1 parent d6b46ba commit e2ff01c
Showing 1 changed file with 22 additions and 22 deletions.
44 changes: 22 additions & 22 deletions src/thread.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ impl<'a> Thread<'a> {
let s0 = self.val(src);
let ret = match op {
1 => s0,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
self.scalar_reg.write64(sdst as usize, ret);
}
Expand Down Expand Up @@ -111,7 +111,7 @@ impl<'a> Thread<'a> {
32 => s0 & saveexec,
34 => s0 | saveexec,
48 => s0 & !saveexec,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
*self.scc = (self.exec.value != 0) as u32;
saveexec
Expand Down Expand Up @@ -272,7 +272,7 @@ impl<'a> Thread<'a> {
23 => s0 & s1,
25 => s0 | s1,
27 => s0 ^ s1,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
self.scalar_reg.write64(sdst as usize, ret);
*self.scc = (ret != 0) as u32;
Expand Down Expand Up @@ -318,7 +318,7 @@ impl<'a> Thread<'a> {
let ret = match op {
0 => s0 + s1,
4 => s0 + s1 + *self.scc as u64,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
(ret as u32, Some(ret >= 0x100000000))
}
Expand All @@ -333,7 +333,7 @@ impl<'a> Thread<'a> {
let ret = match op {
2 => s0 + s1,
3 => s0 - s1,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
let overflow = (nth(s0 as u32, 31) == nth(s1 as u32, 31))
&& (nth(s0 as u32, 31) != nth(ret as u32, 31));
Expand All @@ -355,7 +355,7 @@ impl<'a> Thread<'a> {
18 => (s0 as i32) < (s1 as i32),
19 => s0 < s1,
20 => (s0 as i32) > (s1 as i32),
_ => panic!(),
_ => todo_instr!(instruction)?,
};
let ret = match scc {
true => s0,
Expand Down Expand Up @@ -517,7 +517,7 @@ impl<'a> Thread<'a> {
match op {
33 => (self.vec_reg[vdst] & 0xffff0000) | (ret as u32),
34 => (self.vec_reg[vdst] & 0x0000ffff) | ((ret as u32) << 16),
_ => panic!(),
_ => todo_instr!(instruction)?,
}
}
_ => todo_instr!(instruction)?,
Expand Down Expand Up @@ -618,7 +618,7 @@ impl<'a> Thread<'a> {
47 => 1.0 / s0,
49 => 1.0 / f64::sqrt(s0),
61 => extract_mantissa(s0),
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg.write64(vdst, ret.to_bits())
Expand All @@ -638,15 +638,15 @@ impl<'a> Thread<'a> {
false => (s0.exponent() as i32 - 1023 + 1) as u32,
}
}
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg[vdst] = ret;
}
}
}
}
_ => panic!(),
_ => todo_instr!(instruction)?,
}
}
84..=97 => {
Expand All @@ -670,7 +670,7 @@ impl<'a> Thread<'a> {
4 => (s0 as i32 as f64).to_bits(),
22 => (s0 as f64).to_bits(),
16 => (f32::from_bits(s0) as f64).to_bits(),
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg.write64(vdst, ret)
Expand Down Expand Up @@ -712,7 +712,7 @@ impl<'a> Thread<'a> {
42 => 1.0 / s0,
43 => 1.0 / s0,
51 => f32::sqrt(s0),
_ => panic!(),
_ => todo_instr!(instruction)?,
}
.to_bits()
}
Expand Down Expand Up @@ -938,7 +938,7 @@ impl<'a> Thread<'a> {
43 => f32::mul_add(s0, s1, f32::from_bits(self.vec_reg[vdst])),
44 => f32::mul_add(s0, f32::from_bits(self.simm()), s1),
45 => f32::mul_add(s0, s1, f32::from_bits(self.simm())),
_ => panic!(),
_ => todo_instr!(instruction)?,
}
.to_bits()
}
Expand All @@ -952,7 +952,7 @@ impl<'a> Thread<'a> {
(match op {
18 => i32::max(s0, s1),
26 => s1 >> s0,
_ => panic!(),
_ => todo_instr!(instruction)?,
}) as u32
}
32 => {
Expand All @@ -964,7 +964,7 @@ impl<'a> Thread<'a> {
let temp = match op {
33 => s0 - s1 - self.vcc.read() as u32,
34 => s1 - s0 - self.vcc.read() as u32,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
self.vcc
.set_lane((s1 as u64 + self.vcc.read() as u64) > s0 as u64);
Expand Down Expand Up @@ -1221,11 +1221,11 @@ impl<'a> Thread<'a> {
assert!(!self.vcc.read());
f64::mul_add(s0, s1, s2)
}
_ => panic!(),
_ => todo_instr!(instruction)?,
}
.to_bits()
}
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg.write64(vdst, ret)
Expand All @@ -1244,7 +1244,7 @@ impl<'a> Thread<'a> {
596 => s2 / s1,
313 => f16::max(s0, s1),
314 => f16::min(s0, s1),
_ => panic!(),
_ => todo_instr!(instruction)?,
}
.to_bits();
if self.exec.read() {
Expand Down Expand Up @@ -1306,7 +1306,7 @@ impl<'a> Thread<'a> {
779 => u16::max(s0, s1),
824 => s1 << s0,
825 => s1 >> s0,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg[vdst].mut_lo16(ret);
Expand All @@ -1320,7 +1320,7 @@ impl<'a> Thread<'a> {
780 => i16::min(s0, s1),
781 => s0 + s1,
782 => s0 - s1,
_ => panic!(),
_ => todo_instr!(instruction)?,
};
if self.exec.read() {
self.vec_reg[vdst].mut_lo16(ret as u16);
Expand Down Expand Up @@ -1367,7 +1367,7 @@ impl<'a> Thread<'a> {
}
}
392 => f32::from_bits(s0 as i32 as u32),
_ => panic!(),
_ => todo_instr!(instruction)?,
}
.to_bits()
}
Expand Down Expand Up @@ -1404,7 +1404,7 @@ impl<'a> Thread<'a> {
}
}
814 => ((s0 as i64) * (s1 as i64) >> 32) as i32,
_ => panic!(),
_ => todo_instr!(instruction)?,
}) as u32
}
283 => s0 & s1,
Expand Down

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