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isa.md

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ISA

Data types

type suffix format description
matrix .m 4x4 array of FP16 The matrix data type for the systolic array
int .i 32 bit signed integer

Integer Instructions

Instr Type Name Description Opcode
add.i R ADD rd = rs1 + rs2 0b0110011
sub.i R SUB rd = rs1 - rs2 0b0110011
xor.i R XOR rd = rs1 ^ rs2 0b0110011
or.i R OR rd = rs1 OR rs2 0b0110011
and.i R AND rd = rs1 & rs2 0b0110011
sll.i R Shift Left Logical rd = rs1 << rs2 0b0110011
srl.i R Shift Right Logical rd = rs1 >> rs2 0b0110011
sra.i R Shift Right Arith rd = rs1 >> rs2 0b0110011
slt.i R Set Less Than rd = (rs1 < rs2)?1:0 0b0110011
sltu.i R Set Less Than (U) rd = (rs1 < rs2)?1:0 0b0110011
mul.i R Multiply rd = (rs1 * rs2)[31:0] 0b0110011
mov.i R Move rd = rs1 !NOT IN RISCV SPEC! 0b0110011
addi.i I ADD Immediate rd = rs1 + imm 0b0010011
xori.i I XOR Immediate rd = rs1 ^ imm 0b0010011
ori.i I OR Immediate rd = rs1 OR imm 0b0010011
andi.i I AND Immediate rd = rs1 & imm 0b0010011
slli.i I Shift Left Logical Imm rd = rs1 << imm[0:4] 0b0010011
srli.i I Shift Right Logical Imm rd = rs1 >> imm[0:4] 0b0010011
srai.i I Shift Right Arith Imm rd = rs1 >> imm[0:4] 0b0010011
slti.i I Set Less Than Imm rd = (rs1 < imm)?1:0 0b0010011
sltui.i I Set Less Than Imm (U) rd = (rs1 < imm)?1:0 0b0010011
beq.i B Branch == B if(rs1 == rs2) PC += imm 0b1100011
bne.i B Branch != B if(rs1 != rs2) PC += imm 0b1100011
blt.i B Branch < B if(rs1 < rs2) PC += imm 0b1100011
bge.i B Branch ≥ B if(rs1 >= rs2) PC += imm 0b1100011
lw.i I Load Word rd = M[rs1 + imm] 0b0000011
lui.i U Load Upper Imm rd = imm << 12 0b0110111
sw.i S Store Word M[rs1 + imm] = rd 0b0100011
jal UJ Jump And Link rd = PC+4; PC += imm 0b1101111
jalr I Jump And Link Reg rd = PC+4; PC = rs1 + imm 0b1100111

Matrix Instructions

Instr Type Name Description Opcode
ld.m M Load Matrix md = M[rs1 + imm] 0b1000111
st.m M Store Matrix M[rs1 + imm] = md 0b1010111
gemm.m GEMM Matrix Multiply md = ma @ mb + mc 0b1110111

Psuedo-instructions

Instr Name Description Uses
LI Load Immediate R[rd] = imm lui.i + addi.i
MV Move R[rd] = R[rs1] addi.i
RET Return PC = R[1] jalr
PUSH Stack push sp = sp - 4; M[sp] <= R[rs1] sub.i + sw.i
POP Stack pop sp = sp + 4; R[rs2] <= M[sp] add.i + lw.i
NOP No operation addi.i
HALT halt

Instruction Formats

31 - 25 24 - 20 19 - 15 14 - 12 11 - 7 6 - 0
R funct7 rs2 rs1 funct3 rd opcode
I imm[11:0] rs1 funct3 rd opcode
S imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
B imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
U imm[31:12] rd opcode
UJ imm[20|10:1|11|19:12] rd opcode
31 - 28 27 - 24 23 - 20 19 - 16 15 - 7 6 - 0
GEMM rd ra rb rc reserved opcode meaningless register names
31 - 28 27 - 23 22 - 18 17 - 7 6 - 0
M rd rs1 stride Imm[10:0] opcode

Register Allocation

Register Name Use Saver
x0 zero Constant 0
x1 ra Return Address Caller
x2 sp Stack Pointer Callee
x3-x31 Free
m0 mzero Zero Matrix
m1-m15 Free