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nxstyle fixes
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@PetervdPerk-NXP
PetervdPerk-NXP committed Dec 4, 2023
1 parent 2fe0be7 commit 57e12a3
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Showing 15 changed files with 69 additions and 27 deletions.
1 change: 0 additions & 1 deletion arch/arm/src/imxrt/hardware/imxrt_adc.h
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Expand Up @@ -32,5 +32,4 @@
#include "imxrt_adc_ver1.h"
#endif


#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H */
1 change: 0 additions & 1 deletion arch/arm/src/imxrt/hardware/imxrt_flexspi.h
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Expand Up @@ -102,7 +102,6 @@ struct flexspi_type_s
#define IMXRT_FLEXSPI2_AHBBUFREGIONSTART3 (IMXRT_FLEXSPI2C_BASE + IMXRT_FLEXSPI_AHBBUFREGIONSTART3_OFFSET)
#define IMXRT_FLEXSPI2_AHBBUFREGIONEND3 (IMXRT_FLEXSPI2C_BASE + IMXRT_FLEXSPI_AHBBUFREGIONEND3_OFFSET)


/* MCR0 - Module Control Register 0 */

#define FLEXSPI_MCR0_SWRESET_MASK (0x1u)
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12 changes: 6 additions & 6 deletions arch/arm/src/imxrt/hardware/imxrt_ocotp.h
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Expand Up @@ -279,12 +279,12 @@
/* 64 Bit unique id consisting of:
* LOT_NO_ENC[42:0] 42 bits LOT ID
* IMXRT_OCOTP_UNIQUE_ID_MSB[31:0] IMXRT_OCOTP_UNIQUE_ID_LSB[10:0]
* WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device was fabricated
* IMXRT_OCOTP_UNIQUE_ID_LSB[15:11]
* DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location on the wafer
* IMXRT_OCOTP_UNIQUE_ID_LSB[23:16]
* DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location on the wafer
* IMXRT_OCOTP_UNIQUE_ID_LSB[31:24]
* WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device
* was fabricated IMXRT_OCOTP_UNIQUE_ID_LSB[15:11]
* DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location
* on the wafer IMXRT_OCOTP_UNIQUE_ID_LSB[23:16]
* DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location
* on the wafer IMXRT_OCOTP_UNIQUE_ID_LSB[31:24]
*/
#define IMXRT_OCOTP_UNIQUE_ID_MSB (IMXRT_OCOTP_CFG0) /* Most Significant Bytes of 64 bit UUID */
#define IMXRT_OCOTP_UNIQUE_ID_LSB (IMXRT_OCOTP_CFG1) /* Least Significant Bytes of 64 bit UUID */
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3 changes: 2 additions & 1 deletion arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h
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Expand Up @@ -257,7 +257,8 @@
#define CCM_CG_CTRL_RSTDIV_SHIFT (16) /* Bits 16-23: Clock group global restart count (RSTDIV) */
#define CCM_CG_CTRL_RSTDIV_MASK (0xff << CCM_CG_CTRL_RSTDIV_SHIFT)
# define CCM_CG_CTRL_RSTDIV(n) (((n)-1) << CCM_CG_CTRL_RSTDIV_SHIFT) /* Divide selected clock by n */
#define CCM_CG_CTRL_OFF (1 << 24) /* Bit 24: Shutdown all clocks in clock group (OFF) */
#define CCM_CG_CTRL_OFF (1 << 24)
/* Bit 24: Shutdown all clocks in clock group (OFF) */
/* Bits 25-31: Reserved */

/* Clock group working status (CLOCK_GROUPn_STATUS0, n=0..1) */
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4 changes: 2 additions & 2 deletions arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h
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Expand Up @@ -79,8 +79,8 @@
/* 64 Bit unique id consisting of:
* LOT_NO_ENC[42:0] 42 bits LOT ID
* IMXRT_OCOTP_UNIQUE_ID_MSB[31:0] IMXRT_OCOTP_UNIQUE_ID_LSB[10:0]
* WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device was fabricated
* IMXRT_OCOTP_UNIQUE_ID_LSB[15:11]
* WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device
* was fabricated IMXRT_OCOTP_UNIQUE_ID_LSB[15:11]
* DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location on the wafer
* IMXRT_OCOTP_UNIQUE_ID_LSB[23:16]
* DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location on the wafer
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4 changes: 4 additions & 0 deletions arch/arm/src/imxrt/imxrt102x_gpio.c
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Expand Up @@ -187,3 +187,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
g_gpio5_padmux, /* GPIO5 */
NULL /* End of list */
};

/****************************************************************************
* Public Functions
****************************************************************************/
4 changes: 4 additions & 0 deletions arch/arm/src/imxrt/imxrt105x_gpio.c
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Expand Up @@ -226,3 +226,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
g_gpio5_padmux, /* GPIO5 */
NULL /* End of list */
};

/****************************************************************************
* Public Functions
****************************************************************************/
4 changes: 4 additions & 0 deletions arch/arm/src/imxrt/imxrt106x_gpio.c
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Expand Up @@ -239,3 +239,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
g_gpio4_padmux, /* GPIO9 */
NULL /* End of list */
};

/****************************************************************************
* Public Functions
****************************************************************************/
4 changes: 4 additions & 0 deletions arch/arm/src/imxrt/imxrt117x_gpio.c
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Expand Up @@ -546,3 +546,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
g_gpio13_padmux, /* GPIO13 */
NULL /* End of list */
};

/****************************************************************************
* Public Functions
****************************************************************************/
30 changes: 30 additions & 0 deletions arch/arm/src/imxrt/imxrt117x_mpuinit.c
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Expand Up @@ -52,7 +52,9 @@
putreg32(regval, MPU_RASR);

mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -62,7 +64,9 @@
);

mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -72,7 +76,9 @@
);

mpu_configure_region(IMXRT_ITCM_BASE, 1 * 1024 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -82,7 +88,9 @@
);

mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR /* Normal */
/* Not Cacheable */
Expand All @@ -92,7 +100,9 @@
);

mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR /* Normal */
/* Not Cacheable */
Expand All @@ -102,7 +112,9 @@
);

mpu_configure_region(IMXRT_OCRAM_M4_BASE, 1 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_SO | /* Strongly Ordered */
RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
Expand All @@ -112,7 +124,9 @@
);

mpu_configure_region(IMXRT_OCRAM_M4_BASE + (1 * 1024 * 1024), 512 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_SO | /* Strongly Ordered */
RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
Expand All @@ -122,7 +136,9 @@
);

mpu_configure_region(IMXRT_FLEXSPI1_CIPHER_BASE, 16 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_SO | /* Strongly Ordered */
MPU_RASR_C | /* Cacheable */
Expand All @@ -132,7 +148,9 @@
);

mpu_configure_region(IMXRT_AIPS1_BASE, 16 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -142,7 +160,9 @@
);

mpu_configure_region(IMXRT_SIM_DISP_BASE, 2 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -152,7 +172,9 @@
);

mpu_configure_region(IMXRT_SIM_M7_BASE, 1 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -162,7 +184,9 @@
);

mpu_configure_region(IMXRT_GPU2D_BASE, 2 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
Expand All @@ -172,11 +196,17 @@
);

mpu_configure_region(IMXRT_AIPS_M7_BASE, 1 * 1024 * 1024,

/* Instruction access Enabled */

MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device */
/* Not Cacheable */
/* Not Bufferable */
/* Not Shareable */
/* No Subregion disable */
);

/****************************************************************************
* Public Functions
****************************************************************************/
2 changes: 1 addition & 1 deletion arch/arm/src/imxrt/imxrt_adc_ver1.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/imxrt/imxrt_adc_var1.c
* arch/arm/src/imxrt/imxrt_adc_ver1.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
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3 changes: 2 additions & 1 deletion arch/arm/src/imxrt/imxrt_clockconfig_ver2.c
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Expand Up @@ -127,8 +127,9 @@ static void imxrt_oscsetup(void)
putreg32(reg, IMXRT_CCM_CR_CTRL(8));

/* FlexRAM AXI CLK ROOT */
putreg32(CCM_CG_CTRL_RSTDIV(1) | CCM_CG_CTRL_DIV0(1), IMXRT_CCM_CG_CTRL(0));

putreg32(CCM_CG_CTRL_RSTDIV(1) | CCM_CG_CTRL_DIV0(1),
IMXRT_CCM_CG_CTRL(0));
}

/****************************************************************************
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5 changes: 3 additions & 2 deletions arch/arm/src/imxrt/imxrt_enet.c
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Expand Up @@ -200,8 +200,7 @@
# error "Need at least one RX buffer"
#endif

/*
* From ref manual TDSR/RDSR description
/* From ref manual TDSR/RDSR description
* For optimal performance the pointer should be 512-bit aligned, that is,
* evenly divisible by 64.
*/
Expand Down Expand Up @@ -739,6 +738,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv)

#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
/* Make sure that descriptors are flushed */

ARM_DSB();
#else
up_clean_dcache((uintptr_t)txdesc,
Expand Down Expand Up @@ -1424,6 +1424,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)

#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
/* Make sure that descriptors are flushed */

ARM_DSB();
#endif

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16 changes: 6 additions & 10 deletions arch/arm/src/imxrt/imxrt_gpio.c
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Expand Up @@ -38,16 +38,6 @@
#include "imxrt_gpio.h"
#include "hardware/imxrt_daisy.h"

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

#define IMXRT_PADMUX_INVALID 255

/****************************************************************************
* Private Data
****************************************************************************/

#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
# include "imxrt102x_gpio.c"
#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
Expand All @@ -60,6 +50,12 @@
# error Unrecognized i.MX RT architecture
#endif

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

#define IMXRT_PADMUX_INVALID 255

/****************************************************************************
* Public Data
****************************************************************************/
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3 changes: 1 addition & 2 deletions arch/arm/src/imxrt/imxrt_iomuxc_ver2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -528,7 +528,7 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
}
else if (padctl <= IMXRT_PADCTL_GPIO_DISP_B1_11)
{
/* GPIO_DISP_B1 *********************************************************/
/* GPIO_DISP_B1 *******************************************************/

/* Select drive strength */

Expand Down Expand Up @@ -631,7 +631,6 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
else
{
regval &= ~(PADCTL_DISP_B2_ODE);

}
}
else if (padctl <= IMXRT_PADCTL_GPIO_LPSR_15)
Expand Down

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