Moved files names and folders

Mazamars312 · Dec 5, 2022 · 3a19cd3 · 3a19cd3
1 parent 3a7909b
commit 3a19cd3
Show file tree

Hide file tree

Showing 15 changed files with 58 additions and 4,847 deletions.
diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf
@@ -732,64 +732,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_1wire
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spiclk
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spimiso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bridge_spimosi
-set_global_assignment -name VERILOG_FILE core/wrapper/VexRiscv.v
-set_global_assignment -name VERILOG_FILE core/i2s.v
-set_global_assignment -name VHDL_FILE core/wrapper/simple_uart.vhd
-set_global_assignment -name VERILOG_FILE core/wrapper/substitute_mcu_apf.v
-set_global_assignment -name VERILOG_FILE core/wrapper/controller_rom.v
-set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/sync_fifo.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/sound_i2s.sv"
-set_global_assignment -name VERILOG_FILE "core/analogue-pocket-utils/ip/hex_loader.v"
-set_global_assignment -name VERILOG_FILE "core/analogue-pocket-utils/ip/debug_key.v"
-set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/data_unloader.sv"
-set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/data_loader.sv"
-set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68KdotC_Kernel.vhd
-set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K_Pack.vhd
-set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K_ALU.vhd
-set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K.vhd
-set_global_assignment -name QIP_FILE core/amiga/tg68k/TG68K.qip
-set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/hps_ext.v
-set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109tx.v
-set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109rx.v
-set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109.v
-set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/vexriscv/vexriscv_wrapper.v
-set_global_assignment -name VERILOG_FILE core/amiga/userio.v
-set_global_assignment -name VERILOG_FILE core/amiga/rtg.v
-set_global_assignment -name VERILOG_FILE core/amiga/minimig_syscontrol.v
-set_global_assignment -name VERILOG_FILE core/amiga/minimig_sram_bridge.v
-set_global_assignment -name VERILOG_FILE core/amiga/minimig_m68k_bridge.v
-set_global_assignment -name VERILOG_FILE core/amiga/minimig_bankmapper.v
-set_global_assignment -name VERILOG_FILE core/amiga/minimig.v
-set_global_assignment -name VERILOG_FILE core/amiga/gary.v
-set_global_assignment -name VERILOG_FILE core/amiga/fastchip.v
-set_global_assignment -name VERILOG_FILE core/amiga/cpu_wrapper.v
-set_global_assignment -name VERILOG_FILE core/amiga/cart.v
-set_global_assignment -name VERILOG_FILE core/amiga/amiga_clk.v
-set_global_assignment -name VERILOG_FILE core/amiga/akiko.v
-set_global_assignment -name QIP_FILE core/amiga/fx68k/fx68k.qip
-set_global_assignment -name QIP_FILE core/amiga/ram.qip
-set_global_assignment -name QIP_FILE core/amiga/pll.qip
-set_global_assignment -name QIP_FILE core/amiga/paula.qip
-set_global_assignment -name QIP_FILE core/amiga/gayle.qip
-set_global_assignment -name QIP_FILE core/amiga/denise.qip
-set_global_assignment -name QIP_FILE core/amiga/cia.qip
-set_global_assignment -name QIP_FILE core/amiga/agnus.qip
-set_global_assignment -name QIP_FILE apf/apf.qip
-set_global_assignment -name QIP_FILE apf/mf_ddio_bidir_12.qip
-set_global_assignment -name VERILOG_FILE core/core_top.v
-set_global_assignment -name VERILOG_FILE core/core_bridge_cmd.v
-set_global_assignment -name SDC_FILE core/core_constraints.sdc
-set_global_assignment -name VERILOG_FILE core/io_sdram.v
-set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
-set_global_assignment -name QIP_FILE core/mf_pllbase.qip
-set_global_assignment -name SIP_FILE core/mf_pllbase.sip
-set_global_assignment -name QIP_FILE core/mf_linebuf.qip
-set_global_assignment -name QIP_FILE core/mf_cursorfifo.qip
-set_global_assignment -name QIP_FILE core/mf_cursorimg.qip
-set_global_assignment -name VERILOG_FILE core/amiga/amiga_keyboard_convert.v
-set_global_assignment -name QIP_FILE uart_fifo.qip
-set_global_assignment -name QIP_FILE imem_bram.qip
-set_global_assignment -name QIP_FILE dmem_bram.qip
 set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk_74a -section_id auto_signaltap_0
@@ -1660,5 +1602,63 @@ set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -t
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_global_assignment -name VERILOG_FILE core/MPU/VexRiscv.v
+set_global_assignment -name VERILOG_FILE core/MPU/substitute_mcu_apf.v
+set_global_assignment -name VHDL_FILE core/MPU/simple_uart.vhd
+set_global_assignment -name VERILOG_FILE core/MPU/controller_rom.v
+set_global_assignment -name VERILOG_FILE core/i2s.v
+set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/sync_fifo.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/sound_i2s.sv"
+set_global_assignment -name VERILOG_FILE "core/analogue-pocket-utils/ip/hex_loader.v"
+set_global_assignment -name VERILOG_FILE "core/analogue-pocket-utils/ip/debug_key.v"
+set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/data_unloader.sv"
+set_global_assignment -name SYSTEMVERILOG_FILE "core/analogue-pocket-utils/ip/data_loader.sv"
+set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68KdotC_Kernel.vhd
+set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K_Pack.vhd
+set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K_ALU.vhd
+set_global_assignment -name VHDL_FILE core/amiga/tg68k/TG68K.vhd
+set_global_assignment -name QIP_FILE core/amiga/tg68k/TG68K.qip
+set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/hps_ext.v
+set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109tx.v
+set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109rx.v
+set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/avr/avr109.v
+set_global_assignment -name VERILOG_FILE core/amiga/hps_io_controller/vexriscv/vexriscv_wrapper.v
+set_global_assignment -name VERILOG_FILE core/amiga/userio.v
+set_global_assignment -name VERILOG_FILE core/amiga/rtg.v
+set_global_assignment -name VERILOG_FILE core/amiga/minimig_syscontrol.v
+set_global_assignment -name VERILOG_FILE core/amiga/minimig_sram_bridge.v
+set_global_assignment -name VERILOG_FILE core/amiga/minimig_m68k_bridge.v
+set_global_assignment -name VERILOG_FILE core/amiga/minimig_bankmapper.v
+set_global_assignment -name VERILOG_FILE core/amiga/minimig.v
+set_global_assignment -name VERILOG_FILE core/amiga/gary.v
+set_global_assignment -name VERILOG_FILE core/amiga/fastchip.v
+set_global_assignment -name VERILOG_FILE core/amiga/cpu_wrapper.v
+set_global_assignment -name VERILOG_FILE core/amiga/cart.v
+set_global_assignment -name VERILOG_FILE core/amiga/amiga_clk.v
+set_global_assignment -name VERILOG_FILE core/amiga/akiko.v
+set_global_assignment -name QIP_FILE core/amiga/fx68k/fx68k.qip
+set_global_assignment -name QIP_FILE core/amiga/ram.qip
+set_global_assignment -name QIP_FILE core/amiga/pll.qip
+set_global_assignment -name QIP_FILE core/amiga/paula.qip
+set_global_assignment -name QIP_FILE core/amiga/gayle.qip
+set_global_assignment -name QIP_FILE core/amiga/denise.qip
+set_global_assignment -name QIP_FILE core/amiga/cia.qip
+set_global_assignment -name QIP_FILE core/amiga/agnus.qip
+set_global_assignment -name QIP_FILE apf/apf.qip
+set_global_assignment -name QIP_FILE apf/mf_ddio_bidir_12.qip
+set_global_assignment -name VERILOG_FILE core/core_top.v
+set_global_assignment -name VERILOG_FILE core/core_bridge_cmd.v
+set_global_assignment -name SDC_FILE core/core_constraints.sdc
+set_global_assignment -name VERILOG_FILE core/io_sdram.v
+set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
+set_global_assignment -name QIP_FILE core/mf_pllbase.qip
+set_global_assignment -name SIP_FILE core/mf_pllbase.sip
+set_global_assignment -name QIP_FILE core/mf_linebuf.qip
+set_global_assignment -name QIP_FILE core/mf_cursorfifo.qip
+set_global_assignment -name QIP_FILE core/mf_cursorimg.qip
+set_global_assignment -name VERILOG_FILE core/amiga/amiga_keyboard_convert.v
+set_global_assignment -name QIP_FILE uart_fifo.qip
+set_global_assignment -name QIP_FILE imem_bram.qip
+set_global_assignment -name QIP_FILE dmem_bram.qip
 set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/src/fpga/core/wrapper/VexRiscv.v → src/fpga/core/MPU/VexRiscv.v b/src/fpga/core/wrapper/VexRiscv.v → src/fpga/core/MPU/VexRiscv.v
diff --git a/...iscv.v_toplevel_RegFilePlugin_regFile.bin → ...iscv.v_toplevel_RegFilePlugin_regFile.bin b/...iscv.v_toplevel_RegFilePlugin_regFile.bin → ...iscv.v_toplevel_RegFilePlugin_regFile.bin
diff --git a/src/fpga/core/wrapper/VexRiscv_APF.scala → src/fpga/core/MPU/VexRiscv_APF.scala b/src/fpga/core/wrapper/VexRiscv_APF.scala → src/fpga/core/MPU/VexRiscv_APF.scala
diff --git a/src/fpga/core/wrapper/controller_rom.v → src/fpga/core/MPU/controller_rom.v b/src/fpga/core/wrapper/controller_rom.v → src/fpga/core/MPU/controller_rom.v
diff --git a/src/fpga/core/wrapper/simple_uart.vhd → src/fpga/core/MPU/simple_uart.vhd b/src/fpga/core/wrapper/simple_uart.vhd → src/fpga/core/MPU/simple_uart.vhd
diff --git a/src/fpga/core/wrapper/substitute_mcu_apf.v → src/fpga/core/MPU/substitute_mcu_apf.v b/src/fpga/core/wrapper/substitute_mcu_apf.v → src/fpga/core/MPU/substitute_mcu_apf.v