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Update intrinsics to include f16, bf16, f32 variants as per ARM-softw…
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…are/acle#278
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@MDevereau
MDevereau committed Dec 6, 2023
1 parent adb12c4 commit 01e5d30
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Showing 6 changed files with 182 additions and 2 deletions.
42 changes: 42 additions & 0 deletions clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c
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Expand Up @@ -67,6 +67,34 @@ svint16_t test_svluti2_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_za
return svluti2_lane_zt_s16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti2_lane_zt_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u13__SVFloat16_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
svfloat16_t test_svluti2_lane_zt_f16(svfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti2_lane_zt_f16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti2_lane_zt_bf16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u14__SVBfloat16_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
svbfloat16_t test_svluti2_lane_zt_bf16(svbfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti2_lane_zt_bf16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti2_lane_zt_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> [[ZN:%.*]], i32 2)
Expand Down Expand Up @@ -94,3 +122,17 @@ svuint32_t test_svluti2_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_shared_
svint32_t test_svluti2_lane_zt_s32(svint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti2_lane_zt_s32(0, zn, 2);
}

// CHECK-LABEL: @test_svluti2_lane_zt_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u13__SVFloat32_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
svfloat32_t test_svluti2_lane_zt_f32(svfloat32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti2_lane_zt_f32(0, zn, 2);
}
42 changes: 42 additions & 0 deletions clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,34 @@ svint16_t test_svluti4_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_za
return svluti4_lane_zt_s16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti4_lane_zt_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f16u13__SVFloat16_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
svfloat16_t test_svluti4_lane_zt_f16(svfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti4_lane_zt_f16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti4_lane_zt_bf16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z25test_svluti4_lane_zt_bf16u14__SVBfloat16_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
svbfloat16_t test_svluti4_lane_zt_bf16(svbfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti4_lane_zt_bf16(0, zn, 2);
}

// CHECK-LABEL: @test_svluti4_lane_zt_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> [[ZN:%.*]], i32 2)
Expand Down Expand Up @@ -93,3 +121,17 @@ svuint32_t test_svluti4_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_shared_
svint32_t test_svluti4_lane_zt_s32(svint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti4_lane_zt_s32(0, zn, 2);
}

// CHECK-LABEL: @test_svluti4_lane_zt_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[ZN:%.*]], i32 2)
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f32u13__SVFloat32_t(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[ZN:%.*]], i32 2)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
svfloat32_t test_svluti4_lane_zt_f32(svfloat32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za {
return svluti4_lane_zt_f32(0, zn, 2);
}
28 changes: 26 additions & 2 deletions clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
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Expand Up @@ -78,7 +78,7 @@ void test_svluti4_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm
svluti4_lane_zt_f32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
}

void test_svluti2_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32) __arm_streaming __arm_shared_za __arm_preserves_za {
void test_svluti2_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
// Test Reg Offset
svluti2_lane_zt_u8(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
Expand All @@ -88,12 +88,24 @@ void test_svluti2_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32)
// Test index value range
svluti2_lane_zt_u16(0, zn_u16, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
// Test Reg Offset
svluti2_lane_zt_f16(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti2_lane_zt_f16(0, zn_f16, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
// Test Reg Offset
svluti2_lane_zt_bf16(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti2_lane_zt_bf16(0, zn_bf16, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
// Test Reg Offset
svluti2_lane_zt_u32(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti2_lane_zt_u32(0, zn_u32, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
// Test Reg Offset
svluti2_lane_zt_f32(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti2_lane_zt_f32(0, zn_f32, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}}
}

void test_svluti4_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32) __arm_streaming __arm_shared_za __arm_preserves_za {
void test_svluti4_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za {
// Test Reg Offset
svluti4_lane_zt_u8(1, zn_u8, 2); // expected-error {{argument val]ue 1 is outside the valid range [0, 0]}}
// Test index value range
Expand All @@ -103,7 +115,19 @@ void test_svluti4_lane_zt(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32)
// Test index value range
svluti4_lane_zt_u16(0, zn_u16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
// Test Reg Offset
svluti4_lane_zt_f16(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti4_lane_zt_f16(0, zn_f16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
// Test Reg Offset
svluti4_lane_zt_bf16(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti4_lane_zt_bf16(0, zn_bf16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
// Test Reg Offset
svluti4_lane_zt_u32(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti4_lane_zt_u32(0, zn_u32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
// Test Reg Offset
svluti4_lane_zt_f32(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
// Test index value range
svluti4_lane_zt_f32(0, zn_f32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}}
}
12 changes: 12 additions & 0 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3243,6 +3243,12 @@ multiclass sme2_luti2_vector_index<string mnemonic, SDPatternOperator intrinsic>
(!cast<Instruction>(NAME # _H) $zt, nxv8i16:$zn, (i32 VectorIndexB32b_timm:$imm))>;
def : Pat<(nxv4i32 (intrinsic (imm_to_zt untyped:$zt), nxv4i32:$zn, (i32 VectorIndexB32b_timm:$imm))),
(!cast<Instruction>(NAME # _S) $zt, nxv4i32:$zn, (i32 VectorIndexB32b_timm:$imm))>;
def : Pat<(nxv8f16 (intrinsic (imm_to_zt untyped:$zt), nxv8f16:$zn, (i32 VectorIndexB32b_timm:$imm))),
(!cast<Instruction>(NAME # _H) $zt, nxv8f16:$zn, (i32 VectorIndexB32b_timm:$imm))>;
def : Pat<(nxv8bf16 (intrinsic (imm_to_zt untyped:$zt), nxv8bf16:$zn, (i32 VectorIndexB32b_timm:$imm))),
(!cast<Instruction>(NAME # _H) $zt, nxv8bf16:$zn, (i32 VectorIndexB32b_timm:$imm))>;
def : Pat<(nxv4f32 (intrinsic (imm_to_zt untyped:$zt), nxv4f32:$zn, (i32 VectorIndexB32b_timm:$imm))),
(!cast<Instruction>(NAME # _S) $zt, nxv4f32:$zn, (i32 VectorIndexB32b_timm:$imm))>;
}

class sme2_luti4_vector_index<bits<2> sz, RegisterOperand vector_ty,
Expand All @@ -3263,6 +3269,12 @@ multiclass sme2_luti4_vector_index<string mnemonic, SDPatternOperator intrinsic>
(!cast<Instruction>(NAME # _H) $zt, nxv8i16:$zn, (i32 VectorIndexH32b_timm:$imm))>;
def : Pat<(nxv4i32 (intrinsic (imm_to_zt untyped:$zt), nxv4i32:$zn, (i32 VectorIndexH32b_timm:$imm))),
(!cast<Instruction>(NAME # _S) $zt, nxv4i32:$zn, (i32 VectorIndexH32b_timm:$imm))>;
def : Pat<(nxv8f16 (intrinsic (imm_to_zt untyped:$zt), nxv8f16:$zn, (i32 VectorIndexH32b_timm:$imm))),
(!cast<Instruction>(NAME # _H) $zt, nxv8f16:$zn, (i32 VectorIndexH32b_timm:$imm))>;
def : Pat<(nxv8bf16 (intrinsic (imm_to_zt untyped:$zt), nxv8bf16:$zn, (i32 VectorIndexH32b_timm:$imm))),
(!cast<Instruction>(NAME # _H) $zt, nxv8bf16:$zn, (i32 VectorIndexH32b_timm:$imm))>;
def : Pat<(nxv4f32 (intrinsic (imm_to_zt untyped:$zt), nxv4f32:$zn, (i32 VectorIndexH32b_timm:$imm))),
(!cast<Instruction>(NAME # _S) $zt, nxv4f32:$zn, (i32 VectorIndexH32b_timm:$imm))>;
}

// SME2 lookup table expand two contiguous registers
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,36 @@ define <vscale x 4 x i32> @luti2_i32(<vscale x 4 x i32> %x) {
ret <vscale x 4 x i32> %res
}

define <vscale x 8 x half> @luti2_f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: luti2_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: luti2 z0.h, zt0, z0[15]
; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %x, i32 15)
ret <vscale x 8 x half> %res
}

define <vscale x 8 x bfloat> @luti2_bf16(<vscale x 8 x bfloat> %x) {
; CHECK-LABEL: luti2_bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: luti2 z0.h, zt0, z0[15]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %x, i32 15)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x float> @luti2_f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: luti2_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: luti2 z0.s, zt0, z0[15]
; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %x, i32 15)
ret <vscale x 4 x float> %res
}

declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32, <vscale x 16 x i8>, i32)
declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32, <vscale x 8 x i16>, i32)
declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32, <vscale x 4 x i32>, i32)
declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32, <vscale x 8 x half>, i32)
declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32, <vscale x 8 x bfloat>, i32)
declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32, <vscale x 4 x float>, i32)
30 changes: 30 additions & 0 deletions llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,36 @@ define <vscale x 4 x i32> @luti4_i32(<vscale x 4 x i32> %x) {
ret <vscale x 4 x i32> %res
}

define <vscale x 8 x half> @luti4_f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: luti4_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: luti4 z0.h, zt0, z0[7]
; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %x, i32 7)
ret <vscale x 8 x half> %res
}

define <vscale x 8 x bfloat> @luti4_bf16(<vscale x 8 x bfloat> %x) {
; CHECK-LABEL: luti4_bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: luti4 z0.h, zt0, z0[7]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %x, i32 7)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x float> @luti4_f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: luti4_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: luti4 z0.s, zt0, z0[7]
; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %x, i32 7)
ret <vscale x 4 x float> %res
}

declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32, <vscale x 16 x i8>, i32)
declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32, <vscale x 8 x i16>, i32)
declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32, <vscale x 4 x i32>, i32)
declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32, <vscale x 8 x half>, i32)
declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32, <vscale x 8 x bfloat>, i32)
declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32, <vscale x 4 x float>, i32)

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