Releases · IObundle/py2hwsw

What's Changed

Create PIP installable module by @Edw590 in #1
Program can be run from command line directly now by @Edw590 in #2
lib files added and auto-installed with PIP; py2hwsw callable directly by @Edw590 in #3
Fix permissions of build dir when py2hwsw is installed via Nix by @arturum1 in #5
fix(ctls): Fix setup of iob_ctls module by @Edw590 in #4
Auto-create signal references by @arturum1 in #6
Merge new changes from iob-soc/main into py2hwsw by @arturum1 in #9
iob_comb generates combinatory logic by @agrevin in #8
Parse driven signals in verilog snippets to generate outputs list using regex by @agrevin in #10
feat(ci): Add github actions tests by @arturum1 in #12
Eliminate outputs list; Change parsed signals directly to reg by @agrevin in #11
General improvements to py2hwsw by @arturum1 in #15
Improve regex expressions by @arturum1 in #16
iob_fsm by @agrevin in #17
Py2HWSW now generates FSMs with simpler syntax by @agrevin in #18
Fix bug where searching state names would match incorrectly by @agrevin in #19
General improvements by @arturum1 in #20
Registers can be implicitly declared by using a sufix in the "verilog_code" by @agrevin in #21
Add lib/ to path searched by find_module_setup_dir; move basic logic gates to lib/ by @agrevin in #22
General improvements by @arturum1 in #24
Add support for for loops in iob_fsms by @agrevin in #26
Replace 'purpose' with 'dest_dir' attribute; Copy fpga files from py2 (without override) even if directory exists. by @arturum1 in #25
fix(ENQ): Reset console.py gotENQ if received non-ENQ by @arturum1 in #28
Move CSR scripts into a dedicated csrs lib module. by @arturum1 in #29
Fix for loops in iob_fsm, now every iteration starts one state after the lable by @agrevin in #27
Fix bugs; Resolve issue. by @arturum1 in #32
Add the option to add default assignments to fsms by @agrevin in #31
Add new standard python parameters; Add print_core_dict target. by @arturum1 in #37
Improve csrs module. by @arturum1 in #38
Registers are only infered when "_nxt" is present by @agrevin in #39
Resolve issue; Improve debug features; Rename FPGA files/folders. by @arturum1 in #40
ShortHand notation by @agrevin in #41
Rename default $(FPGA_TOP) value and constraints by @arturum1 in #42
Shorthand notation supports multiple line strings, where each line adds an attribute by @agrevin in #43
FIx ci.yml; Add missing regs in csrs module; Resolve issues. by @arturum1 in #44
Shorthand notation changed to look like command line by @agrevin in #45
Add support for shorthand notation i wires and ports by @agrevin in #46
Generate internal CSR FIFOS (via python params); Add CSRs APB, AXI, AXIL support; Remove default pc-emul sources. by @arturum1 in #48
Validate that parameter values fit within the specified range by @agrevin in #49
Blocks can be instantiated with shorthand notation by @agrevin in #47
Add parent attribute; Add bit slicing and concatenations in port connections; Add regfile in CSRs and asym FIFOs. by @arturum1 in #50
Add acknowledgement; Add SPDX license headers; Add defaults for original_name and name; Fix append of lists from child cores. by @arturum1 in #51
fix(xsim): variables for remote simulation by @P-Miranda in #52
Move iob-soc lib modules into py2hwsw. by @arturum1 in #53
Add iob_and_tb.v; Update README.md; Update Nix; Format code. by @arturum1 in #54
Signals with direction must represent it by addign a suffix to its name instead of a "direction" variable by @agrevin in #56
Improve error messages; Add --py2hwsw_docs argument; Initial py2 user guide; Fix linter; by @arturum1 in #57
Remove 2 least significant bits from address buses; Rename port_prefix and wire_prefix to prefix; Update README. by @arturum1 in #58
Interface subtype is now infered from port/wire name by @agrevin in #59
Fix bugs in iob_system fpga wrappers; Improve build dir Makefile clean targets. by @arturum1 in #62
Fix bugs in cyclonev wrapper; Move README.md to iob-soc. by @arturum1 in #64
Resolve github issues. by @arturum1 in #69
Add iob_ prefix to remanining lib modules and bsp.[v]h by @arturum1 in #76
Add --split flag to makehex.py; Fix iob_system. by @arturum1 in #75
Add address signal to regfiles & remove csrs_iob; Merge iob-soc/main into py2hwsw. by @arturum1 in #77
Add support for doc_only attribute in core's confs and csr_groups. by @arturum1 in #80
Add doc_only attribute to confs and csr_groups; Add input validation for port suffix; Add missing suffixes in lib modules. by @arturum1 in #79
Merge iob-soc/main, fix iob_acc, fix py2 parent bug by @And-Nob in #81
Fix bug in py2hwsw; Add instructions to build py2hwsw user guide; Add bin folder with symlink to py2hwsw.py by @arturum1 in #89
Shorthand notation suports csrs iob_uart has the iob_csrs block as an example by @agrevin in #78
fix(console): faster serial read by @P-Miranda in #92
fix(questa): clean target calls gen-clean by @P-Miranda in #94
Resolve py2hwsw github issues. by @arturum1 in #93
Add support for confs/block groups; Add support for ungrouped confs/csrs/blocks. by @arturum1 in #97
Improve py2 user guide; Resolve py2 issues. by @arturum1 in #99
User guide improvements; Initial docker; Fix generated fpga wrappers. by @arturum1 in #102
feat(docs, docker): ug improvements,initial docker by @P-Miranda in #100
Add iob_address_translator module. by @arturum1 in #104
Update if_gen by @agrevin in #103
feat(docker): workflow to build and publish image by @P-Miranda in #105
Add superblock and subblock lists. by @arturum1 in #106
CSRs: Remove iob_ready dependency for ren/wen signals with autoreg=False by @arturum1 in #110
Remove setup attribute. by @arturum1 in #108
Create iob_axi_split, iob_axi_merge, iob_axi_interconnect lib modules; Update iob_system. by @arturum1 in #107
Resolve github issues by @arturum1 in #114
fix(CDC, doc): axistream_in nword CDC. Doc typo by @P-Miranda in #117
fix(mem): generate if for RAMS when HEXFILE="none" by @P-Miranda in #118
Fix py2hwsw bugs and lib modules; Update README and User Guide; Add tester (WIP). by @arturum1 in #119