Merge pull request #119 from arturum1/main

Fix py2hwsw bugs and lib modules; Update README and User Guide; Add tester (WIP).

README.md

@@ -10,14 +10,13 @@ SPDX-License-Identifier: MIT
 
 This project introduces a Python framework to (1) manage the
 files of an embedded hardware/software (HW/SW) codesign project and (2) generate
-the Verilog code of the hardware components. The flow will
-use only open-source tools.
+the Verilog code of the hardware components. The flow uses only open-source tools.
 
 An embedded HW/SW project requires that various source files be conveniently
 organized in a directory tree so that the various EDA tools can run. Typically, 
 makefiles and different scripting languages are employed to drive these tools,
-which is often a barrier for new developers. The proposed Python framework will
-raise developer accessibility by providing a single cockpit for the design
+which is often a barrier for new developers. The Python framework raises
+developer accessibility by providing a single cockpit for the design
 process.
 
 Hardware Design Languages such as Verilog and VHDL give a lot of flexibility to

py2hwsw/hardware/fpga/quartus/build.mk

@@ -31,7 +31,7 @@ endif
 # Set the Quartus command to porgram the FPGA
 FPGA_PROG=nios2_command_shell.sh quartus_pgm -m jtag -c 1 -o "p;$(FPGA_TOP).sof"
 
-QUARTUS_FLAGS = -t quartus/build.tcl $(FPGA_TOP) $(BOARD) "$(VSRC)" $(IS_FPGA) $(USE_EXTMEM) $(QUARTUS_SEED) $(USE_QUARTUS_PRO)
+QUARTUS_FLAGS = -t quartus/build.tcl $(FPGA_TOP) $(BOARD) "$(VSRC)" "$(INCLUDE_DIRS)" $(IS_FPGA) $(USE_EXTMEM) $(QUARTUS_SEED) $(USE_QUARTUS_PRO)
 
 $(FPGA_OBJ): $(VHDR) $(VSRC) $(wildcard $(BOARD)/*.sdc)
 	nios2_command_shell.sh quartus_sh $(QUARTUS_FLAGS)

py2hwsw/hardware/fpga/quartus/build.tcl

@@ -6,10 +6,11 @@
 set NAME [lindex $argv 0]
 set BOARD [lindex $argv 1]
 set VSRC [lindex $argv 2]
-set IS_FPGA [lindex $argv 3]
-set USE_EXTMEM [lindex $argv 4]
-set SEED [lindex $argv 5]
-set USE_QUARTUS_PRO [lindex $argv 6]
+set INCLUDE_DIRS [lindex $argv 3]
+set IS_FPGA [lindex $argv 4]
+set USE_EXTMEM [lindex $argv 5]
+set SEED [lindex $argv 6]
+set USE_QUARTUS_PRO [lindex $argv 7]
 
 load_package flow
 
@@ -37,6 +38,10 @@ set_global_assignment -name SEARCH_PATH ../common_src
 set_global_assignment -name SEARCH_PATH ./src
 set_global_assignment -name SEARCH_PATH quartus/$BOARD
 
+foreach dir $INCLUDE_DIRS {
+    set_global_assignment -name SEARCH_PATH $dir
+}
+
 #verilog sources, quartus IPs, use extension
 foreach file [split $VSRC \ ] {
     if { [ file extension $file ] == ".qsys" } {

py2hwsw/hardware/fpga/vivado/build.mk

@@ -24,7 +24,7 @@ FPGA_PROG=vivado -nojournal -log vivado.log -mode batch -source vivado/prog.tcl
 # work-around for http://svn.clifford.at/handicraft/2016/vivadosig11
 export RDI_VERBOSE = False
 
-VIVADO_FLAGS= -nojournal -log reports/vivado.log -mode batch -source vivado/build.tcl -tclargs $(FPGA_TOP) $(CSR_IF) $(BOARD) "$(VSRC)" $(IS_FPGA) $(USE_EXTMEM)
+VIVADO_FLAGS= -nojournal -log reports/vivado.log -mode batch -source vivado/build.tcl -tclargs $(FPGA_TOP) $(CSR_IF) $(BOARD) "$(VSRC)" "$(INCLUDE_DIRS)" $(IS_FPGA) $(USE_EXTMEM)
 
 $(FPGA_OBJ): $(VSRC) $(VHDR) $(wildcard $(BOARD)/*.sdc)
 	mkdir -p reports && vivado $(VIVADO_FLAGS) 

py2hwsw/hardware/fpga/vivado/build.tcl

@@ -7,8 +7,9 @@ set NAME [lindex $argv 0]
 set CSR_IF [lindex $argv 1]
 set BOARD [lindex $argv 2]
 set VSRC [lindex $argv 3]
-set IS_FPGA [lindex $argv 4]
-set USE_EXTMEM [lindex $argv 5]
+set INCLUDE_DIRS [lindex $argv 4]
+set IS_FPGA [lindex $argv 5]
+set USE_EXTMEM [lindex $argv 6]
 
 #verilog sources, vivado IPs, use file extension
 foreach file [split $VSRC \ ] {
@@ -29,6 +30,11 @@ if {[file exists "vivado/premap.tcl"]} {
     source "vivado/premap.tcl"
 }
 
+set SYNTH_FLAGS {}
+foreach dir $INCLUDE_DIRS {
+    lappend SYNTH_FLAGS "-include_dirs ${dir}"
+}
+
 
 #read design constraints and synthesize design
 if { $IS_FPGA == "1" } {
@@ -43,7 +49,7 @@ if { $IS_FPGA == "1" } {
     if {[file exists "vivado/tool.sdc"]} {
         read_xdc vivado/tool.sdc
     }
-    synth_design -include_dirs ../src -include_dirs ../common_src -include_dirs ./src -include_dirs ./vivado/$BOARD -part $PART -top $NAME -verbose
+    synth_design -include_dirs ../src -include_dirs ../common_src -include_dirs ./src -include_dirs ./vivado/$BOARD $SYNTH_FLAGS -part $PART -top $NAME -verbose
 } else {
     #read design constraints
     puts "Out of context synthesis"
@@ -52,7 +58,7 @@ if { $IS_FPGA == "1" } {
     if {[file exists "vivado/tool.sdc"]} {
         read_xdc -mode out_of_context vivado/tool.sdc
     }
-    synth_design -include_dirs ../src -include_dirs ../common_src -include_dirs ./src -include_dirs ./vivado/$BOARD -part $PART -top $NAME -mode out_of_context -flatten_hierarchy full -verbose
+    synth_design -include_dirs ../src -include_dirs ../common_src -include_dirs ./src -include_dirs ./vivado/$BOARD $SYNTH_FLAGS -part $PART -top $NAME -mode out_of_context -flatten_hierarchy full -verbose
 }
 
 #set post-map custom assignments

py2hwsw/hardware/lint/spyglass.tcl

@@ -5,6 +5,7 @@
 #grab TOP from environment variable NAME in tcl
 set TOP $env(NAME)
 set CSR_IF $env(CSR_IF)
+set INCLUDE_DIRS $env(INCLUDE_DIRS)
 
 puts "TOP: $TOP"
 puts "CSR_IF: $CSR_IF"
@@ -34,6 +35,7 @@ set_option language_mode mixed
 set_option enableV05 yes
 set_option top $TOP
 set_option incdir { . ../src }
+set_option incdir $INCLUDE_DIRS
 #set_option active_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
 set_option pragma { synopsys synthesis }
 #set_option sdc2sgdc yes

py2hwsw/hardware/lint/verilator.mk

@@ -4,8 +4,10 @@
 
 # This makefile is used at build-time
 
+VFLAGS+=$(addprefix -I,$(INCLUDE_DIRS))
+
 run-lint:
-	verilator --lint-only -Wall --timing -I. -I../src -I../simulation/src $(VSRC)
+	verilator --lint-only -Wall --timing -I. -I../src -I../simulation/src $(VFLAGS) $(VSRC)
 
 clean-lint:
 

py2hwsw/hardware/simulation/icarus.mk

@@ -3,6 +3,7 @@
 # SPDX-License-Identifier: MIT
 
 VFLAGS+=-W all -g2005-sv -I. -I../src -I../common_src -Isrc -Ihardware/src
+VFLAGS+=$(addprefix -I,$(INCLUDE_DIRS))
 
 ifeq ($(VCD),1)
 VFLAGS+=-DVCD

py2hwsw/hardware/simulation/questa.mk

@@ -11,6 +11,7 @@ SIM_SYNC_FLAGS=$(QUESTA_SYNC_FLAGS)
 SIM_PROC=vsim
 
 CFLAGS = -quiet -sv +incdir+. +incdir+../src +incdir+../common_src  +incdir+src $(VFLAGS)
+CFLAGS+=$(addprefix +incdir+,$(INCLUDE_DIRS))
 SFLAGS = -voptargs="+acc" -c
 ifeq ($(VCD),1)
 CFLAGS+=+define+VCD

py2hwsw/hardware/simulation/vcs.mk

@@ -11,6 +11,7 @@ SIM_SYNC_FLAGS=$(SYNOPSYS_SYNC_FLAGS)
 SIM_PROC=simv
 
 SFLAGS=-nc -sverilog +incdir+. +incdir+../src +incdir+../common_src  +incdir+src $(VFLAGS)
+SFLAGS+=$(addprefix +incdir+,$(INCLUDE_DIRS))
 ifeq ($(VCD),1)
 SFLAGS+=+define+VCD
 endif

py2hwsw/hardware/simulation/verilator.mk

@@ -5,6 +5,7 @@
 VTOP?=$(NAME)
 
 VFLAGS+=--cc --exe -I. -I../src -I../common_src -Isrc --top-module $(VTOP)
+VFLAGS+=$(addprefix -I,$(INCLUDE_DIRS))
 VFLAGS+=-Wno-lint --Wno-UNOPTFLAT
 VFLAGS+=--no-timing
 # Include embedded headers

py2hwsw/hardware/simulation/xcelium.mk

@@ -35,6 +35,8 @@ ifneq ($(wildcard hardware/src),)
 VFLAGS+=-incdir hardware/src
 endif
 
+VFLAGS+=$(addprefix -incdir ,$(INCLUDE_DIRS))
+
 ifeq ($(VCD),1)
 VFLAGS+=-define VCD
 endif

py2hwsw/hardware/simulation/xsim.mk

@@ -25,6 +25,8 @@ ifneq ($(wildcard hardware/src),)
 VFLAGS+=-i hardware/src
 endif
 
+VFLAGS+=$(addprefix -i ,$(INCLUDE_DIRS))
+
 ifeq ($(VCD),1)
 VFLAGS+=-d VCD
 endif

py2hwsw/hardware/syn/Makefile

@@ -24,8 +24,8 @@ include syn_build.mk
 endif
 
 #include the module's headers and sources
-VHDR+=$(wildcard ../src/*.vh)  
-VSRC+=$(wildcard ../src/*.v) 
+VHDR+=$(wildcard ../src/*.vh)
+VSRC+=$(wildcard ../src/*.v)
 
 INCLUDE+=.
 INCLUDE+=../src

py2hwsw/hardware/syn/yosys/build.tcl

@@ -2,8 +2,15 @@
 #
 # SPDX-License-Identifier: MIT
 
+set INCLUDE_DIRS $env(INCLUDE_DIRS)
+
+set YOSYS_FLAGS {}
+foreach dir $INCLUDE_DIRS {
+    lappend YOSYS_FLAGS "-I${dir}"
+}
+
 # Read the Verilog files
-yosys read_verilog -DSYNTHESIS -I./src -I../src -I../common_src ../src/*.v
+yosys read_verilog -DSYNTHESIS -I./src -I../src -I../common_src $YOSYS_FLAGS ../src/*.v
 
 set top iob_soc
 

py2hwsw/lib/hardware/basic_tests/iob_aoi/iob_aoi.py

@@ -82,6 +82,12 @@ def setup(py_params_dict):
                 "instance_name": "iob_sim",
                 "dest_dir": "hardware/simulation/src",
             },
+            # Tester
+            {
+                "core_name": "iob_aoi_tester",
+                "instance_name": "iob_tester",
+                "dest_dir": "submodules/tester",
+            },
         ],
     }
 

py2hwsw/lib/hardware/basic_tests/iob_aoi/submodules/tester/iob_aoi_tester.py

@@ -0,0 +1,127 @@
+# SPDX-FileCopyrightText: 2024 IObundle
+#
+# SPDX-License-Identifier: MIT
+
+
+def setup(py_params_dict):
+    attributes_dict = {
+        # Set "is_tester" attribute to generate Makefile and flows allowing to run this core as top module
+        "is_tester": True,
+        "version": "0.1",
+        "confs": [
+            {
+                "name": "W",
+                "type": "P",
+                "val": "21",
+                "min": "1",
+                "max": "32",
+                "descr": "IO width",
+            },
+        ],
+        "wires": [
+            {
+                "name": "a",
+                "descr": "AOI input port 1",
+                "signals": [
+                    {"name": "a", "width": "W"},
+                ],
+            },
+            {
+                "name": "b",
+                "descr": "AOI input port 2",
+                "signals": [
+                    {"name": "b", "width": "W"},
+                ],
+            },
+            {
+                "name": "c",
+                "descr": "AOI input port 3",
+                "signals": [
+                    {"name": "c", "width": "W"},
+                ],
+            },
+            {
+                "name": "d",
+                "descr": "AOI input port 4",
+                "signals": [
+                    {"name": "d", "width": "W"},
+                ],
+            },
+            {
+                "name": "y",
+                "descr": "AOI output port",
+                "signals": [
+                    {"name": "y", "width": "W"},
+                ],
+            },
+        ],
+        "subblocks": [
+            {
+                "core_name": "iob_aoi",
+                "instance_name": "uut_aoi",
+                "instance_description": "Unit Under Test",
+                "parameters": {
+                    "W": "W",
+                },
+                "connect": {
+                    "a_i": "a",
+                    "b_i": "b",
+                    "c_i": "c",
+                    "d_i": "d",
+                    "y_o": "y",
+                },
+            }
+        ],
+        "superblocks": [
+            {
+                "name": "simulation",
+                "descr": "Blocks for simulation",
+                "blocks": [
+                    # Simulation wrapper
+                    {
+                        "core_name": "iob_sim",
+                        "instance_name": "iob_sim",
+                        "dest_dir": "hardware/simulation/src",
+                    },
+                ],
+            },
+        ],
+        "snippets": [
+            {
+                "verilog_code": """\
+   // Tester body / verification code
+   // Currently using non-synthesizable code
+
+   reg     [3:0] data_i = 0;
+   wire          data_o;
+
+   assign a = data_i[0];
+   assign b = data_i[1];
+   assign c = data_i[2];
+   assign d = data_i[3];
+   assign data_o = y;
+
+   integer       i;
+   integer       fp;
+
+   initial begin
+
+      for (i = 0; i < 16; i = i + 1) begin
+         #10 data_i = i[3:0];
+         #10 $display("data_i = %b, data_o = %b", data_i, data_o);
+      end
+      #10 $display("%c[1;34m", 8'd27);
+      $display("Test completed successfully.");
+      $display("%c[0m", 8'd27);
+
+      fp = $fopen("test.log", "w");
+      $fdisplay(fp, "Test passed!");
+
+      $finish();
+   end
+"""
+            }
+        ],
+    }
+
+    return attributes_dict

py2hwsw/lib/hardware/buses/iob_axi2iob/hardware/src/iob_axi2iob.v

@@ -156,8 +156,8 @@ module iob_axi2iob #(
       .clk_i (clk_i),
       .arst_i(arst_i),
       .cke_i (cke_i),
-      .rst_i (1'b0),
-      .en_i  (iob_rvalid_e),
+      .rst_i (m_axil_rvalid & m_axil_rready),
+      .en_i  (iob_rvalid_i),
       .data_i(iob_rvalid_i),
       .data_o(iob_rvalid_q)
    );
@@ -170,7 +170,7 @@ module iob_axi2iob #(
       .arst_i(arst_i),
       .cke_i (cke_i),
       .rst_i (1'b0),
-      .en_i  (iob_rvalid_e),
+      .en_i  (iob_rvalid_i),
       .data_i(iob_rdata_i),
       .data_o(iob_rdata_q)
    );

py2hwsw/lib/hardware/buses/iob_axi_merge/iob_axi_merge.py

@@ -346,7 +346,7 @@ def setup(py_params_dict):
             "name": "read_prio_enc_o",
             "descr": "Output of read priority encoder",
             "signals": [
-                {"name": "read_prio_enc_o"},
+                {"name": "read_prio_enc_o", "width": NBITS},
             ],
         },
         # Write priority encoder signals
@@ -361,7 +361,7 @@ def setup(py_params_dict):
             "name": "write_prio_enc_o",
             "descr": "Output of write priority encoder",
             "signals": [
-                {"name": "write_prio_enc_o"},
+                {"name": "write_prio_enc_o", "width": NBITS},
             ],
         },
     ]