Merge pull request #45 from arturum1/main

Use IOb interface for cbus of PLIC and CLINT; Add iob2axil converters.
IObundle · Oct 2, 2024 · acc7405 · acc7405
2 parents 213a9a9 + 4466e1e
commit acc7405
Showing 1 changed file with 90 additions and 46 deletions.
diff --git a/iob_vexriscv.py b/iob_vexriscv.py
@@ -87,26 +87,20 @@ def setup(py_params_dict):
                 "name": "clint_cbus_s",
                 "descr": "CLINT CSRs bus",
                 "interface": {
-                    "type": "axil",
+                    "type": "iob",
                     "subtype": "slave",
                     "port_prefix": "clint_",
-                    "ID_W": "AXI_ID_W",
                     "ADDR_W": "16",
-                    "DATA_W": "AXI_DATA_W",
-                    "LEN_W": "AXI_LEN_W",
                 },
             },
             {
                 "name": "plic_cbus_s",
                 "descr": "PLIC CSRs bus",
                 "interface": {
-                    "type": "axil",
+                    "type": "iob",
                     "subtype": "slave",
                     "port_prefix": "plic_",
-                    "ID_W": "AXI_ID_W",
                     "ADDR_W": "22",
-                    "DATA_W": "AXI_DATA_W",
-                    "LEN_W": "AXI_LEN_W",
                 },
             },
             {
@@ -148,52 +142,102 @@ def setup(py_params_dict):
                     {"name": "dbus_axi_arlock_int", "width": "1"},
                 ],
             },
+            {
+                "name": "clint_cbus_axil",
+                "descr": "CLINT CSRs bus",
+                "interface": {
+                    "type": "axil",
+                    "subtype": "slave",
+                    "wire_prefix": "clint_",
+                    "ADDR_W": "16",
+                    "DATA_W": "AXI_DATA_W",
+                },
+            },
+            {
+                "name": "plic_cbus_axil",
+                "descr": "PLIC CSRs bus",
+                "interface": {
+                    "type": "axil",
+                    "subtype": "slave",
+                    "wire_prefix": "plic_",
+                    "ADDR_W": "22",
+                    "DATA_W": "AXI_DATA_W",
+                },
+            },
+        ],
+        "blocks": [
+            {
+                "core_name": "iob2axil",
+                "instance_name": "clint_iob2axil",
+                "instance_description": "Convert IOb to AXI lite for CLINT",
+                "parameters": {
+                    "AXIL_ADDR_W": "16",
+                    "AXIL_DATA_W": "AXI_DATA_W",
+                },
+                "connect": {
+                    "iob_s": "clint_cbus_s",
+                    "axil_m": "clint_cbus_axil",
+                },
+            },
+            {
+                "core_name": "iob2axil",
+                "instance_name": "plic_iob2axil",
+                "instance_description": "Convert IOb to AXI lite for PLIC",
+                "parameters": {
+                    "AXIL_ADDR_W": "22",
+                    "AXIL_DATA_W": "AXI_DATA_W",
+                },
+                "connect": {
+                    "iob_s": "plic_cbus_s",
+                    "axil_m": "plic_cbus_axil",
+                },
+            },
         ],
         "snippets": [
             {
                 "verilog_code": """
   // Instantiation of VexRiscv, Plic, and Clint
   VexRiscvAxi4LinuxPlicClint CPU (
       // CLINT
-      .clint_awvalid(clint_axil_awvalid_i),
-      .clint_awready(clint_axil_awready_o),
-      .clint_awaddr(clint_axil_awaddr_i),
-      .clint_awprot(clint_axil_awprot_i),
-      .clint_wvalid(clint_axil_wvalid_i),
-      .clint_wready(clint_axil_wready_o),
-      .clint_wdata(clint_axil_wdata_i),
-      .clint_wstrb(clint_axil_wstrb_i),
-      .clint_bvalid(clint_axil_bvalid_o),
-      .clint_bready(clint_axil_bready_i),
-      .clint_bresp(clint_axil_bresp_o),
-      .clint_arvalid(clint_axil_arvalid_i),
-      .clint_arready(clint_axil_arready_o),
-      .clint_araddr(clint_axil_araddr_i),
-      .clint_arprot(clint_axil_arprot_i),
-      .clint_rvalid(clint_axil_rvalid_o),
-      .clint_rready(clint_axil_rready_i),
-      .clint_rdata(clint_axil_rdata_o),
-      .clint_rresp(clint_axil_rresp_o),
+      .clint_awvalid(clint_axil_awvalid),
+      .clint_awready(clint_axil_awready),
+      .clint_awaddr(clint_axil_awaddr),
+      .clint_awprot(clint_axil_awprot),
+      .clint_wvalid(clint_axil_wvalid),
+      .clint_wready(clint_axil_wready),
+      .clint_wdata(clint_axil_wdata),
+      .clint_wstrb(clint_axil_wstrb),
+      .clint_bvalid(clint_axil_bvalid),
+      .clint_bready(clint_axil_bready),
+      .clint_bresp(clint_axil_bresp),
+      .clint_arvalid(clint_axil_arvalid),
+      .clint_arready(clint_axil_arready),
+      .clint_araddr(clint_axil_araddr),
+      .clint_arprot(clint_axil_arprot),
+      .clint_rvalid(clint_axil_rvalid),
+      .clint_rready(clint_axil_rready),
+      .clint_rdata(clint_axil_rdata),
+      .clint_rresp(clint_axil_rresp),
       // PLIC
-      .plic_awvalid(plic_axil_awvalid_i),
-      .plic_awready(plic_axil_awready_o),
-      .plic_awaddr(plic_axil_awaddr_i),
-      .plic_awprot(plic_axil_awprot_i),
-      .plic_wvalid(plic_axil_wvalid_i),
-      .plic_wready(plic_axil_wready_o),
-      .plic_wdata(plic_axil_wdata_i),
-      .plic_wstrb(plic_axil_wstrb_i),
-      .plic_bvalid(plic_axil_bvalid_o),
-      .plic_bready(plic_axil_bready_i),
-      .plic_bresp(plic_axil_bresp_o),
-      .plic_arvalid(plic_axil_arvalid_i),
-      .plic_arready(plic_axil_arready_o),
-      .plic_araddr(plic_axil_araddr_i),
-      .plic_arprot(plic_axil_arprot_i),
-      .plic_rvalid(plic_axil_rvalid_o),
-      .plic_rready(plic_axil_rready_i),
-      .plic_rdata(plic_axil_rdata_o),
-      .plic_rresp(plic_axil_rresp_o),
+      .plic_awvalid(plic_axil_awvalid),
+      .plic_awready(plic_axil_awready),
+      .plic_awaddr(plic_axil_awaddr),
+      .plic_awprot(plic_axil_awprot),
+      .plic_wvalid(plic_axil_wvalid),
+      .plic_wready(plic_axil_wready),
+      .plic_wdata(plic_axil_wdata),
+      .plic_wstrb(plic_axil_wstrb),
+      .plic_bvalid(plic_axil_bvalid),
+      .plic_bready(plic_axil_bready),
+      .plic_bresp(plic_axil_bresp),
+      .plic_arvalid(plic_axil_arvalid),
+      .plic_arready(plic_axil_arready),
+      .plic_araddr(plic_axil_araddr),
+      .plic_arprot(plic_axil_arprot),
+      .plic_rvalid(plic_axil_rvalid),
+      .plic_rready(plic_axil_rready),
+      .plic_rdata(plic_axil_rdata),
+      .plic_rresp(plic_axil_rresp),
       .plicInterrupts(plic_interrupts_i),
       // Instruction Bus
       .iBusAxi_arvalid(ibus_axi_arvalid_o),