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If gen2 #974

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merged 1,580 commits into from
Nov 12, 2024
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253eb9d
fix(format): python formatting
P-Miranda Aug 21, 2024
826b177
Add iob_reg as iob_soc.py dependency
Edw590 Aug 21, 2024
64d790e
Update py2 to fix state number bug
agrevin Aug 21, 2024
49c0159
organize folders
jjts Aug 21, 2024
046c446
Merge remote-tracking branch 'upstream/if_gen2' into axis
P-Miranda Aug 21, 2024
73371a4
Merge pull request #915 from P-Miranda/nco
jjts Aug 21, 2024
e7eeab2
Merge pull request #920 from agrevin/if_gen2
jjts Aug 21, 2024
0810505
FW stack size is configurable now
Edw590 Aug 21, 2024
b6f20a8
Fix 2 of 3 Kintex tests (internal memory tests)
Edw590 Aug 21, 2024
deea411
Merge remote-tracking branch 'origin/if_gen2' into revamp2
Edw590 Aug 21, 2024
c00b3a3
Update CACHE
Edw590 Aug 21, 2024
2db644f
Merge pull request #918 from P-Miranda/axis
jjts Aug 21, 2024
cac1106
Outdate py2hwsw temporarily to one that has a fix
Edw590 Aug 21, 2024
c0ce9f5
fix(ci): Clean submodules after checkout
arturum1 Aug 21, 2024
b559530
Merge pull request #1 from arturum1/pr_913
Edw590 Aug 21, 2024
26fcb9a
refactor(Makefile): Simplify Makefile; Update CACHE.
arturum1 Aug 21, 2024
fbe6285
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into iob_wishbo…
mbot27 Aug 21, 2024
2343e37
Update lib/hardware/buses/iob_wishbone2iob/iob_wishbone2iob.py
mbot27 Aug 22, 2024
314858d
feat(py2hwsw): Update py2hwsw version
arturum1 Aug 22, 2024
b7b812d
chore(gpio): Move gpio code into lib folder
arturum1 Aug 22, 2024
44e146e
Merge commit 'b7b812dd' into if_gen2
arturum1 Aug 22, 2024
35f5f95
chore(regfileif): Move regfileif to lib
arturum1 Aug 22, 2024
28a9ad3
Merge commit '35f5f956' into if_gen2
arturum1 Aug 22, 2024
da226da
style(lib): Format code.
arturum1 Aug 22, 2024
a09b544
style(fifo): Update testbench test passed msg; Format code.
arturum1 Aug 22, 2024
f04bab1
Merge pull request #922 from mbot27/iob_wishbone2iob
jjts Aug 22, 2024
8c4b501
feat(gpio): Generate gpio with py2hwsw
arturum1 Aug 22, 2024
60799af
wip(regfileif): Generate regfileif with py2hwsw.
arturum1 Aug 22, 2024
d4f40d5
feat(py2hwsw): Update py2hwsw version
arturum1 Aug 22, 2024
9c5b4e6
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Aug 22, 2024
4cc6616
Merge branch 'main' into if_gen2
arturum1 Aug 22, 2024
ab70cc4
fix(ci): Clean submodules after checkout
arturum1 Aug 21, 2024
add5e26
Merge branch 'main' into if_gen2
arturum1 Aug 22, 2024
fd73d07
Merge pull request #923 from arturum1/if_gen2
jjts Aug 23, 2024
5e8fb1f
Merge branch 'main' into if_gen2
arturum1 Aug 23, 2024
5deb703
Merge remote-tracking branch 'origin/if_gen2' into revamp2
Edw590 Aug 23, 2024
108183c
Update CACHE
Edw590 Aug 23, 2024
e2e9c97
Use DDR_ADDR_W for DDR instead
Edw590 Aug 23, 2024
29849f1
Remove config_setup.mk from BOOTROM
Edw590 Aug 23, 2024
4d90565
Merge pull request #913 from Edw590/revamp2
jjts Aug 23, 2024
616f098
fix(mem): rename memories
P-Miranda Aug 23, 2024
e132467
feat(ram_2p): implement iob_ram_2p
P-Miranda Aug 23, 2024
447598b
Merge pull request #926 from P-Miranda/mem
jjts Aug 23, 2024
d8b2a56
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Aug 23, 2024
390188e
feat(axistream): Update iob_axistream cores to use py2hwsw generated
arturum1 Aug 24, 2024
34b7af3
Merge remote-tracking branch 'origin/if_gen2' into revamp2
Edw590 Aug 25, 2024
ff46a99
feat(regfileif): Inherit instantiator confs; Update py2hwsw.
arturum1 Aug 26, 2024
80a9f8f
Merge pull request #928 from Edw590/revamp2
jjts Aug 26, 2024
fe8a2ec
fix(cyclonev): Fix `rzqin` signal in cyclonev wrapper
arturum1 Aug 26, 2024
1eb39e9
docs(ku040): Add description for ku040 wrapper instances
arturum1 Aug 26, 2024
f7869b7
Merge pull request #929 from arturum1/if_gen2
jjts Aug 26, 2024
a1f0182
refactor(iob_soc): Remove unused "file_prefix" from interfaces
arturum1 Aug 26, 2024
4928581
feat(iob_wishbone2iob): Generate 'wb' interface with if_gen.py
arturum1 Aug 26, 2024
b98de6f
rename bootrom signals
jjts Aug 26, 2024
c928b45
Fix need for ADDR-4 on preboot.S
Edw590 Aug 26, 2024
f3607c5
Merge remote-tracking branch 'origin/if_gen2' into revamp2
Edw590 Aug 26, 2024
63a777b
Attempt at updating according to py2hwsw version
Edw590 Aug 26, 2024
f95e0f0
Rename iob bus to cbus on bootrom
Edw590 Aug 26, 2024
65405b1
Correct includes naming on bootrom.v
Edw590 Aug 26, 2024
729ea64
Merge pull request #930 from Edw590/revamp2
jjts Aug 26, 2024
06cb280
simplify bootrom
jjts Aug 26, 2024
b14ea07
feat(bootrom): Update bootrom with new py2hwsw csrs.
arturum1 Aug 26, 2024
19d5702
Merge branch 'revamp2' of github.com:IObundle/iob-soc into pr_930
arturum1 Aug 26, 2024
1551170
Merge pull request #931 from arturum1/pr_930
jjts Aug 26, 2024
897d632
update cache
jjts Aug 27, 2024
d5f9ad9
reorg files
jjts Aug 27, 2024
fcbafc6
somre refactoring
jjts Aug 27, 2024
e338f01
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Aug 27, 2024
27bfe88
feat(fpga): Rename fpgas according to new py2hwsw version; Fix clean
arturum1 Aug 27, 2024
269a169
fix(bugs): Fix fpga bugs; Add `DEBUG` Makefile argument.
arturum1 Aug 27, 2024
9ec7e02
feat(ku040): Remove automation scripts (improves legibility);
arturum1 Aug 28, 2024
f64d565
Merge pull request #932 from arturum1/if_gen2
jjts Aug 28, 2024
41dc0ec
Update CACHE
Edw590 Aug 28, 2024
1fdce51
Merge remote-tracking branch 'origin/if_gen2' into revamp2
Edw590 Aug 28, 2024
d417e79
feat(fpga): Rename fpga files; Add iob_reset_sync to xilinx_clock_wiz…
arturum1 Aug 28, 2024
9fa87fc
feat(iob_soc): Apply improvements suggested in PR #935
arturum1 Aug 29, 2024
18a9c02
Merge branch 'pr_935' of github.com:arturum1/iob-soc into if_gen2
arturum1 Aug 29, 2024
5174ce4
refactor(iob_soc): Refactor iob_soc.py; Move lib modules into correct
arturum1 Aug 29, 2024
f349ac7
chore(cache): Update CACHE submodule
arturum1 Aug 29, 2024
6c0c71d
Merge pull request #936 from arturum1/if_gen2
jjts Aug 29, 2024
e90489f
feat(axi_interconnect): Create wrapper for axi_interconnect
arturum1 Aug 29, 2024
1c326bc
feat(cyclonev): Update CycloneV wrapper to use new
arturum1 Aug 29, 2024
c50ee59
feat(sim_wrapper): Use new axi_interconnect_wrapper;
arturum1 Aug 29, 2024
10b17b3
refactor(wrappers): Refactor iob-soc wrappers
arturum1 Aug 29, 2024
39388c3
feat(bootrom): Generate iob_bootrom with py2hwsw; Fix iob-soc warnings.
arturum1 Aug 29, 2024
ad687cf
fix(cyclonev): Fix clock signal
arturum1 Aug 30, 2024
f79ce2a
Create iob_rom_2p
Edw590 Aug 30, 2024
c141add
Merge pull request #937 from arturum1/if_gen2
jjts Aug 30, 2024
43db60f
feat(nix): Add support for `PY2HWSW_PATH` environment variable.
arturum1 Aug 30, 2024
81a982a
refactor(lib): Refactor lib Makefile
arturum1 Aug 30, 2024
c168ecf
module iob_ram_sp_generated with py2hwsw
mbot27 Aug 30, 2024
e5dd9ea
feat(lib): Add missing regs in lib modules; Update py2hwsw.
arturum1 Aug 30, 2024
2c57a8d
Merge pull request #939 from mbot27/ram2
jjts Aug 30, 2024
044593f
Add ready signals to iob_rom_2p
Edw590 Aug 31, 2024
d774683
Merge branch 'IObundle:if_gen2' into if_gen2
Edw590 Aug 31, 2024
1abbc78
feat(py2hwsw): Update py2hwsw version
arturum1 Sep 2, 2024
7b3dcb4
module iob_ram_2p generated with py2hwsw
mbot27 Sep 2, 2024
1eb3118
Merge pull request #940 from arturum1/if_gen2
jjts Sep 2, 2024
b65e54d
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into ram2
mbot27 Sep 2, 2024
4f8fdc1
Merge pull request #941 from mbot27/ram2
jjts Sep 2, 2024
d880fd3
add future block diagram
jjts Sep 2, 2024
0209c09
feat(fifos): Add confs to FIFOs python modules
arturum1 Sep 3, 2024
f963808
fix figure
jjts Sep 4, 2024
83cdb04
feat(vex): Add VexRiscV CPU; Use single bootrom;
arturum1 Sep 4, 2024
6e81cb8
module iob_ram_at2p generated with py2hwsw
mbot27 Sep 6, 2024
a27903b
changes in module iob_ram_at2p
mbot27 Sep 6, 2024
2758e15
module iob_ram_atdp generated with py2hwsw
mbot27 Sep 6, 2024
fd6d7a3
fix(setup): Fix setup issues
arturum1 Sep 6, 2024
dbc8f29
wip(interconnect): Add support for interconnect master interfaces with
arturum1 Sep 6, 2024
0a9d463
fix(iob-soc): Remove pbus split; Fix address ranges.
arturum1 Sep 6, 2024
86d02ac
feat(axi): Remove axi2iob converters; Use all peripherals with AXI cbus.
arturum1 Sep 6, 2024
bbff026
module iob_ram_atdp_be generated with py2hwsw
mbot27 Sep 6, 2024
524888d
module iob_ram_sp_be generated with py2hwsw
mbot27 Sep 6, 2024
0adb9d5
module iob_ram_sp_se generated with py2hwsw
mbot27 Sep 6, 2024
e742943
modules iob_ram_t2ps generated with py2hwsw
mbot27 Sep 7, 2024
f1f2f4c
modules iob_ram_tdps generated with py2hwsw
mbot27 Sep 7, 2024
7a59187
feat(csrs): Add wires for new csrs "IOb" output interface;
arturum1 Sep 8, 2024
0c3c04d
Update lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py
mbot27 Sep 8, 2024
9dada39
Update lib/hardware/memories/ram/iob_ram_tdp_be/iob_ram_tdp_be.py
mbot27 Sep 8, 2024
2a11bc9
Merge pull request #943 from mbot27/ram2
jjts Sep 9, 2024
9988c11
refactor(rom): Apply suggestion from https://github.com/IObundle/iob-…
arturum1 Sep 9, 2024
558358f
Merge pull request #944 from arturum1/pr_938
jjts Sep 9, 2024
390fcb6
fix(bugs): Fix iob-soc and depedencies.
arturum1 Sep 9, 2024
7df9aad
feat(ci): Remove unused CACHE test.
arturum1 Sep 10, 2024
d8d6abf
fix(bugs): Fix fpga depedencies; pc-emul sources; axi_ram;
arturum1 Sep 10, 2024
265c1d9
fix(vivado): Add missing include for axi_ram.v source
arturum1 Sep 10, 2024
a9a91b1
feat(axi_ram): Update axi_ram source to remove SystemVerilog syntax.
arturum1 Sep 10, 2024
3cecc5f
Merge pull request #945 from arturum1/if_gen2
jjts Sep 10, 2024
8d365b8
wip(axil_split): Add axil_split module; Add axi2axil bridge; Use axil
arturum1 Sep 12, 2024
f57db1e
fix(iob-soc): Fix bugs in axil_split and iob-soc.
arturum1 Sep 12, 2024
fc7c6dc
fix(lib): Fix axi_rlast signal of axi2axil; Fix txdata reg of iob_uart.
arturum1 Sep 13, 2024
41db4fd
feat(gpio): Add python parameters
arturum1 Sep 13, 2024
c008c4f
Merge pull request #946 from arturum1/if_gen2
jjts Sep 13, 2024
234dce7
feat(bus_width_converter): add bus width converter module
arturum1 Sep 17, 2024
51e009c
feat(is_peripheral): Add support for 'is_peripheral' block attribute
arturum1 Sep 17, 2024
175906d
feat(iob_system): Rename iob_soc to iob_system; Move system to lib.
arturum1 Sep 17, 2024
11a9846
Update altera cores to new py2 syntaxe
agrevin Sep 18, 2024
337b439
Update py2 version
agrevin Sep 18, 2024
12cbc5a
Update amd directiory to new py2 syntax
agrevin Sep 18, 2024
7712ab1
Update counter directory to new py2 syntax
agrevin Sep 18, 2024
1394dba
Update arith directory to new py2 syntax
agrevin Sep 18, 2024
f9cfc4d
Update buses directory to new py2 syntax
agrevin Sep 18, 2024
6c85590
Update clocks, fifo, gpio, picorv32, regileiif, timer, uart directori…
agrevin Sep 18, 2024
faec986
Update shifters and synchronizers directories to new py2 syntax
agrevin Sep 18, 2024
a994b32
Update memories directory to new py2 syntax
agrevin Sep 18, 2024
f64ef20
Update py2 version to accomodate csrs with new syntax
agrevin Sep 18, 2024
65d4a7d
Change csrs connections
agrevin Sep 18, 2024
5c254b4
Update iob_soc syntax to new lib
agrevin Sep 19, 2024
f5f8479
Update syntax of bootrom
agrevin Sep 19, 2024
7da179f
Update py2 version
agrevin Sep 19, 2024
6045c82
Fix test errors
agrevin Sep 19, 2024
c627654
Remove suffix from wire in uart
agrevin Sep 19, 2024
ba6aae9
Fix pulse_gen
agrevin Sep 19, 2024
7005f3b
Update csrs output connections
agrevin Sep 19, 2024
a104a81
Fix iob_nco
agrevin Sep 19, 2024
d5b6baf
Remove data_nxt_o wire in nco
agrevin Sep 19, 2024
f1916d6
Update nco sync
agrevin Sep 19, 2024
3e97cc3
updated vex
agrevin Sep 19, 2024
4739dfa
change vexriscv connections
agrevin Sep 19, 2024
acbbb1c
Fix axi interconnect wrapper connections
agrevin Sep 19, 2024
328e25e
Fix ALL wrapper connections
agrevin Sep 19, 2024
71211c4
Update bootrom connections to csrs
agrevin Sep 19, 2024
a848153
Update hardware directory to new py2 syntax
agrevin Sep 19, 2024
797aaa9
Fix sim wrapper connections
agrevin Sep 19, 2024
d0c5322
Fix sim wrapper connections
agrevin Sep 19, 2024
6c56695
fix soc sim wrapper
agrevin Sep 19, 2024
bc8d2f8
fix soc sim wrapper
agrevin Sep 19, 2024
92dabc8
Update vexriscv
agrevin Sep 19, 2024
5a00b7b
add suffixes
agrevin Sep 19, 2024
a401807
xilinx clock wizard fix
agrevin Sep 19, 2024
187d90d
xilinx clock wizard fix
agrevin Sep 19, 2024
1d7fecf
fix typo
agrevin Sep 20, 2024
94ac191
Merge pull request #951 from agrevin/if_gen2
jjts Sep 20, 2024
4c054b2
fix(iob_system): Fix iob_system setup process
arturum1 Sep 22, 2024
e16b9d7
insert synthesis macro
jjts Sep 22, 2024
72e31c3
update py2hwsw commit
jjts Sep 22, 2024
708a577
update py2hwsw version
jjts Sep 23, 2024
954d292
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Sep 30, 2024
0c5a0eb
feat(bit slice): Resolve some warnings with new bit slice feature of
arturum1 Sep 30, 2024
26dc8c9
feat(cbus): Replace axil peripheral cbus interfaces by iob interfaces.
arturum1 Oct 1, 2024
48d768e
feat(iob_soc): Add example custom firmware
arturum1 Oct 1, 2024
baaf041
feat(iob-soc): Add uart and timer blocks. These override ones from io…
arturum1 Oct 1, 2024
1bf5c46
fix(ci): Increase lib test timout to 20 min
arturum1 Oct 2, 2024
cfd427d
fix(warnings): Fix verilog warnings; Update py2hwsw.
arturum1 Oct 2, 2024
9cc6e27
fix(cbus): Fix cbus width verilog warnings
arturum1 Oct 2, 2024
5569a59
feat(iob_system): Set init_mem to True by default.
arturum1 Oct 2, 2024
64f5782
Merge pull request #953 from arturum1/if_gen2
jjts Oct 2, 2024
3498578
Revert "fix(cbus): Fix cbus width verilog warnings"
arturum1 Oct 2, 2024
b65ed33
feat(peripheral_addr_w): Replace `is_peripheral` attribute by `periph…
arturum1 Oct 3, 2024
577913f
feat(iob_soc): Pass attribute overrides via python paremeters to parent.
arturum1 Oct 3, 2024
5142164
Merge pull request #955 from arturum1/if_gen2
jjts Oct 3, 2024
bd9467a
refactor(system_overrides): Rename `system_overrides` to `system_attr…
arturum1 Oct 3, 2024
e7ea5f0
feat(axi_interconnect_wrapper): Add ADDR_W verilog parameter for each
arturum1 Oct 3, 2024
bce3d0c
license(spdx): Add SPDX license headers with `reuse` tool
arturum1 Oct 4, 2024
19aefda
license(spdx): Add SPDX license headers to project files
arturum1 Oct 5, 2024
d69506e
fix(license): Re-add non-MIT licenses. Re-add copyright holders.
arturum1 Oct 6, 2024
31b00ec
try to add basys3
jjts Oct 6, 2024
998aee4
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 7, 2024
09ada87
license(basys3): Add SPDX license header to basys3.py
arturum1 Oct 7, 2024
305ca06
style(python): Format python code
arturum1 Oct 7, 2024
016d9ff
feat(name): Remove `original_name` and `name` from modules that use t…
arturum1 Oct 7, 2024
3a76391
fix(iob_system): Fix append of child objects in board_list and ignore…
arturum1 Oct 7, 2024
14f32fb
chore(VEXRISCV): Update VEXRISCV submodule
arturum1 Oct 7, 2024
8228338
feat(py2hwsw): Update py2hwsw version
arturum1 Oct 7, 2024
4b24017
feat(ci): Add test to check compliance with REUSE Specification
arturum1 Oct 7, 2024
c63aeb4
feat(lib): Move lib modules to py2hwsw repo
arturum1 Oct 8, 2024
88d1b30
Merge pull request #956 from arturum1/if_gen2
jjts Oct 8, 2024
c4b616d
fix(default.nix): Fix clone of py2hwsw submodules
arturum1 Oct 8, 2024
909c463
try to add a new board zybo z7
jjts Oct 9, 2024
9b159ca
compiles zybo z7
jjts Oct 9, 2024
2d57458
chore(py2hwsw): Update py2hwsw
arturum1 Oct 9, 2024
3b9f038
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 9, 2024
85d44e3
chore(py2hwsw): update py2hwsw
arturum1 Oct 9, 2024
1d79169
Merge pull request #958 from arturum1/if_gen2
jjts Oct 9, 2024
5cefe4b
move default.nix up
jjts Oct 9, 2024
2319cd0
fix and upadte nix
jjts Oct 9, 2024
9bced6e
fix nix
jjts Oct 9, 2024
fa73017
update nix
jjts Oct 9, 2024
4f610a7
feat(nix): Improve default.nix to import the one from py2hwsw.
arturum1 Oct 10, 2024
e08609f
Merge branch 'if_gen2' of github.com:arturum1/iob-soc into if_gen2
arturum1 Oct 10, 2024
fe95028
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 10, 2024
5dbec6d
fix(reuse): Remove unused license file
arturum1 Oct 10, 2024
ddda86f
feat(py2hwsw): Update py2hwsw version.
arturum1 Oct 10, 2024
dac666e
Merge pull request #959 from arturum1/if_gen2
jjts Oct 10, 2024
125ccd4
feat(nix): Update py2 version
arturum1 Oct 16, 2024
ac3487b
fix(cyclonev): Update py2hwsw version
arturum1 Oct 16, 2024
9f1a9cc
fix(use_extmem): Update py2hwsw version
arturum1 Oct 17, 2024
92614f6
docs(README.md): Add readme based on one from iob_system (from py2hwsw).
arturum1 Oct 17, 2024
ac7526a
fix(cyclonev): Update py2hwsw version
arturum1 Oct 17, 2024
ef00f1f
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 17, 2024
d80c356
Merge pull request #962 from arturum1/if_gen2
jjts Oct 17, 2024
7d079b1
update py2hwsw
jjts Oct 20, 2024
35b69fa
update py2hwsw
jjts Oct 20, 2024
04498d7
update py2hwsw
jjts Oct 20, 2024
3c1029d
feat(py2): Update py2hwsw version; Remove clang-format file.
arturum1 Oct 24, 2024
9e63d1f
Merge branch 'if_gen2' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 30, 2024
d8e8560
Merge branch 'main' of github.com:IObundle/iob-soc into if_gen2
arturum1 Oct 31, 2024
338ead3
feat(py2hwsw): Update py2hwsw version; Rename `bsp` to `iob_bsp`.
arturum1 Nov 4, 2024
fc6fcb4
chore(py2): Update py2hwsw version
arturum1 Nov 4, 2024
b3fff91
chore(py2hwsw): Update py2hwsw version
arturum1 Nov 5, 2024
9951ee5
Merge pull request #967 from arturum1/if_gen2
jjts Nov 5, 2024
825313a
chore(py2hwsw): Update py2hwsw version
arturum1 Nov 6, 2024
b737367
chore(py2hwsw): Update py2hwsw to support doc_only
arturum1 Nov 6, 2024
33a5ef3
Merge pull request #968 from arturum1/if_gen2
jjts Nov 6, 2024
a8bd959
Merge branch 'main' of github.com:IObundle/iob-soc into if_gen2
arturum1 Nov 6, 2024
91383e7
chore(py2hwsw): Update py2hwsw version
arturum1 Nov 7, 2024
a2fd712
chore(py2hwsw): Update py2hwsw version
arturum1 Nov 7, 2024
b8530d3
Merge pull request #971 from arturum1/if_gen2
jjts Nov 7, 2024
bb0e2ef
Merge branch 'main' of github.com:IObundle/iob-soc into if_gen2
arturum1 Nov 7, 2024
8104e50
Merge pull request #973 from arturum1/if_gen2
jjts Nov 11, 2024
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3 changes: 0 additions & 3 deletions .clang-format

This file was deleted.

73 changes: 31 additions & 42 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
# SPDX-FileCopyrightText: 2024 IObundle
#
# SPDX-License-Identifier: MIT

name: CI

# Set default shell as interactive (source ~/.bashrc)
Expand Down Expand Up @@ -29,6 +33,8 @@ jobs:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: run test
run: make pc-emul-test

Expand All @@ -43,8 +49,10 @@ jobs:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: run test
run: nix-shell --run "make sim-test"
run: make sim-test

cyclonev:
runs-on: self-hosted
Expand All @@ -56,10 +64,12 @@ jobs:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: init mem and no ext mem
run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=1 USE_EXTMEM=0
run: make fpga-run BOARD=cyclonev_gt_dk INIT_MEM=1 USE_EXTMEM=0
- name: no init mem and ext mem
run: make fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=0 USE_EXTMEM=1
run: make fpga-run BOARD=cyclonev_gt_dk INIT_MEM=0 USE_EXTMEM=1

ku040:
runs-on: self-hosted
Expand All @@ -71,60 +81,39 @@ jobs:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: init mem and no ext mem
run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=1 USE_EXTMEM=0
run: make fpga-run BOARD=aes_ku040_db_g INIT_MEM=1 USE_EXTMEM=0
- name: no init mem and ext mem
run: make fpga-run BOARD=AES-KU040-DB-G INIT_MEM=0 USE_EXTMEM=1
run: make fpga-run BOARD=aes_ku040_db_g INIT_MEM=0 USE_EXTMEM=1

lib:
doc:
runs-on: self-hosted
timeout-minutes: 10
timeout-minutes: 60
if: ${{ !cancelled() }}
needs: [ cyclonev ]

steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: run LIB test
run: nix-shell --run "cd submodules/LIB; ./scripts/test.sh test"

uart:
runs-on: self-hosted
timeout-minutes: 5
if: ${{ !cancelled() }}
needs: [ lib ]


steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: run uart test
run: make -C submodules/UART test
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: doc test
run: make doc-test

cache:
reuse:
runs-on: self-hosted
timeout-minutes: 20
timeout-minutes: 3
if: ${{ !cancelled() }}
needs: [ cyclonev ]
needs: [ doc ]

steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: run simulation test
run: make -C submodules/CACHE sim-test
- name: run fpga test
run: make -C submodules/CACHE fpga-test
doc:
runs-on: self-hosted
timeout-minutes: 60
if: ${{ !cancelled() }}
needs: [ cyclonev ]

steps:
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: doc test
run: nix-shell --run "make -C ../iob_soc_V* doc-test"
- name: Clean untracked files and directories (like old submodules)
run: git clean -ffdx
- name: Check compliance with REUSE specification
run: nix-shell --run "reuse lint"
13 changes: 4 additions & 9 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,9 +1,4 @@
[submodule "submodules/CACHE"]
path = submodules/CACHE
url = [email protected]:IObundle/iob-cache.git
[submodule "submodules/PICORV32"]
path = submodules/PICORV32
url = [email protected]:IObundle/iob-picorv32.git
[submodule "submodules/AXI"]
path = submodules/AXI
url = [email protected]:IObundle/verilog-axi.git
# SPDX-FileCopyrightText: 2024 IObundle
#
# SPDX-License-Identifier: MIT

11 changes: 11 additions & 0 deletions CITATION.cff
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
cff-version: 1.2.0
message: "If you use this software, please cite it as below. If you are contributor, submit a pull request to add you as an author."
authors:
- family-names: "T. de Sousa "
given-names: "Jose"
orcid: "https://orcid.org/0000-0001-7525-7546"
title: "A RISC-V-based System-on-Chip Template"
version: 0.7.2
doi: 10.5281/zenodo.13346032
date-released: 2021-12-18
url: "https://github.com/IObundle/iob-soc"
3 changes: 3 additions & 0 deletions CITATION.cff.license
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
SPDX-FileCopyrightText: 2024 IObundle

SPDX-License-Identifier: MIT
9 changes: 9 additions & 0 deletions LICENSES/MIT.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
MIT License

Copyright (c) <year> <copyright holders>

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
66 changes: 37 additions & 29 deletions Makefile
Original file line number Diff line number Diff line change
@@ -1,61 +1,57 @@
# SPDX-FileCopyrightText: 2024 IObundle
#
# SPDX-License-Identifier: MIT

CORE := iob_soc

SIMULATOR ?= icarus
SYNTHESIZER ?= yosys
BOARD ?= CYCLONEV-GT-DK

DISABLE_LINT:=1
BOARD ?= cyclonev_gt_dk

include submodules/LIB/setup.mk
BUILD_DIR ?= $(shell nix-shell --run "py2hwsw $(CORE) print_build_dir")

INIT_MEM ?= 1
USE_EXTMEM ?= 0


ifeq ($(INIT_MEM),1)
SETUP_ARGS += INIT_MEM
endif

ifeq ($(USE_EXTMEM),1)
SETUP_ARGS += USE_EXTMEM
ifneq ($(DEBUG),)
EXTRA_ARGS +=--debug_level $(DEBUG)
endif

setup:
nix-shell --run 'make build-setup SETUP_ARGS="$(SETUP_ARGS)"'
nix-shell --run "py2hwsw $(CORE) setup --no_verilog_lint --py_params 'init_mem=$(INIT_MEM):use_extmem=$(USE_EXTMEM)' $(EXTRA_ARGS)"

pc-emul-run:
nix-shell --run 'make clean setup && make -C ../$(CORE)_V*/ pc-emul-run'
nix-shell --run "make clean setup && make -C ../$(CORE)_V*/ pc-emul-run"

pc-emul-test:
nix-shell --run 'make clean setup && make -C ../$(CORE)_V*/ pc-emul-run'
nix-shell --run "make clean setup && make -C ../$(CORE)_V*/ pc-emul-run"

sim-run:
nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ fw-build'
nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ sim-run SIMULATOR=$(SIMULATOR)'
nix-shell --run "make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ sim-run SIMULATOR=$(SIMULATOR)"

sim-test:
nix-shell --run 'make clean setup INIT_MEM=1 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=icarus'
nix-shell --run 'make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator'
nix-shell --run 'make clean setup INIT_MEM=1 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator'
nix-shell --run "make clean setup INIT_MEM=1 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=icarus"
nix-shell --run "make clean setup INIT_MEM=0 USE_EXTMEM=0 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator"
nix-shell --run "make clean setup INIT_MEM=0 USE_EXTMEM=1 && make -C ../$(CORE)_V*/ sim-run SIMULATOR=verilator"

fpga-run:
nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD)'
nix-shell --run "make clean setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) && make -C ../$(CORE)_V*/ fpga-fw-build BOARD=$(BOARD)"
make -C ../$(CORE)_V*/ fpga-run BOARD=$(BOARD)

fpga-test:
make clean setup fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=1 USE_EXTMEM=0
make clean setup fpga-run BOARD=CYCLONEV-GT-DK INIT_MEM=0 USE_EXTMEM=1
make clean setup fpga-run BOARD=AES-KU040-DB-G INIT_MEM=1 USE_EXTMEM=0
make clean setup fpga-run BOARD=AES-KU040-DB-G INIT_MEM=0 USE_EXTMEM=1
make clean setup fpga-run BOARD=cyclonev_gt_dk INIT_MEM=1 USE_EXTMEM=0
make clean setup fpga-run BOARD=cyclonev_gt_dk INIT_MEM=0 USE_EXTMEM=1
make clean setup fpga-run BOARD=aes_ku040_db_g INIT_MEM=1 USE_EXTMEM=0
make clean setup fpga-run BOARD=aes_ku040_db_g INIT_MEM=0 USE_EXTMEM=1

syn-build: clean
nix-shell --run 'make setup && make -C ../$(CORE)_V*/ syn-build SYNTHESIZER=$(SYNTHESIZER)'
nix-shell --run "make setup && make -C ../$(CORE)_V*/ syn-build SYNTHESIZER=$(SYNTHESIZER)"

doc-build:
nix-shell --run 'make clean setup && make -C ../$(CORE)_V*/ doc-build'
nix-shell --run "make clean setup && make -C ../$(CORE)_V*/ doc-build"

doc-test:
nix-shell --run 'make clean setup && make -C ../$(CORE)_V*/ doc-test'
nix-shell --run "make clean setup && make -C ../$(CORE)_V*/ doc-test"


test-all: pc-emul-test sim-test fpga-test doc-test
Expand All @@ -64,12 +60,24 @@ test-all: pc-emul-test sim-test fpga-test doc-test

# Install board server and client
board_server_install:
make -C submodules/LIB board_server_install
make -C lib board_server_install

board_server_uninstall:
make -C submodules/LIB board_server_uninstall
make -C lib board_server_uninstall

board_server_status:
systemctl status board_server

.PHONY: setup sim-test fpga-test doc-test test-all board_server_install board_server_uninstall board_server_status


clean:
nix-shell --run "py2hwsw $(CORE) clean --build_dir '$(BUILD_DIR)'"
@rm -rf ../*.summary ../*.rpt
@find . -name \*~ -delete

# Remove all __pycache__ folders with python bytecode
python-cache-clean:
find . -name "*__pycache__" -exec rm -rf {} \; -prune

.PHONY: clean python-cache-clean
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