modules iob_ram_t2ps generated with py2hwsw

lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py

@@ -3,7 +3,126 @@ def setup(py_params_dict):
         "original_name": "iob_ram_t2p",
         "name": "iob_ram_t2p",
         "version": "0.1",
-        "generate_hw": False,
+        "confs": [
+            {
+                "name": "HEXFILE",
+                "type": "P",
+                "val": '"none"',
+                "min": "NA",
+                "max": "NA",
+                "descr": "Name of file to load into RAM",
+            },
+            {
+                "name": "ADDR_W",
+                "type": "P",
+                "val": "0",
+                "min": "0",
+                "max": "NA",
+                "descr": "Address bus width",
+            },
+            {
+                "name": "DATA_W",
+                "type": "P",
+                "val": "0",
+                "min": "0",
+                "max": "NA",
+                "descr": "Data bus width",
+            },
+            {
+                "name": "MEM_INIT_FILE_INT",
+                "type": "F",
+                "val": "HEXFILE",
+                "min": "0",
+                "max": "NA",
+                "descr": "",
+            },
+        ],
+        "ports": [
+            {
+                "name": "clk",
+                "descr": "Clock",
+                "signals": [
+                    {"name": "clk", "width": 1, "direction": "input"},
+                ],
+            },
+            {
+                "name": "w_en_i",
+                "descr": "Input port",
+                "signals": [
+                    {"name": "w_en", "width": 1, "direction": "input"},
+                ],
+            },
+            {
+                "name": "w_addr_i",
+                "descr": "Input port",
+                "signals": [
+                    {"name": "w_addr", "width": "ADDR_W", "direction": "input"},
+                ],
+            },
+            {
+                "name": "w_data_i",
+                "descr": "Input port",
+                "signals": [
+                    {"name": "w_data", "width": "DATA_W", "direction": "input"},
+                ],
+            },
+            {
+                "name": "r_en_i",
+                "descr": "Input port",
+                "signals": [
+                    {"name": "r_en", "width": 1, "direction": "input"},
+                ],
+            },
+            {
+                "name": "r_addr_i",
+                "descr": "Input port",
+                "signals": [
+                    {"name": "r_addr", "width": "ADDR_W", "direction": "input"},
+                ],
+            },
+            {
+                "name": "r_data_o",
+                "descr": "Output port",
+                "signals": [
+                    {"name": "r_data", "width": "DATA_W", "direction": "output"},
+                ],
+            },
+        ],
+        "snippets": [
+            {
+                "verilog_code": """
+            
+
+
+   // Declare the RAM
+   reg [DATA_W-1:0] mem    [(2**ADDR_W)-1:0];
+
+   reg [DATA_W-1:0] r_data;
+   // Initialize the RAM
+   initial begin
+       if (MEM_INIT_FILE_INT != "none") begin
+           $readmemh(MEM_INIT_FILE_INT, mem, 0, (2 ** ADDR_W) - 1);
+       end
+   end
+
+   //read port
+   always @(posedge clk_i) begin
+       if (r_en_i) begin
+           r_data <= mem[r_addr_i];
+       end
+   end
+
+   //write port
+   always @(posedge clk_i) begin
+       if (w_en_i) begin
+           mem[w_addr_i] <= w_data_i;
+       end
+   end
+
+   assign r_data_o = r_data;
+            """,
+            },
+        ],
     }
 
     return attributes_dict