feat(cbus): Replace axil peripheral cbus interfaces by iob interfaces.

Fix some verilog warnings with bit slicing. Fix lib modules.
IObundle · Oct 1, 2024 · 26dc8c9 · 26dc8c9
1 parent 0c5a0eb
commit 26dc8c9
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Showing 8 changed files with 87 additions and 36 deletions.
diff --git a/lib/hardware/buses/iob2axil/iob2axil.py b/lib/hardware/buses/iob2axil/iob2axil.py
@@ -4,6 +4,62 @@ def setup(py_params_dict):
         "name": "iob2axil",
         "version": "0.1",
         "generate_hw": False,
+        "confs": [
+            {
+                "name": "AXIL_ADDR_W",
+                "descr": "",
+                "type": "P",
+                "val": "21",
+                "min": "1",
+                "max": "32",
+            },
+            {
+                "name": "AXIL_DATA_W",
+                "descr": "",
+                "type": "P",
+                "val": "21",
+                "min": "1",
+                "max": "32",
+            },
+            {
+                "name": "ADDR_W",
+                "descr": "",
+                "type": "P",
+                "val": "21",
+                "min": "1",
+                "max": "32",
+            },
+            {
+                "name": "DATA_W",
+                "descr": "",
+                "type": "P",
+                "val": "21",
+                "min": "1",
+                "max": "32",
+            },
+        ],
+        "ports": [
+            {
+                "name": "iob_s",
+                "descr": "Slave IOb interface",
+                "interface": {
+                    "type": "iob",
+                    "subtype": "slave",
+                    "ADDR_W": "ADDR_W",
+                    "DATA_W": "DATA_W",
+                },
+            },
+            {
+                "name": "axil_m",
+                "descr": "Master AXI Lite interface",
+                "interface": {
+                    "type": "axil",
+                    "subtype": "master",
+                    "ADDR_W": "AXIL_ADDR_W",
+                    "DATA_W": "AXIL_DATA_W",
+                },
+            },
+        ],
     }
 
     return attributes_dict
diff --git a/lib/hardware/buses/iob_split/iob_split.py b/lib/hardware/buses/iob_split/iob_split.py
@@ -215,7 +215,7 @@ def setup(py_params_dict):
             },
             "connect": {
                 "clk_en_rst_s": "clk_en_rst_s",
-                "en_rst_s": "sel_reg_en_rst",
+                "en_rst_i": "sel_reg_en_rst",
                 "data_i": "sel_reg_data_i",
                 "data_o": "sel_reg_data_o",
             },

diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py
@@ -257,6 +257,7 @@ def setup(py_params_dict):
                 "ADDR_W": params["addr_w"] - 2,
                 "DATA_W": "AXI_DATA_W",
                 "LEN_W": "AXI_LEN_W",
+                "LOCK_W": "1",
             },
         },
         {
@@ -272,10 +273,10 @@ def setup(py_params_dict):
             },
         },
         {
-            "name": "axil_periphs_cbus",
+            "name": "iob_periphs_cbus",
             "descr": "AXI-Lite bus for peripheral CSRs",
             "interface": {
-                "type": "axil",
+                "type": "iob",
                 "wire_prefix": "periphs_",
                 "ID_W": "AXI_ID_W",
                 "ADDR_W": params["addr_w"] - 1,
@@ -317,13 +318,11 @@ def setup(py_params_dict):
                 "plic_interrupts_i": "interrupts",
                 "plic_cbus_s": (
                     "plic_cbus",
-                    "plic_cbus_axil_araddr[22-1:0]",
-                    "plic_cbus_axil_awaddr[22-1:0]",
+                    "plic_cbus_iob_addr[22-1:0]",
                 ),
                 "clint_cbus_s": (
                     "clint_cbus",
-                    "clint_cbus_axil_araddr[16-1:0]",
-                    "clint_cbus_axil_awaddr[16-1:0]",
+                    "clint_cbus_iob_addr[16-1:0]",
                 ),
             },
         },
@@ -348,7 +347,11 @@ def setup(py_params_dict):
                     "axi_awlock[0]",
                 ),
                 "bootrom_axi_m": "bootrom_cbus",
-                "peripherals_axi_m": "axi_periphs_cbus",
+                "peripherals_axi_m": (
+                    "axi_periphs_cbus",
+                    "periphs_axi_awlock[0]",
+                    "periphs_axi_arlock[0]",
+                ),
             },
             "num_slaves": 2,
             "masters": {
@@ -376,29 +379,29 @@ def setup(py_params_dict):
             "soc_name": params["name"],
         },
         {
-            "core_name": "axi2axil",
-            "instance_name": "periphs_axi2axil",
+            "core_name": "axi2iob",
+            "instance_name": "periphs_axi2iob",
             "instance_description": "Convert AXI to AXI lite for CLINT",
             "parameters": {
-                "AXI_ID_W": "AXI_ID_W",
-                "AXI_ADDR_W": params["addr_w"] - 1,
-                "AXI_DATA_W": "AXI_DATA_W",
-                "AXI_LEN_W": "AXI_LEN_W",
+                "AXI_ID_WIDTH": "AXI_ID_W",
+                "ADDR_WIDTH": params["addr_w"] - 1,
+                "DATA_WIDTH": "AXI_DATA_W",
             },
             "connect": {
+                "clk_en_rst_s": "clk_en_rst_s",
                 "axi_s": "axi_periphs_cbus",
-                "axil_m": "axil_periphs_cbus",
+                "iob_m": "iob_periphs_cbus",
             },
         },
         {
-            "core_name": "iob_axil_split",
-            "name": "iob_axil_pbus_split",
-            "instance_name": "iob_axil_pbus_split",
+            "core_name": "iob_split",
+            "name": "iob_pbus_split",
+            "instance_name": "iob_pbus_split",
             "instance_description": "Split between peripherals",
             "connect": {
                 "clk_en_rst_s": "clk_en_rst_s",
                 "reset_i": "split_reset",
-                "input_s": "axil_periphs_cbus",
+                "input_s": "iob_periphs_cbus",
                 # Peripherals cbus connections added automatically
             },
             "num_outputs": 0,  # Num outputs configured automatically

diff --git a/lib/hardware/iob_system/scripts/iob_system_utils.py b/lib/hardware/iob_system/scripts/iob_system_utils.py
@@ -72,7 +72,7 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params):
     # Find pbus_split
     pbus_split = None
     for block in attributes_dict["blocks"]:
-        if block["instance_name"] == "iob_axil_pbus_split":
+        if block["instance_name"] == "iob_pbus_split":
             pbus_split = block
 
     # Number of peripherals = peripherals + CLINT + PLIC
@@ -90,12 +90,9 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params):
                 "name": f"{peripheral_name}_cbus",
                 "descr": f"{peripheral_name} Control/Status Registers bus",
                 "interface": {
-                    "type": "axil",
+                    "type": "iob",
                     "wire_prefix": f"{peripheral_name}_cbus_",
-                    "ID_W": "AXI_ID_W",
                     "ADDR_W": peripheral_addr_w,
-                    "DATA_W": "AXI_DATA_W",
-                    "LEN_W": "AXI_LEN_W",
                 },
             },
         )
@@ -110,24 +107,18 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params):
             "name": "clint_cbus",
             "descr": "CLINT Control/Status Registers bus",
             "interface": {
-                "type": "axil",
+                "type": "iob",
                 "wire_prefix": "clint_cbus_",
-                "ID_W": "AXI_ID_W",
                 "ADDR_W": peripheral_addr_w,
-                "DATA_W": "AXI_DATA_W",
-                "LEN_W": "AXI_LEN_W",
             },
         },
         {
             "name": "plic_cbus",
             "descr": "PLIC Control/Status Registers bus",
             "interface": {
-                "type": "axil",
+                "type": "iob",
                 "wire_prefix": "plic_cbus_",
-                "ID_W": "AXI_ID_W",
                 "ADDR_W": peripheral_addr_w,
-                "DATA_W": "AXI_DATA_W",
-                "LEN_W": "AXI_LEN_W",
             },
         },
     ]

diff --git a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py
@@ -84,6 +84,7 @@ def setup(py_params_dict):
                     "port_prefix": "cbus_",
                     "ADDR_W": BOOTROM_ADDR_W,
                     "DATA_W": "DATA_W",
+                    "LOCK_W": "1",
                 },
             },
             {

diff --git a/lib/hardware/iob_system/submodules/VEXRISCV b/lib/hardware/iob_system/submodules/VEXRISCV
diff --git a/lib/hardware/iob_timer/iob_timer.py b/lib/hardware/iob_timer/iob_timer.py
@@ -41,7 +41,7 @@ def setup(py_params_dict):
             {
                 "name": "cbus_s",
                 "interface": {
-                    "type": "axil",
+                    "type": "iob",
                     "subtype": "slave",
                     "ADDR_W": "4",  # Same as `IOB_TIMER_CSRS_ADDR_W
                     "DATA_W": "DATA_W",
@@ -174,7 +174,7 @@ def setup(py_params_dict):
                         ],
                     },
                 ],
-                "csr_if": "axil",
+                "csr_if": "iob",
                 "connect": {
                     "clk_en_rst_s": "clk_en_rst_s",
                     "control_if_s": "cbus_s",

diff --git a/lib/hardware/iob_uart/iob_uart.py b/lib/hardware/iob_uart/iob_uart.py
@@ -1,5 +1,5 @@
 def setup(py_params_dict):
-    CSR_IF = py_params_dict["csr_if"] if "csr_if" in py_params_dict else "axil"
+    CSR_IF = py_params_dict["csr_if"] if "csr_if" in py_params_dict else "iob"
     NAME = py_params_dict["name"] if "name" in py_params_dict else "iob_uart"
     attributes_dict = {
         "original_name": "iob_uart",