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Removed debug counters, added vacc N control
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kiranshila committed Aug 15, 2023
1 parent cdc4d90 commit 566d990
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Showing 3 changed files with 38 additions and 4 deletions.
Binary file modified grex_gateware.slx
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2 changes: 1 addition & 1 deletion requant_config.m
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ function requant_config(this_block)
data_out_port.setType('UFix_16_0');

addr_port = this_block.port('addr');
addr_port.setType('UFix_12_0');
addr_port.setType('UFix_11_0');

% -----------------------------
if (this_block.inputTypesKnown)
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40 changes: 37 additions & 3 deletions vacc_config.m
Original file line number Diff line number Diff line change
@@ -1,10 +1,28 @@

function vacc_config(this_block)

% Revision History:
%
% 14-Aug-2023 (18:03 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% /home/casper/Desktop/gateware/hdl/artifacts/vacc.v
%
%

this_block.setTopLevelLanguage('Verilog');

this_block.setEntityName('vacc');

% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
% this_block.tagAsCombinational;

this_block.addSimulinkInport('rst');
this_block.addSimulinkInport('acc_n');
this_block.addSimulinkInport('data_in');
this_block.addSimulinkInport('sync');
this_block.addSimulinkInport('trig');

this_block.addSimulinkOutport('data_out');
this_block.addSimulinkOutport('we');
this_block.addSimulinkOutport('addr');
Expand All @@ -28,10 +46,15 @@ function vacc_config(this_block)
end

this_block.port('rst').useHDLVector(false);


if (this_block.port('acc_n').width ~= 32);
this_block.setError('Input data type for port "acc_n" must have width=32.');
end

if (this_block.port('data_in').width ~= 32);
this_block.setError('Input data type for port "data_in" must have width=32.');
end

if (this_block.port('sync').width ~= 1);
this_block.setError('Input data type for port "sync" must have width=1.');
end
Expand All @@ -43,7 +66,6 @@ function vacc_config(this_block)
end

this_block.port('trig').useHDLVector(false);

end % if(inputTypesKnown)
% -----------------------------

Expand All @@ -59,11 +81,23 @@ function vacc_config(this_block)
% on input types, make the settings in the "inputTypesKnown" code block.
% The addGeneric function takes 3 parameters, generic name, type and constant value.
% Supported types are boolean, real, integer and string.
this_block.addGeneric('ACCUMULATIONS','integer','262144');
this_block.addGeneric('VECTOR_WIDTH','integer','11');
this_block.addGeneric('INPUT_WIDTH','integer','32');
this_block.addGeneric('OUTPUT_WIDTH','integer','64');

% Add addtional source files as needed.
% |-------------
% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
% | this_block.addFile('b.vhd');
% | this_block.addFile('a.vhd');
% |-------------

% this_block.addFile('');
% this_block.addFile('');
this_block.addFile('hdl/artifacts/dpram.v');
this_block.addFile('hdl/artifacts/vacc.v');

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