Rename bitmanip constraints

Files Changed: * constraints.md: Change contraint names. * corev.md: Likewise.
EEESlab · Nov 2, 2023 · b14af4e · b14af4e
1 parent 4a6bad0
commit b14af4e
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Showing 2 changed files with 7 additions and 12 deletions.
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
@@ -168,16 +168,11 @@
        (and (match_test "IN_RANGE (ival, 0, 1073741823)")
             (match_test "exact_log2 (ival + 1) != -1"))))
 
-(define_constraint "M"
+(define_constraint "MVs10"
   "A 10-bit unsigned immediate for CORE-V bitmanip."
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, 0, 1023)")))
 
-(define_constraint "N"
-  "A 2-bit unsigned immediate for CORE-V bitmanip."
-  (and (match_code "const_int")
-       (match_test "IN_RANGE (ival, 0, 3)")))
-
 (define_constraint "CVs6"
   "A 6-bit signed immediate for SIMD."
   (and (match_code "const_int")

diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
@@ -922,7 +922,7 @@
 (define_expand "riscv_cv_bitmanip_extract"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-                   (match_operand:HI 2 "bit_extract_operand" "M,r")]
+                   (match_operand:HI 2 "bit_extract_operand" "MVs10,r")]
          UNSPEC_CV_BITMANIP_EXTRACT))]
 
   "TARGET_XCVBITMANIP && !TARGET_64BIT"
@@ -972,7 +972,7 @@
 (define_expand "riscv_cv_bitmanip_extractu"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-                   (match_operand:HI 2 "bit_extract_operand" "M,r")]
+                   (match_operand:HI 2 "bit_extract_operand" "MVs10,r")]
          UNSPEC_CV_BITMANIP_EXTRACTU))]
 
   "TARGET_XCVBITMANIP && !TARGET_64BIT"
@@ -1024,7 +1024,7 @@
 (define_expand "riscv_cv_bitmanip_insert"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-                   (match_operand:HI 2 "bit_extract_operand" "M,r")
+                   (match_operand:HI 2 "bit_extract_operand" "MVs10,r")
                    (match_operand:SI 3 "register_operand" "0,0")]
          UNSPEC_CV_BITMANIP_INSERT))]
 
@@ -1077,7 +1077,7 @@
 (define_expand "riscv_cv_bitmanip_bclr"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-                   (match_operand:HI 2 "bit_extract_operand" "M,r")]
+                   (match_operand:HI 2 "bit_extract_operand" "MVs10,r")]
          UNSPEC_CV_BITMANIP_BCLR))]
 
   "TARGET_XCVBITMANIP && !TARGET_64BIT"
@@ -1127,7 +1127,7 @@
 (define_expand "riscv_cv_bitmanip_bset"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-                   (match_operand:HI 2 "bit_extract_operand" "M,r")]
+                   (match_operand:HI 2 "bit_extract_operand" "MVs10,r")]
          UNSPEC_CV_BITMANIP_BSET))]
 
   "TARGET_XCVBITMANIP && !TARGET_64BIT"
@@ -1207,7 +1207,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
                     (match_operand:QI 2 "const_csr_operand" "K")
-                    (match_operand:QI 3 "const_int2_operand" "N")]
+                    (match_operand:QI 3 "const_int2_operand" "D03")]
          UNSPEC_CV_BITMANIP_BITREV))]
 
   "TARGET_XCVBITMANIP && !TARGET_64BIT"