#2384: trace: add some manual timings

DARMA-tasking · Jan 9, 2025 · 661437a · 661437a
1 parent fc07449
commit 661437a
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Showing 3 changed files with 24 additions and 0 deletions.
diff --git a/src/vt/trace/trace.cc b/src/vt/trace/trace.cc
@@ -67,6 +67,8 @@
 
 namespace vt { namespace trace {
 
+std::unordered_map<std::string, double> manual_timings;
+
 using TraceContainersType = TraceContainers;
 
 using LogType = Trace::LogType;
@@ -119,6 +121,13 @@ void Trace::finalize() /*override*/ {
   // Always end any between-loop event left open.
   endProcessing(between_sched_event_, timing::getCurrentTime());
   between_sched_event_ = TraceProcessingTag{};
+
+  fmt::print("{}: ", theContext()->getNode());
+  for (auto const& [name, time] : manual_timings) {
+    fmt::print("({},{}) ", name, time);
+  }
+  fmt::print("\n");
+  fflush(stdout);
 }
 
 void Trace::loadAndBroadcastSpec() {

diff --git a/src/vt/trace/trace.h b/src/vt/trace/trace.h
@@ -64,6 +64,8 @@
 
 namespace vt { namespace trace {
 
+extern std::unordered_map<std::string, double> manual_timings;
+
 /// Tracking information for beginProcessing/endProcessing.
 struct TraceProcessingTag {
 

diff --git a/src/vt/vrt/collection/balance/baselb/baselb.cc b/src/vt/vrt/collection/balance/baselb/baselb.cc
@@ -77,9 +77,22 @@ std::shared_ptr<const balance::Reassignment> BaseLB::startLB(
   importProcessorData(in_stats, in_comm_lb_data, in_data_map);
 
   runInEpochCollective("BaseLB::startLB -> runLB", [this,total_load]{
+
+    auto t1 = timing::getCurrentTime();
     getArgs(phase_);
+    auto t2 = timing::getCurrentTime();
+    trace::manual_timings["getArgs"] = t2-t1;
+
     inputParams(config_entry_.get());
+
+    auto t3 = timing::getCurrentTime();
+    trace::manual_timings["inputParams"] = t3-t2;
+
     runLB(total_load);
+
+    auto t4 = timing::getCurrentTime();
+    trace::manual_timings["runLB"] = t4-t3;
+
   });
 
   return normalizeReassignments();