Merge pull request #17 from CIDARLAB/dev

fixed verilog template
CIDARLAB · Apr 30, 2024 · 8b8e644 · 8b8e644
2 parents 8bcb55a + 525b5cd
commit 8b8e644
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/library/templates/cello_verilog_template.v b/library/templates/cello_verilog_template.v
@@ -14,7 +14,7 @@ module and_gate (in_A, in_B, out);
 
     output out;
 
-    assign out = in_A & in_B;
+    and(out, in_A, in_B);
 
 endmodule