Hi this is Awadhesh Chauhan sharing my github repsository of the workshop held between 3-7th August 2022 in online mode in collibration with efabless. First of all , I will try to brief about workshop.
First of all , I will try to brief about workshop.
This worskshop held between 3 to 7th August 2022 with the title "sky130-pd-workshop". It was basically about physical design. I get to learn the whole physical design flow with tool Openlane flow.
What is Openlane?
Openalane is automated RTL to GDSII flow, an tcl based complete flow for Physical design. It is the supeset of the tolls like OPenRoad, Yosys, Netgen, CVC, SPEF_Extractor, CU-GR, Klayout and a lot of custom scripting of python and tcl for optimization and exploration. This opensource floe is tasted for full ASIC implementation steps from RTL to GDSII.
this is the openlan flow block diagram ,it tells at what stage which tool is used along with the flow.
Introduction to openlab flow lab
In this we were given lab access with pre installed openlane flow. Actually openlane flow is installed using docker. Before running the flow we have to invoke docker using the docker command
RUN ./flow.tcl -interactive
after doing the above step : %package require openlane 0.9 it sync all the package required to the openlane specific version
prep -design picorv32a -->design setup stage
synthesis
Synthesis is the process of conversion of the program into the circuit linke interms of flops, gates ect. In this flow Yosys for synthesis and abc for technology mapping has been used.
to run synthesis below command is used
run_synthesis
after running this the synthesised rtl is saved at the location
awadhesh.chauhan@sky130-pd-workshop-02:~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/results/synthesis$
from the generated output report we get to know
The flop ratio = 1613/14876=0.1084
The buffer ratio = 1656/14876
Below are the reports that are generated after synthesis:
Floorplan
In physical design , floorplaning is the step of determining the size,shape and locations of modules in a chip and to estimate the total chip area,delay and interconnects
to run floorplaning below command is used :
run_floorplan
Magic view of floorplans:
This the zoomed view of the specific part:
if we to change any paprmeter we can use this way . In the above images pin placements are with equal spacing but we want to change it to random spacing of the pins
We updated the property and saw the result again.
In this image pin placement is random.
Placement
Placement is the way of determining the locations of the circuit devices on a die of the chip.It gives effect on routablity,performance,heat distribution and a little bit power consumption.
CMOS STANDARD CELL
We have to download the vsdstdcelldesign from the github below provided link:
clone https://github.com/nickson-jose/vsdstdcelldesign.git to clone std cell library at openlane folder and it will create folder name vsdstdcelldesign
copied sky130A.tech :
Below command is use dto run inverter in the magic to see layout:
awadhesh.chauhan@sky130-pd-workshop-02:~/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign$ magic -T sky130A.tech sky130_inv.mag & The inverter Layout
Extract spice netlist
This generates teh sky130_inv.ext and sky130_inv.spice files.
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
Spice file
the updated spice file
We have Update the sky130_inv.spice file to use the correct scaling factor and models. From the tkcon the root cell box is 0.01 x 0.01 microns. The scale is change to `.option scale =0.01u'
Simulating the spice file
Plotting the result plot y vs time a
Inverter Cell
Going the the directroy and running magic by the below command
magic -d XR -T sky130A.tech sky130_inv.mag&
magic -d XR -T sky130A.tech sky130_inv.mag&
save the file
Location of the file where its is saved
Open the new file using magic -d XR -T sky130A.tech sky130_jayinv.mag&
SRC file setup
cd /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign/extras
cp my_base.sdc /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
cd /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign/
copy the sky130 libraries to the picorv32a/src
config.tcl
Modify the config.tcl to include the copied libraries at /home/p-brane/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/config.tcl The modified file is shown below. LIB_MIN was replaced with LIB_FASTEST, and LIB_MAX was replace with LIB_SLOWEST.
Now run openlane
docker ./flow.tcl interactive
package require openlane 0.9
prep -design picorv32a -tag 04-08_06-57 -overwrite
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
run_synthesis
Static time analysis
Floorplan
Now , We have to run the following commmands sequentially
init_floorplan
place_io
global_placement_or
detailed_placement
tap_decap_or
detailed_placement
gen_pdn
run_routing
Magic
Now we are going to view the placement on magic using the below command
magic -d XR -T /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/tmp/merged.lef def read /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/results/placement/picorv32a.placement.def&
power Distribution Network
As placement gets all legality checks, we run the gen_pdn command to generate th PDN.
Routing Routing is the process of stablishing physical connections betweeen signal pins using metal layers is called routing.It is a stage after CTS and optimizing when exact paths for the interconnection of standard cells and macros and I/O pins are determined.
run_routing command is used for routing in openlane flow.
The 20-tritonRouting.drc log file can be found at /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/runs/03-08_19-58/reports/routing/ and shows the DRC violations. They are shown below:
Magic
below is the commmand to see routinng in the magic
magic -d XR -T /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/tmp/merged.lef def read /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/results/routing/picorv32a.def&
SPEF FILE GENERATION Data from wires in a chip are represented in the ASCII format known as Standard Parasitic Exchange Format (SPEF).A programme called SPEF EXTRACTOR is part of OpenLANE and is used to create SPEF files. It is a Python-based parser that creates the SPEF file from the LEF and DEF files as input inputs.
Below is the command to invoke SPEF_EXTRACTOR
cd ../tools/SPEF_EXTRACTOR python3 main.py /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/tmp/merged.lef /home/awadhesh.chauhan/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-08_19-58/results/floorplaning/picorv32a.def
below is trhe extracted .spef file short snop;
