Alignof · Alignof · Dec 30, 2024 · Dec 26, 2024 · Dec 26, 2024 · Dec 26, 2024
diff --git a/.cargo/config.toml b/.cargo/config.toml
@@ -3,7 +3,7 @@ runner = """
 qemu-system-riscv64
 -cpu rv64,smstateen=true
 -machine virt
--bios none
+-bios default
 -nographic
 -m 2G
 -initrd vmlinux_debug
@@ -22,7 +22,6 @@ qemu-system-riscv64
 
 rustflags = [
   "-C", "link-arg=-Tmemory.x",
-  "-C", "link-arg=-Tlink.x",
   "-C", "target-feature=+h",
 ]
 

diff --git a/Cargo.toml b/Cargo.toml
@@ -22,10 +22,9 @@ embedded_host_dtb = []
 elf = { version = "0.7.2", default-features = false }
 fdt = "0.1.5"
 linked_list_allocator = "0.10.5"
-raki = "1.2.0"
+raki = "1.3.1"
 riscv = "0.11.1"
-riscv-rt = { git = "https://github.com/Alignof/riscv", branch = "fix/link_error_on_latest_rust" }
 rustsbi = { version = "0.4.0", features = ["machine"] }
 sbi-rt = "0.0.3"
-sbi-spec = { version = "0.0.7", features = [ "legacy" ] }
+sbi-spec = { version = "0.0.8", features = [ "legacy" ] }
 spin = "0.9.8"
diff --git a/guest.dtb b/guest.dtb
diff --git a/guest_image/build_dtb.sh b/guest_image/build_dtb.sh
@@ -10,7 +10,7 @@ function help() {
 function create_host() {
     $qemu_path -S -gdb tcp::10000 \
         -machine virt \
-        -bios none  \
+        -bios default \
         -m 256M \
         -initrd ../vmlinux_debug \
         -drive file=../rootfs.ext2,format=raw,id=hd0,if=none \
@@ -28,7 +28,7 @@ function create_host() {
 function create_guest() {
     $qemu_path -S -gdb tcp::10000 \
         -machine virt \
-        -bios none  \
+        -bios default \
         -m 256M \
         -initrd ../vmlinux_debug \
         -drive file=../rootfs.ext2,format=raw,id=hd0,if=none \

diff --git a/guest_image/guest.dts b/guest_image/guest.dts
@@ -90,10 +90,10 @@
 
 	chosen {
 		bootargs = "root=/dev/vda rw console=ttyS0";
-		linux,initrd-end = <0x00 0x9812b230>;
-		linux,initrd-start = <0x00 0x88000000>;
+		linux,initrd-end = <0x00 0x9832b230>;
+		linux,initrd-start = <0x00 0x88200000>;
 		stdout-path = "/soc/serial@10000000";
-		rng-seed = <0x2b05a034 0xe739bfb7 0x512d2025 0xf0ec97e8 0x69399e86 0x1f2de5a9 0xcacea4aa 0xafb54655>;
+		rng-seed = <0x9775b34d 0xe39158f2 0x3e9d10b1 0x73692dfd 0x13c15814 0xa4ad203f 0x8b0d62f7 0x6bf8a79d>;
 	};
 
 	soc {

diff --git a/guest_image/host.dts b/guest_image/host.dts
@@ -90,10 +90,10 @@
 
 	chosen {
 		bootargs = "root=/dev/vda rw console=ttyS0";
-		linux,initrd-end = <0x00 0x9812b230>;
-		linux,initrd-start = <0x00 0x88000000>;
+		linux,initrd-end = <0x00 0x9832b230>;
+		linux,initrd-start = <0x00 0x88200000>;
 		stdout-path = "/soc/serial@10000000";
-		rng-seed = <0x43b57d4e 0xc47d1e53 0xf72be401 0x8782f496 0x6b3aef66 0xccfa8bb3 0x710c4d0d 0x40c7b7c6>;
+		rng-seed = <0xb7ff67db 0xb4fa9154 0xf9f2f06c 0xed096f3b 0x953e577a 0x32c67d9 0x8272b7a5 0xb93e1980>;
 	};
 
 	soc {

diff --git a/host.dtb b/host.dtb
diff --git a/memory.x b/memory.x
@@ -1,16 +1,16 @@
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 2M
-  MACHINE_RAM (rw) : ORIGIN = 0x80200000, LENGTH = 6M
+  FLASH (rx) : ORIGIN = 0x80200000, LENGTH = 2M
+  BOOT_RAM (rw) : ORIGIN = 0x80400000, LENGTH = 6M
   RAM (rwx) : ORIGIN = 0xc1000000, LENGTH = 528M
   L2_LIM (rw) : ORIGIN = 0xe2000000, LENGTH = 8M
 }
 
 /*
- * FLASH (TEXT), 0x8000_0000..0x8020_0000
- * MACHINE_RAM , 0x8020_0000..0x8080_0000
- * RAM (DATA, BSS, HEAP), 0x8100_0000..0xa200_0000
- * L2_LIM (STACK), 0xa200_0000..0xa300_0000
+ * FLASH (TEXT), 0x8020_0000..0x8040_0000
+ * BOOT_RAM , 0x8040_0000..0x80a0_0000
+ * RAM (DATA, BSS, HEAP), 0xc100_0000..0xe200_0000
+ * L2_LIM (STACK), 0xe200_0000..0xa300_0000
  */
 
 REGION_ALIAS("REGION_TEXT", FLASH);
@@ -22,16 +22,22 @@ REGION_ALIAS("REGION_STACK", L2_LIM);
 
 _stack_start = ORIGIN(L2_LIM) + LENGTH(L2_LIM);
 _hv_heap_size = 0x20000000;
-_m_stack_size = 0x200000;
+_b_stack_size = 0x200000;
 
 /* defined section in hikami */
 SECTIONS
 {
-    .machine_stack : ALIGN(4K) {
-        _bottom_m_stack = .;
-        . += _m_stack_size;
-        _top_m_stack = .;
-    } > MACHINE_RAM
+    .text : {
+        *(.text.entry)
+        . = ALIGN(4K);
+        *(.text .text.*)
+    } > REGION_TEXT
+
+    .boot_stack : ALIGN(4K) {
+        _bottom_b_stack = .;
+        . += _b_stack_size;
+        _top_b_stack = .;
+    } > BOOT_RAM
 
     .host_dtb : ALIGN(4K)
     {

diff --git a/rust-toolchain.toml b/rust-toolchain.toml
@@ -1,4 +1,4 @@
 [toolchain]
-channel = "1.82.0"
+channel = "nightly"
 components = [ "rustfmt", "clippy" ]
 targets = [ "riscv64imac-unknown-none-elf" ]
diff --git a/src/device/iommu.rs b/src/device/iommu.rs
@@ -57,16 +57,16 @@ impl PciDevice for IoMmu {
             .next()
             .unwrap();
         assert_eq!(pci_reg.address.len(), 12); // 4 bytes * 3
-        let pci_first_reg = u32::from(pci_reg.address[0]) << 24
-            | u32::from(pci_reg.address[1]) << 16
-            | u32::from(pci_reg.address[2]) << 8
+        let pci_first_reg = (u32::from(pci_reg.address[0]) << 24)
+            | (u32::from(pci_reg.address[1]) << 16)
+            | (u32::from(pci_reg.address[2]) << 8)
             | u32::from(pci_reg.address[3]);
 
         // https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci.txt
         Some(IoMmu {
-            bus: pci_first_reg >> 16 & 0b1111_1111, // 8 bit
-            device: pci_first_reg >> 11 & 0b1_1111, // 5 bit
-            function: pci_first_reg >> 8 & 0b111,   // 3 bit
+            bus: (pci_first_reg >> 16) & 0b1111_1111, // 8 bit
+            device: (pci_first_reg >> 11) & 0b1_1111, // 5 bit
+            function: (pci_first_reg >> 8) & 0b111,   // 3 bit
         })
     }
 

diff --git a/src/device/iommu/register_map.rs b/src/device/iommu/register_map.rs
@@ -49,7 +49,7 @@ impl Capabilities {
     /// Return (major version, minor version)
     pub fn version(&self) -> (u8, u8) {
         let version_reg = self.0;
-        ((version_reg >> 4 & 0xf) as u8, (version_reg & 0xf) as u8)
+        (((version_reg >> 4) & 0xf) as u8, (version_reg & 0xf) as u8)
     }
 
     /// Is base format?
@@ -65,7 +65,7 @@ impl Capabilities {
         /// Field `Sv39x4` of `capabilities` register.
         const FIELD_CAPABILITIES_SV39X4: usize = 17;
 
-        self.0 >> FIELD_CAPABILITIES_SV39X4 & 0x1 == 1
+        (self.0 >> FIELD_CAPABILITIES_SV39X4) & 0x1 == 1
     }
 }
 
@@ -78,7 +78,7 @@ impl Cqb {
         assert!(queue_addr % 4096 == 0);
 
         // CQB.PPN = B, CQB.LOG2SZ-1 = k - 1
-        self.0 = (queue_addr.0 as u64 >> 12) << 10 | u64::from(size.ilog2() - 1);
+        self.0 = ((queue_addr.0 as u64 >> 12) << 10) | u64::from(size.ilog2() - 1);
     }
 }
 
@@ -118,7 +118,7 @@ impl Fqb {
         assert!(queue_addr % 4096 == 0);
 
         // FQB.PPN = B, FQB.LOG2SZ-1 = k - 1
-        self.0 = (queue_addr.0 as u64 >> 12) << 10 | u64::from(size.ilog2() - 1);
+        self.0 = ((queue_addr.0 as u64 >> 12) << 10) | u64::from(size.ilog2() - 1);
     }
 }
 
@@ -144,7 +144,7 @@ impl FqCsr {
         /// Field `fqon` of `fqcsr` register. (16 bit)
         const FIELD_FQCSR_FQON: usize = 0x10;
         let fqcsr = self.0;
-        fqcsr >> FIELD_FQCSR_FQON & 0x1 == 1
+        (fqcsr >> FIELD_FQCSR_FQON) & 0x1 == 1
     }
 }
 
@@ -157,7 +157,7 @@ impl Pqb {
         assert!(queue_addr % 4096 == 0);
 
         // PQB.PPN = B, PQB.LOG2SZ-1 = k - 1
-        self.0 = (queue_addr.0 as u64 >> 12) << 10 | u64::from(size.ilog2() - 1);
+        self.0 = ((queue_addr.0 as u64 >> 12) << 10) | u64::from(size.ilog2() - 1);
     }
 }
 
@@ -184,7 +184,7 @@ impl PqCsr {
         const FIELD_PQCSR_PQON: usize = 0x10;
 
         let pqcsr = self.0;
-        pqcsr >> FIELD_PQCSR_PQON & 0x1 == 1
+        (pqcsr >> FIELD_PQCSR_PQON) & 0x1 == 1
     }
 }
 
@@ -211,6 +211,6 @@ impl Ddtp {
         /// Field `ppn` of `ddtp` register. (16 bit)
         const FIELD_DDTP_PPN: usize = 10;
 
-        self.0 = (ddt_addr.0 as u64 >> 12) << FIELD_DDTP_PPN | mode as u64;
+        self.0 = ((ddt_addr.0 as u64 >> 12) << FIELD_DDTP_PPN) | mode as u64;
     }
 }
diff --git a/src/device/pci.rs b/src/device/pci.rs
@@ -50,9 +50,9 @@ impl Pci {
         reg: ConfigSpaceRegister,
     ) -> u32 {
         let config_data_reg_addr = self.base_addr.0 as u32
-            | (bus_num & 0b1111_1111) << 20
-            | (device_num & 0b1_1111) << 15
-            | (function_num & 0b111) << 12
+            | ((bus_num & 0b1111_1111) << 20)
+            | ((device_num & 0b1_1111) << 15)
+            | ((function_num & 0b111) << 12)
             | reg as u32;
 
         match reg {
@@ -80,9 +80,9 @@ impl Pci {
         data: u32,
     ) {
         let config_data_reg_addr = self.base_addr.0 as u32
-            | (bus_num & 0b1111_1111) << 20
-            | (device_num & 0b1_1111) << 15
-            | (function_num & 0b111) << 12
+            | ((bus_num & 0b1111_1111) << 20)
+            | ((device_num & 0b1_1111) << 15)
+            | ((function_num & 0b111) << 12)
             | reg as u32;
         match reg {
             ConfigSpaceRegister::VendorId
@@ -133,9 +133,9 @@ impl MmioDevice for Pci {
 
         let get_u32 = |range: &[u8], four_bytes_index: usize| {
             let index = four_bytes_index * 4;
-            u32::from(range[index]) << 24
-                | u32::from(range[index + 1]) << 16
-                | u32::from(range[index + 2]) << 8
+            (u32::from(range[index]) << 24)
+                | (u32::from(range[index + 1]) << 16)
+                | (u32::from(range[index + 2]) << 8)
                 | u32::from(range[index + 3])
         };
         let mut memory_maps = Vec::new();
@@ -145,8 +145,8 @@ impl MmioDevice for Pci {
             // ignore I/O space map
             // https://elinux.org/Device_Tree_Usage#PCI_Address_Translation
             if (bus_address >> 24) & 0b11 != 0b01 {
-                let address = (get_u32(range, 3) as usize) << 32 | get_u32(range, 4) as usize;
-                let size = (get_u32(range, 5) as usize) << 32 | get_u32(range, 6) as usize;
+                let address = ((get_u32(range, 3) as usize) << 32) | get_u32(range, 4) as usize;
+                let size = ((get_u32(range, 5) as usize) << 32) | get_u32(range, 6) as usize;
 
                 memory_maps.push(MemoryMap::new(
                     GuestPhysicalAddress(address)..GuestPhysicalAddress(address) + size,

diff --git a/src/device/uart.rs b/src/device/uart.rs
@@ -124,7 +124,7 @@ impl rustsbi::Console for Uart {
         };
         for c in byte_data {
             unsafe {
-                while (uart_lsr_ptr.read_volatile() >> 5 & 0x1) == 1 {}
+                while ((uart_lsr_ptr.read_volatile() >> 5) & 0x1) == 1 {}
                 uart_ptr.write_volatile(u32::from(*c));
             }
         }
@@ -159,7 +159,7 @@ impl rustsbi::Console for Uart {
         let uart_ptr = self.base_addr.raw() as *mut u32;
         let uart_lsr_ptr = self.lsr_addr().raw() as *mut u32;
         unsafe {
-            while (uart_lsr_ptr.read_volatile() >> 5 & 0x1) == 1 {}
+            while ((uart_lsr_ptr.read_volatile() >> 5) & 0x1) == 1 {}
             uart_ptr.write_volatile(u32::from(byte));
         }
         SbiRet::success(0)

diff --git a/src/emulate_extension.rs b/src/emulate_extension.rs
@@ -3,7 +3,7 @@
 pub mod zicfiss;
 
 use crate::h_extension::csrs::vstvec;
-use crate::trap::hypervisor_supervisor::hstrap_exit;
+use crate::trap::hstrap_exit;
 use crate::HYPERVISOR_DATA;
 
 use core::arch::asm;
@@ -52,7 +52,7 @@
 /// TODO: Remove it when `OnceCell` is replaced to `LazyCell`.
 pub fn initialize() {
    use zicfiss::{Zicfiss, ZICFISS_DATA};
    unsafe { ZICFISS_DATA.lock() }.get_or_init(Zicfiss::new);
 }

 /// Throw an VS-level exception.
@@ -60,7 +60,7 @@
 /// * `trap_value`: Trap value. (stored to vstval)
 pub fn pseudo_vs_exception(exception_num: usize, trap_value: usize) -> ! {
    unsafe {
        let hypervisor_data = HYPERVISOR_DATA.lock();
        let mut context = hypervisor_data.get().unwrap().guest().context;
        asm!(
            "csrw vsepc, {sepc}",
@@ -74,18 +74,18 @@
         let spp = sstatus::read().spp();
         let vsstatus: usize;
         asm!("csrr {status}, vsstatus", status = out(reg) vsstatus);
-        let sie = vsstatus >> 1 & 0x1;
+        let sie = (vsstatus >> 1) & 0x1;
         asm!(
             "csrw vsstatus, {status}",
-            status = in(reg) (vsstatus & !(1 << 8)) | (spp as usize) << 8
+            status = in(reg) (vsstatus & !(1 << 8)) | ((spp as usize) << 8)
         );
         // disable interrupt
         asm!(
             "csrs vsstatus, {status}",
             "csrci vsstatus, 0b10",
             status = in(reg) sie << 5,
         );
-        context.set_sstatus(context.sstatus() | 1 << 8);
+        context.set_sstatus(context.sstatus() | (1 << 8));
 
         context.set_sepc(vstvec::read().bits());
 

diff --git a/src/emulate_extension/zicfiss.rs b/src/emulate_extension/zicfiss.rs
@@ -51,8 +51,8 @@
            hpa.0 as *mut usize
        } else {
            unsafe {
                HYPERVISOR_DATA.force_unlock();
                ZICFISS_DATA.force_unlock();
            }
            pseudo_vs_exception(STORE_AMO_PAGE_FAULT, self.ssp.0 as usize);
        }
@@ -84,7 +84,7 @@
     ///
     /// Chack corresponding `SSE` bit of xenvcfg.
     fn is_ss_enable(&self, sstatus: usize) -> bool {
-        let spp = sstatus >> 8 & 0x1;
+        let spp = (sstatus >> 8) & 0x1;
         if spp == 0 {
             self.senv_sse
         } else {
@@ -97,7 +97,7 @@
    /// Emulate Zicfiss instruction.
    #[allow(clippy::cast_possible_truncation)]
    fn instruction(&mut self, inst: &Instruction) {
        let mut context = unsafe { HYPERVISOR_DATA.lock() }
            .get()
            .unwrap()
            .guest()
@@ -123,8 +123,8 @@
                    let expected_value = context.xreg(inst.rs1.unwrap()) as usize;
                    if pop_value != expected_value {
                        unsafe {
                            HYPERVISOR_DATA.force_unlock();
                            ZICFISS_DATA.force_unlock();
                        }
                        pseudo_vs_exception(SOFTWARE_CHECK_EXCEPTION, SHADOW_STACK_FAULT)
                    }
@@ -136,8 +136,8 @@
                    let expected_value = context.xreg(inst.rd.unwrap()) as usize;
                    if pop_value != expected_value {
                        unsafe {
                            HYPERVISOR_DATA.force_unlock();
                            ZICFISS_DATA.force_unlock();
                        }
                        pseudo_vs_exception(SOFTWARE_CHECK_EXCEPTION, SHADOW_STACK_FAULT)
                    }
@@ -160,7 +160,7 @@
        /// Register number of `Shadow Stack Pointer`.
        const CSR_SSP: usize = 0x11;

        let hypervisor_data = unsafe { HYPERVISOR_DATA.lock() };
        let mut context = hypervisor_data.get().unwrap().guest().context;

        let csr_num = inst.rs2.unwrap();
@@ -219,12 +219,12 @@
                     | ZicsrOpcode::CSRRWI
                     | ZicsrOpcode::CSRRSI,
                 ) => {
-                    if write_to_csr_value >> 3 & 0x1 == 1 {
+                    if (write_to_csr_value >> 3) & 0x1 == 1 {
                         self.senv_sse = true;
                     }
                 }
                 OpcodeKind::Zicsr(ZicsrOpcode::CSRRC | ZicsrOpcode::CSRRCI) => {
-                    if write_to_csr_value >> 3 & 0x1 == 1 {
+                    if (write_to_csr_value >> 3) & 0x1 == 1 {
                         self.senv_sse = false;
                     }
                 }

diff --git a/src/guest.rs b/src/guest.rs
@@ -209,7 +209,7 @@ impl Guest {
     }
 
     /// Allocate guest memory space from heap and create corresponding page table.
-    pub fn filling_memory_region(&self, region: Range<GuestPhysicalAddress>) {
+    pub fn allocate_memory_region(&self, region: Range<GuestPhysicalAddress>) {
         use PteFlag::{Accessed, Dirty, Exec, Read, User, Valid, Write};
 
         let all_pte_flags_are_set = &[Dirty, Accessed, Exec, Write, Read, User, Valid];

diff --git a/src/h_extension/csrs.rs b/src/h_extension/csrs.rs
@@ -440,7 +440,7 @@ pub mod hgatp {
 
     /// Set Hgatp fields.
     pub fn set(mode: Mode, vmid: usize, ppn: usize) {
-        write((0xF & (mode as usize)) << 60 | (0x3FFF & vmid) << 44 | 0x0FFF_FFFF_FFFF & ppn);
+        write(((0xF & (mode as usize)) << 60) | ((0x3FFF & vmid) << 44) | 0x0FFF_FFFF_FFFF & ppn);
     }
 
     impl_bits!(Hgatp);