Skip to content
View A7med3id10's full-sized avatar
πŸ’ͺ
Focusing
πŸ’ͺ
Focusing
  • Cairo University
  • Cairo, Egypt
  • 12:33 (UTC +02:00)

Block or report A7med3id10

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
A7med3id10/README.md

Pinned Loading

  1. UART_TX UART_TX Public

    UART_TX Implementation Using Verilog

    Verilog

  2. UART_RX UART_RX Public

    UART RX Implementation using Verilog

    Verilog 1

  3. Integer_Clock_Divider Integer_Clock_Divider Public

    Integer Clock Divider implementation using Verilog.

    Verilog

  4. UART_Digital_Communication_System UART_Digital_Communication_System Public

    UART Verilog Project

    Verilog