PWM max frequency getting capped in STM32F4 (96b_aerocore2)?

[gabopushups]

Hi. I'm trying to drive a motor with a STM32F427VIT6, but I can't go any faster than 8.33 kHz.
I measured this by setting a PWM with a period of 2 cycles, and an active state of 1 cycle:
ret = pwm_pin_set_cycles(pwm, PWM_CHANNEL, 2, 1, PWM_FLAGS);

I tried to measure the amount of cycles per second but it shows zero:
ret = pwm_get_cycles_per_sec(pwm,PWM_CHANNEL,maxp);

The .dts I'm using is based on the 96b Aerocore 2, and I overrode the definition of timers1 in the following way:

&timers1 {
	status = "okay";
	pwm1: pwm {
		status = "okay";
		pinctrl-0 = <&tim1_ch1_pe9
			     &tim1_ch4_pe14>;
		st,prescaler = <0>;
	};
};

And these are the settings that I use in my defconfig file, which were only modified to get a clock of 168 MHz

# Copyright (c) 2020 Linaro Limited
# SPDX-License-Identifier: Apache-2.0

CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F427XX=y
# 168MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=168000000

# Enable MPU
CONFIG_ARM_MPU=y

# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y

CONFIG_SERIAL=y

# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

# enable pinmux
CONFIG_PINMUX=y

# enable GPIO
CONFIG_GPIO=y

# clock configuration
CONFIG_CLOCK_CONTROL=y


# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=12000000

# produce 168MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=12
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1

# APB1 clock must not exceed 50MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=4
CONFIG_CLOCK_STM32_APB2_PRESCALER=2

Any ideas?

[gabopushups]

EDIT: I installed Zephyr 2.6.99 to try it, and what seems to be capped is the min period for the PWM, instead of the pulswidth itself.

I checked with

	ret = pwm_pin_set_cycles(pwm, PWM_CHANNEL, 100,
				       10, PWM1_FLAGS);

In this case, the 100 corresponds to the period in clock cycles, but again, it doesn't go any lower from 10 kHz, suggesting that the clock for the pwm is 1000 KHz. Setting it below 100 clock cycles would drive the pwm to a constant off state.
However, the pulsewidth of 10 cycles seems to be working, hitting around 300 ns, which would suggest that the clock for this pwm is around 30.33 MHz

EDIT 2: I also modified the preescaler of the APB1 (the clock that feeds the pwm). And keeping all parameters constant, the pulsewidth would increase or decrease accordingly, but the period would remain unmodified. That means, increasing the preescaler from 4 to 8 would duplicate the pulsewidth, but the period would stay at 100 microsecs minimum