From d31db8b43d3fc3cf242c0fb00d8259be17cf6357 Mon Sep 17 00:00:00 2001
From: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Date: Tue, 13 Aug 2024 13:20:31 +0700
Subject: [PATCH] s32: soc: s32z2: update QSPI clock sources

Select PERIPHPLL_DFS0 clock as QSPI0 clock source
Select PERIPHPLL_DFS2 clock as QSPI1 clock source
Update QSPI dividers so that value clocks:
 P4_QSPI0_1X_CLK is 200 MHz
 P4_QSPI0_2X_CLK is 400 MHz
 P4_QSPI1_1X_CLK is 150 MHz
 P4_QSPI1_2X_CLK is 300 MHz

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
---
 s32/soc/s32z270/src/Clock_Ip_Cfg.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/s32/soc/s32z270/src/Clock_Ip_Cfg.c b/s32/soc/s32z270/src/Clock_Ip_Cfg.c
index 7086c8a01..638a9f17e 100644
--- a/s32/soc/s32z270/src/Clock_Ip_Cfg.c
+++ b/s32/soc/s32z270/src/Clock_Ip_Cfg.c
@@ -557,7 +557,7 @@ static const Clock_Ip_SelectorConfigType Clock_Ip_SelectorConfigurations_0[CLOCK
     #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 41U
     {
         P4_QSPI0_2X_CLK,                    /* Clock name associated to selector */
-        FIRC_CLK,                    /* Name of the selected input source */
+        PERIPHPLL_DFS0_CLK,                    /* Name of the selected input source */
     },
     #endif
 
@@ -571,7 +571,7 @@ static const Clock_Ip_SelectorConfigType Clock_Ip_SelectorConfigurations_0[CLOCK
     #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 43U
     {
         P4_SDHC_CLK,                    /* Clock name associated to selector */
-        FIRC_CLK,                    /* Name of the selected input source */
+        PERIPHPLL_DFS2_CLK,                    /* Name of the selected input source */
     },
     #endif
 
@@ -1345,7 +1345,7 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I
     #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 63U
     {
         P4_QSPI0_2X_CLK,                    /* name */
-        1U,                              /* value */
+        2U,                              /* value */
         {
             0U,
         }
@@ -1555,7 +1555,7 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I
     #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 84U
     {
         P4_SDHC_CLK,                    /* name */
-        1U,                              /* value */
+        2U,                              /* value */
         {
             0U,
         }
@@ -1672,7 +1672,7 @@ static const Clock_Ip_FracDivConfigType Clock_Ip_FracDivsConfigurations_0[CLOCK_
         1U,          /* Enabled */
         {
             2U,          /* integer part */
-            18U,          /* fractional part */
+            0U,          /* fractional part */
         },
     },
     #endif