From 868c9e363cad8770850284b4e49d9e1698ab8734 Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 24 Jan 2024 15:11:39 -0800 Subject: [PATCH 01/11] Fixes for NXP T1024 with Integrity OS. Adds additional FDT fixups for FMAN, Ethernet, PCI. Add PCI init and enumeration. --- arch.mk | 1 + hal/nxp_t1024.c | 344 +++++++++++++++++++++++++++++++++++++------ include/fdt.h | 6 + include/pci.h | 41 +++++- src/boot_ppc_start.S | 2 +- src/fdt.c | 82 +++++++++++ src/pci.c | 109 +++++++++++--- 7 files changed, 518 insertions(+), 67 deletions(-) diff --git a/arch.mk b/arch.mk index c95cb7a50..a974fa3ca 100644 --- a/arch.mk +++ b/arch.mk @@ -425,6 +425,7 @@ ifeq ($(TARGET),nxp_t1024) LDFLAGS+=-Wl,--as-needed # remove weak functions not used OBJS+=src/boot_ppc_mp.o # support for spin table OBJS+=src/fdt.o + OBJS+=src/pci.o UPDATE_OBJS:=src/update_ram.o ifeq ($(SPMATH),1) MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 6a0323750..8fb8e4547 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -25,6 +25,7 @@ #include "hal.h" #include "nxp_ppc.h" #include "fdt.h" +#include "pci.h" /* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */ /* IFC: CS0 NOR, CS1 MRAM, CS2 APU CPLD, CS3, MPU CPLD */ @@ -118,8 +119,34 @@ static void hal_flash_unlock_sector(uint32_t sector); #define DCFG_DMA2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x584)) /* PCI Express LIODN base register */ -#define PCI_BASE(n) (0x240000 + ((n) * 0x10000)) -#define PCIE_LIODN(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x40)) /* PEXx_PEX_LBR */ +#define PCI_BASE(n) (CCSRBAR + 0x240000 + ((n-1) * 0x10000)) +#define PCIE_CONFIG_ADDR(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x00)) /* PEXx_PEX_CONFIG_ADDR - configuration address */ +#define PCIE_CONFIG_DATA(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x04)) /* PEXx_PEX_CONFIG_DATA - configuration data */ +#define PCIE_LIODN(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x40)) /* PEXx_PEX_LBR */ +#define PCIE_BLK_REV1(n) ((volatile uint32_t*)(PCI_BASE(n) + 0xBF8)) /* PEXx_PEX_IP_BLK_REV1 */ +#define PCIE_BLK_REV2(n) ((volatile uint32_t*)(PCI_BASE(n) + 0xBFC)) /* PEXx_PEX_IP_BLK_REV1 */ + +/* PCIe Output Windows (max 5) */ +#define PCIE_OTAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC00 + ((w) * 32))) /* PEXx_PEXOTARn - outbound translation address */ +#define PCIE_OTEAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC04 + ((w) * 32))) /* PEXx_PEXOTEARn - outbound translation extended address */ +#define PCIE_OWBAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC08 + ((w) * 32))) /* PEXx_PEXOWBARn - outbound window base address */ +#define PCIE_OWAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC10 + ((w) * 32))) /* PEXx_PEXOWARn - outbound window attributes */ +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 + +/* PCIe Input Windows (max 4 - seq is 3,2,1,0) */ +#define PCIE_ITAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD80 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXITARn - inbound translation address */ +#define PCIE_IWBAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD88 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBARn - inbound window base address */ +#define PCIE_IWBEAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD8C + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBEARn- inbound window base extended address */ +#define PCIE_IWAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD90 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWARn - inbound window attributes */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 /* Buffer Manager */ #define BMAN_LIODNR ((volatile uint32_t*)(BMAN_CCSR_BASE + 0xD08)) @@ -128,7 +155,7 @@ static void hal_flash_unlock_sector(uint32_t sector); /* Frame Queue Descriptor (FQD) */ #define FQD_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC04)) #define FQD_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC10)) -/* Packed Frame Desc riptor Record (PFDR) */ +/* Packed Frame Descriptor Record (PFDR) */ #define PFDR_BARE ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC20)) #define PFDR_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC24)) #define PFDR_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC30)) @@ -300,10 +327,13 @@ static void hal_flash_unlock_sector(uint32_t sector); /* Hardware Ports (0-63) 4KB each (256KB total) */ #define FMAN_BMI(n) ((FMAN_BASE + 0x80000) + ((n) * 0x1000)) +#define FMAN_BMI_SPLIODN(n, p) ((volatile uint32_t*)(FMAN_BMI(n) + 0x304 + ((((p) - 1) & 0x3F) * 4))) #define FMAN_QMI(n) ((FMAN_BASE + 0x80000) + ((n) * 0x1000) + 0x400) #define FMAN_DMA (FMAN_BASE + 0xC2000UL) /* FMan DMA */ +#define FMAN_DMA_ENTRIES (32) +#define FMAN_DMA_PORT_LIODN(n) ((volatile uint32_t*)(FMAN_DMA + 0x60 + (((n) & 0x1F) * 4))) /* FMan DMA portID-LIODN #0..31 register */ #define FMAN_FPM (FMAN_BASE + 0xC3000UL) /* Frame processing manager (FPM) */ @@ -1141,37 +1171,178 @@ void hal_early_init(void) } #ifdef ENABLE_PCIE + +/* PCI IO read/write functions */ +/* Intel PCI addr/data mappings for compatibility with our PCI driver */ +#define PCI_CONFIG_ADDR_PORT 0xcf8 +#define PCI_CONFIG_DATA_PORT 0xcfc +static int pcie_bus = 0; +void io_write32(uint16_t port, uint32_t value) +{ + if (port == PCI_CONFIG_ADDR_PORT) { + set32(PCIE_CONFIG_ADDR(pcie_bus), value); + } + else if (port == PCI_CONFIG_DATA_PORT) { + set32(PCIE_CONFIG_DATA(pcie_bus), value); + } +} +uint32_t io_read32(uint16_t port) +{ + uint32_t value = 0; + if (port == PCI_CONFIG_ADDR_PORT) { + value = get32(PCIE_CONFIG_ADDR(1)); + } + else if (port == PCI_CONFIG_DATA_PORT) { + value = get32(PCIE_CONFIG_DATA(1)); + } + return value; +} + +#define PCI_MMIO32_LENGTH (1024UL * 1024U * 1024U) +#define PCI_MMIO32_PREFETCH_LENGTH (1024UL * 1024U * 1024U) + #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x00000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_IO_PHYS_HIGH 0xF -#define CONFIG_SYS_PCIE1_IO_PHYS 0xF8000000 -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_PHYS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x00000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_IO_PHYS_HIGH 0xF +#define CONFIG_SYS_PCIE1_IO_PHYS 0xF8000000 +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_PHYS #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x10000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x10000000 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 #define CONFIG_SYS_PCIE2_IO_PHYS_HIGHT 0xF -#define CONFIG_SYS_PCIE2_IO_PHYS 0xF8010000 -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_PHYS +#define CONFIG_SYS_PCIE2_IO_PHYS 0xF8010000 +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_PHYS #define CONFIG_SYS_PCIE3_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x20000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xA0000000 -#define CONFIG_SYS_PCIE3_IO_PHYS_HIGH 0xF -#define CONFIG_SYS_PCIE3_IO_PHYS 0xF8020000 -#define CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE3_IO_PHYS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x20000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xA0000000 +#define CONFIG_SYS_PCIE3_IO_PHYS_HIGH 0xF +#define CONFIG_SYS_PCIE3_IO_PHYS 0xF8020000 +#define CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE3_IO_PHYS + static int hal_pcie_init(void) { - /* Map TLB for PCIe */ - set_tlb(1, 3, CONFIG_SYS_PCIE1_MEM_VIRT, - CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, - CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + int ret; + int bus, i; + int law_start = 14; + struct pci_enum_info enum_info; + + for (pcie_bus=1; pcie_bus<=3; pcie_bus++) { + /* Check device disable register */ + if (get32(DCFG_DEVDISR3) & (1 << (32-pcie_bus))) { + wolfBoot_printf("PCIe %d: Disabled\n", pcie_bus); + continue; + } - return 0; + /* Read block revision */ + wolfBoot_printf("PCIe %d: Base 0x%x, Rev 0x%x\n", + pcie_bus, PCI_BASE(pcie_bus), + get32(PCIE_BLK_REV1(pcie_bus))); + + /* Setup PCIe memory regions */ + memset(&enum_info, 0, sizeof(enum_info)); + if (pcie_bus == 1) { + enum_info.mem = CONFIG_SYS_PCIE1_MEM_VIRT; + enum_info.io = CONFIG_SYS_PCIE1_IO_VIRT; + + /* Map TLB for PCIe */ + set_tlb(1, law_start++, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); + set_tlb(1, law_start++, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + } + else if (pcie_bus == 2) { + enum_info.mem = CONFIG_SYS_PCIE2_MEM_VIRT; + enum_info.io = CONFIG_SYS_PCIE2_IO_VIRT; + + /* Map TLB for PCIe */ + set_tlb(1, law_start++, CONFIG_SYS_PCIE2_MEM_VIRT, + CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); + set_tlb(1, law_start++, CONFIG_SYS_PCIE2_MEM_VIRT, + CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + } + else if (pcie_bus == 3) { + enum_info.mem = CONFIG_SYS_PCIE3_MEM_VIRT; + enum_info.io = CONFIG_SYS_PCIE3_IO_VIRT; + + /* Map TLB for PCIe */ + set_tlb(1, law_start++, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); + set_tlb(1, law_start++, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + } + enum_info.mem_limit = enum_info.mem + (PCI_MMIO32_LENGTH - 1); + enum_info.mem_pf = (enum_info.mem + PCI_MMIO32_PREFETCH_LENGTH); + enum_info.mem_pf_limit = PCI_MMIO32_PREFETCH_LENGTH; + + /* Setup PCIe Output Windows */ + if (pcie_bus == 1) { + set32( PCIE_OTAR(pcie_bus, 0), 0x0); + set32(PCIE_OTEAR(pcie_bus, 0), 0x0); + set32( PCIE_OWAR(pcie_bus, 0), 0x80044027); + + set32( PCIE_OTAR(pcie_bus, 1), 0xE0000); + set32(PCIE_OTEAR(pcie_bus, 1), 0x0); + set32(PCIE_OWBAR(pcie_bus, 1), 0xC00000); /* MEM_PHYS >> 12 */ + set32( PCIE_OWAR(pcie_bus, 1), 0x8004401B); + + set32( PCIE_OTAR(pcie_bus, 2), 0x0); + set32(PCIE_OTEAR(pcie_bus, 2), 0x0); + set32(PCIE_OWBAR(pcie_bus, 2), 0xFF8000); /* IO_PHYS >> 12 */ + set32( PCIE_OWAR(pcie_bus, 2), 0x8008800F); + + } + else if (pcie_bus == 3) { + set32( PCIE_OTAR(pcie_bus, 0), 0x0); + set32(PCIE_OWBAR(pcie_bus, 0), 0x0); + set32( PCIE_OWAR(pcie_bus, 0), 0x80044027); + + set32( PCIE_OTAR(pcie_bus, 1), 0xE0000); + set32(PCIE_OTEAR(pcie_bus, 1), 0x0); + set32(PCIE_OWBAR(pcie_bus, 1), 0xC20000); /* MEM_PHYS >> 12 */ + set32( PCIE_OWAR(pcie_bus, 1), 0x8004401B); + + set32( PCIE_OTAR(pcie_bus, 2), 0x0); + set32(PCIE_OTEAR(pcie_bus, 2), 0x0); + set32(PCIE_OWBAR(pcie_bus, 2), 0xFF8020); /* IO_PHYS >> 12 */ + set32( PCIE_OWAR(pcie_bus, 2), 0x8008800F); + } + + /* Setup PCIe Input Windows */ + set32( PCIE_ITAR(pcie_bus, 0), 0xFFE000); + set32( PCIE_IWAR(pcie_bus, 0), 0x80E44017); + + set32( PCIE_ITAR(pcie_bus, 1), 0x0); + set32( PCIE_IWBAR(pcie_bus, 1), 0x0); + set32( PCIE_IWAR(pcie_bus, 1), 0xA0F5501E); + + set32( PCIE_ITAR(pcie_bus, 2), 0x0); + set32( PCIE_IWBAR(pcie_bus, 2), 0x1000000); + set32(PCIE_IWBEAR(pcie_bus, 2), 0x0); + set32( PCIE_IWAR(pcie_bus, 2), 0xA0F5501E); + + set32( PCIE_ITAR(pcie_bus, 3), 0x0); + set32( PCIE_IWBAR(pcie_bus, 3), 0x0); + set32(PCIE_IWBEAR(pcie_bus, 3), 0x0); + set32( PCIE_IWAR(pcie_bus, 3), 0x20F44027); + + /* TODO: setup PCSRBAR/PEXCSRBAR */ + + + ret = pci_enum_bus(0, &enum_info); + if (ret != 0) { + wolfBoot_printf("PCIe %d: Enum failed %d\n", pcie_bus, ret); + } + } + return ret; } #endif @@ -1368,23 +1539,27 @@ static const struct liodn_id_table liodn_tbl[] = { SET_LIODN("fsl,qe", 559, DCFG_QELIODNR), SET_LIODN("fsl,elo3-dma", 147, DCFG_DMA1LIODNR), SET_LIODN("fsl,elo3-dma", 227, DCFG_DMA2LIODNR), - + SET_LIODN("fsl,fman-port-1g-rx", 0x425, NULL), + SET_LIODN("fsl,fman-port-1g-rx", 0x426, NULL), + SET_LIODN("fsl,fman-port-1g-rx", 0x427, NULL), + SET_LIODN("fsl,fman-port-1g-rx", 0x428, NULL), SET_LIODN("fsl,qman", 62, QMAN_LIODNR), SET_LIODN("fsl,bman", 63, BMAN_LIODNR), - SET_LIODN("fsl,qoriq-pcie-v2.4", 148, PCIE_LIODN(1)), - SET_LIODN("fsl,qoriq-pcie-v2.4", 228, PCIE_LIODN(2)), - SET_LIODN("fsl,qoriq-pcie-v2.4", 308, PCIE_LIODN(3)), + SET_LIODN("fsl,qoriq-pcie", 148, PCIE_LIODN(1)), + SET_LIODN("fsl,qoriq-pcie", 228, PCIE_LIODN(2)), + SET_LIODN("fsl,qoriq-pcie", 308, PCIE_LIODN(3)), }; - /* Logical I/O Device Number */ void hal_liodn_init(void) { int i; for (i=0; i<(int)(sizeof(liodn_tbl)/sizeof(struct liodn_id_table)); i++) { - wolfBoot_printf("LIODN %s: %p=%d\n", - liodn_tbl[i].compat, liodn_tbl[i].reg_offset, liodn_tbl[i].id); - set32(liodn_tbl[i].reg_offset, liodn_tbl[i].id); + if (liodn_tbl[i].reg_offset != NULL) { + wolfBoot_printf("LIODN %s: %p=%d\n", + liodn_tbl[i].compat, liodn_tbl[i].reg_offset, liodn_tbl[i].id); + set32(liodn_tbl[i].reg_offset, liodn_tbl[i].id); + } } } @@ -1609,9 +1784,11 @@ static int fman_upload_firmware(const struct qe_firmware *firmware) return 0; } +#define FMAN_DMA_LIODN 973 + static int hal_fman_init(void) { - int ret; + int ret, i; const struct qe_firmware* fw = (const struct qe_firmware*)FMAN_FW_ADDR; /* Upload microcode to IRAM */ @@ -1620,7 +1797,17 @@ static int hal_fman_init(void) ret = fman_upload_firmware(fw); } if (ret == 0) { - + /* Setup FMAN LIDON */ + set32(FMAN_BMI_SPLIODN(0, 0+8), 88); /* RX_10G_TYPE2 */ + set32(FMAN_BMI_SPLIODN(0, 1+8), 89); /* RX_1G */ + set32(FMAN_BMI_SPLIODN(0, 2+8), 90); /* RX_1G */ + set32(FMAN_BMI_SPLIODN(0, 3+8), 91); /* RX_1G */ + + /* Setup FMAN DMA LIODN - use same base for all */ + for (i=0; itotalsize += 1024; /* expand by 1KB */ - wolfBoot_printf("FDT: Expanded (1KB) to %d bytes\n", fdt->totalsize); + fdt->totalsize += 2048; /* expand by 2KB */ + wolfBoot_printf("FDT: Expanded (2KB) to %d bytes\n", fdt->totalsize); /* fixup the memory region - single bank */ off = fdt_find_devtype(fdt, -1, "memory"); @@ -2027,18 +2220,24 @@ int hal_dts_fixup(void* dts_addr) } /* fixup the LIODN */ + prev_compat = NULL; for (i=0; i<(int)(sizeof(liodn_tbl)/sizeof(struct liodn_id_table)); i++) { - off = fdt_node_offset_by_compatible(fdt, -1, liodn_tbl[i].compat); + if (prev_compat == NULL || strcmp(prev_compat, liodn_tbl[i].compat) != 0) { + off = -1; + } + off = fdt_node_offset_by_compatible(fdt, off, liodn_tbl[i].compat); if (off >= 0) { fdt_fixup_val(fdt, off, liodn_tbl[i].compat, "fsl,liodn", liodn_tbl[i].id); } + prev_compat = liodn_tbl[i].compat; } /* fixup the QMAN portals */ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { uint32_t liodns[2]; + int childoff; reg = (uint32_t*)fdt_getprop(fdt, off, "cell-index", NULL); if (reg == NULL) @@ -2054,13 +2253,72 @@ int hal_dts_fixup(void* dts_addr) "qman-portal", i, off, "fsl,liodn", liodns[0], liodns[1]); fdt_setprop(fdt, off, "fsl,liodn", liodns, sizeof(liodns)); + /* Add fman@0 node and fsl,liodon = FMAN_DMA_LIODN + index */ + childoff = fdt_add_subnode(fdt, off, "fman@0"); + if (childoff > 0) { + liodns[0] = FMAN_DMA_LIODN + i + 1; + wolfBoot_printf("FDT: Set %s@%d/%s (%d), %s=%d\n", + "qman-portal", i, "fman@0", childoff, "fsl,liodn", liodns[0]); + fdt_setprop(fdt, childoff, "fsl,liodn", liodns, sizeof(liodns[0])); + off = childoff; + } + off = fdt_node_offset_by_compatible(fdt, off, "fsl,qman-portal"); } - /* mpic clock */ - off = fdt_find_devtype(fdt, -1, "open-pic"); - if (off != -FDT_ERR_NOTFOUND) { - fdt_fixup_val(fdt, off, "open-pic", "clock-frequency", hal_get_bus_clk()); + /* fixup the fman clock */ + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,fman"); + if (off != !FDT_ERR_NOTFOUND) { + fdt_fixup_val(fdt, off, "fman@", "clock-frequency", hal_get_bus_clk()); + } + + /* Ethernet Devices */ + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,fman-memac"); + while (off != -FDT_ERR_NOTFOUND) { + reg = (uint32_t*)fdt_getprop(fdt, off, "cell-index", NULL); + if (reg == NULL) + break; + i = (int)fdt32_to_cpu(*reg); + + wolfBoot_printf("FDT: Ethernet%d: Offset %d\n", i, off); + + /* Set Ethernet MAC addresses (incrementing) */ + wolfBoot_printf("FDT: Set %s@%d (%d), %s=%x:%x:%x:%x:%x:%x\n", + "ethernet", i, off, "local-mac-address", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5]); + fdt_setprop(fdt, off, "local-mac-address", mac_addr, sizeof(mac_addr)); + + mac_addr[5]++; + off = fdt_node_offset_by_compatible(fdt, off, "fsl,fman-memac"); + } + + /* PCIe Ranges */ + i = 0; + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,qoriq-pcie"); + while (off != -FDT_ERR_NOTFOUND) { + uint32_t dma_ranges[] = { + /* TYPE BUS START PHYS SIZE */ + (FDT_PCI_MEM32), + 0x00, 0xff000000, 0x0f, 0xfe000000, 0x00, 0x01000000, + (FDT_PCI_PREFETCH | FDT_PCI_MEM32), + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80000000, + (FDT_PCI_PREFETCH | FDT_PCI_MEM32), + 0x10, 0x00, 0x00, 0x00, 0x00, 0x80000000 + }; + uint32_t bus_range[2]; + bus_range[0] = 0; + bus_range[1] = i; + + wolfBoot_printf("FDT: PCI%d: Offset %d\n", i, off); + + /* Set "dma-ranges" */ + fdt_setprop(fdt, off, "dma-ranges", dma_ranges, sizeof(dma_ranges)); + /* Set "bus-range" */ + fdt_setprop(fdt, off, "bus-range", bus_range, sizeof(bus_range)); + + i++; + off = fdt_node_offset_by_compatible(fdt, off, "fsl,qoriq-pcie"); } #endif /* !BUILD_LOADER_STAGE1 */ return 0; diff --git a/include/fdt.h b/include/fdt.h index 12a50774c..60d804eb5 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -91,7 +91,12 @@ struct fdt_property { #define FDT_ERR_NOSPACE 7 #define FDT_ERR_TRUNCATED 8 #define FDT_ERR_INTERNAL 9 +#define FDT_ERR_EXISTS 10 +#define FDT_PCI_PREFETCH (0x40000000) +#define FDT_PCI_MEM32 (0x02000000) +#define FDT_PCI_IO (0x01000000) +#define FDT_PCI_MEM64 (0x03000000) uint32_t cpu_to_fdt32(uint32_t x); uint64_t cpu_to_fdt64(uint64_t x); @@ -137,6 +142,7 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, in int fdt_find_devtype(void* fdt, int startoff, const char* node); int fdt_node_check_compatible(const void *fdt, int nodeoffset, const char *compatible); int fdt_node_offset_by_compatible(const void *fdt, int startoffset, const char *compatible); +int fdt_add_subnode(void* fdt, int parentoff, const char* name); /* helpers to fix/append a property to a node */ int fdt_fixup_str(void* fdt, int off, const char* node, const char* name, const char* str); diff --git a/include/pci.h b/include/pci.h index 14e22746a..9ad571e13 100644 --- a/include/pci.h +++ b/include/pci.h @@ -31,7 +31,7 @@ #define PCI_HEADER_TYPE_OFFSET 0x0E #define PCI_BAR0_OFFSET (0x10) #define PCI_BAR5_OFFSET 0x24 -#define PCI_BAR5_MASK (~0x3) +#define PCI_BAR_MASK (~0x3) #define PCI_INTR_OFFSET 0x3C #define PCI_HEADER_TYPE_MULTIFUNC_MASK 0x80 #define PCI_HEADER_TYPE_TYPE_MASK 0x7F @@ -50,7 +50,8 @@ #define PCI_MMIO_LIMIT_OFF 0x22 #define PCI_IO_BASE_OFF 0x30 #define PCI_IO_LIMIT_OFF 0x32 - +#define PCI_PWR_MGMT_CTRL_STATUS 0x84 +#define PCI_POWER_STATE_MASK 0x3 /* Shifts & masks for CONFIG_ADDRESS register */ #define PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT 31 #define PCI_CONFIG_ADDRESS_BUS_SHIFT 16 @@ -70,9 +71,33 @@ #define PCI_COMMAND_MEM_SPACE (1 << 1) #define PCI_COMMAND_IO_SPACE (1 << 0) +typedef struct { + int bus; + int device; + int function; + uint32_t device_id; +} pci_ctrlr_info_t; + +struct pci_enum_info { + uint32_t mem; + uint32_t mem_limit; + uint32_t io; + uint32_t mem_pf; + uint32_t mem_pf_limit; + uint8_t curr_bus_number; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef PCH_HAS_PCR uint32_t pch_read32(uint8_t port_id, uint16_t offset); void pch_write32(uint8_t port_id, uint16_t offset, uint32_t val); +#endif + uint32_t pci_config_read32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off); void pci_config_write32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off, uint32_t value); @@ -82,5 +107,15 @@ void pci_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off, uint8_t pci_config_read8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off); void pci_config_write8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off, uint8_t value); -int pci_enum_do(); +uint64_t pci_get_mmio_addr(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t bar); + +uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info); + +int pci_enum_do(void); +int pci_pre_enum(void); + +#ifdef __cplusplus +} +#endif + #endif /* PCI_H */ diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 3ce577cc9..8211a0aa3 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -544,7 +544,7 @@ init_sram_law: isync init_sram_tlb: - /* Inital SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT */ + /* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT */ set_tlb(1, 9, INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, diff --git a/src/fdt.c b/src/fdt.c index ae5b7f5cc..17da097db 100644 --- a/src/fdt.c +++ b/src/fdt.c @@ -364,6 +364,41 @@ static int fdt_add_property_(void *fdt, int nodeoffset, const char *name, return 0; } +/* return: 0=no match, 1=matched */ +static int fdt_nodename_eq_(const void *fdt, int offset, const char *s, + int len) +{ + const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1); + if (p == NULL || memcmp(p, s, len) != 0) { + return 0; + } + if (p[len] == '\0') { + return 1; + } else if (!memchr(s, '@', len) && (p[len] == '@')) { + return 1; + } + return 0; +} + +static int fdt_subnode_offset_namelen(const void *fdt, int offset, + const char *name, int namelen) +{ + int depth; + for (depth = 0; + (offset >= 0) && (depth >= 0); + offset = fdt_next_node(fdt, offset, &depth)) + { + if ((depth == 1) && fdt_nodename_eq_(fdt, offset, name, namelen)) { + return offset; + } + } + if (depth < 0) { + return -FDT_ERR_NOTFOUND; + } + return offset; /* error */ +} + + /* Public Functions */ int fdt_check_header(const void *fdt) @@ -514,6 +549,10 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, memcpy(prop_data, val, len); } } + if (err != 0) { + wolfBoot_printf("FDT: Set prop failed! %d (name %d, off %d)\n", + err, name, nodeoffset); + } return err; } @@ -581,6 +620,49 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset, return offset; } +int fdt_add_subnode(void* fdt, int parentoff, const char *name) +{ + int err; + struct fdt_node_header *nh; + int offset, nextoffset; + int nodelen; + uint32_t tag, *endtag; + int namelen = (int)strlen(name); + + err = fdt_check_header(fdt); + if (err != 0) + return err; + + offset = fdt_subnode_offset_namelen(fdt, parentoff, name, namelen); + if (offset >= 0) + return -FDT_ERR_EXISTS; + else if (offset != -FDT_ERR_NOTFOUND) + return offset; + + /* Find the node after properties */ + /* skip the first node (BEGIN_NODE) */ + fdt_next_tag(fdt, parentoff, &nextoffset); + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + } while ((tag == FDT_PROP) || (tag == FDT_NOP)); + + nh = (struct fdt_node_header*)fdt_offset_ptr_(fdt, offset); + nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; + + err = fdt_splice_struct_(fdt, nh, 0, nodelen); + if (err == 0) { + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memset(nh->name, 0, FDT_TAGALIGN(namelen+1)); + memcpy(nh->name, name, namelen); + endtag = (uint32_t*)((char *)nh + nodelen - FDT_TAGSIZE); + *endtag = cpu_to_fdt32(FDT_END_NODE); + err = offset; + } + return err; +} + + /* adjust the actual total size in the FDT header */ int fdt_shrink(void* fdt) { diff --git a/src/pci.c b/src/pci.c index 3dff773c7..3f9f275f7 100644 --- a/src/pci.c +++ b/src/pci.c @@ -77,17 +77,14 @@ #define PCI_ENUM_MM_BAR_MASK ~(0xf) #define PCI_ENUM_IO_BAR_MASK ~(0x3) +#define CAPID0_A_0_0_0_PCI (0xE4) +#define DEVICE_ENABLE (0x54) +#define DTT_DEVICE_DISABLE (1 << 15) #define ONE_MB (1024 * 1024) #define FOUR_KB (4 * 1024) -struct pci_enum_info { - uint32_t mem; - uint32_t mem_limit; - uint32_t io; - uint32_t mem_pf; - uint32_t mem_pf_limit; - uint8_t curr_bus_number; -}; +static int pci_enum_is_64bit(uint32_t value); +static int pci_enum_is_mmio(uint32_t value); static inline uint32_t align_up(uint32_t address, uint32_t alignment) { return (address + alignment - 1) & ~(alignment - 1); @@ -202,7 +199,7 @@ static void pci_ecam_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, #define PCI_IO_CONFIG_ADDR(bus, dev, fn, off) \ (uint32_t)( \ - (1UL << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ + (1 << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ (bus << PCI_CONFIG_ADDRESS_BUS_SHIFT) | \ (dev << PCI_CONFIG_ADDRESS_DEVICE_SHIFT) | \ (fn << PCI_CONFIG_ADDRESS_FUNCTION_SHIFT) | \ @@ -340,6 +337,36 @@ uint8_t pci_config_read8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off) return (reg >> shift); } +uint64_t pci_get_mmio_addr(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t bar) +{ + uint32_t reg; + uint64_t addr = 0; + + if (bar >= PCI_ENUM_MAX_BARS) + { + return addr; + } + + reg = pci_config_read32(bus, dev, fun, PCI_BAR0_OFFSET + (bar * 8)); + wolfBoot_printf("BAR%d[0x%x] reg value = 0x%x\r\n", bar, PCI_BAR0_OFFSET + (bar * 8), reg); + + if (!pci_enum_is_mmio(reg)) + { + return addr; + } + + addr = reg & 0xFFFFFFF0; + + if (pci_enum_is_64bit(reg)) + { + reg = pci_config_read32(bus, dev, fun, (PCI_BAR0_OFFSET + 4) + (bar * 8)); + wolfBoot_printf("BAR%d_HIGH[0x%x] reg value = 0x%x\r\n", bar, (PCI_BAR0_OFFSET + 4) + (bar * 8), reg); + addr |= ((uint64_t)reg << 32); + } + + return addr; +} + static int pci_enum_is_64bit(uint32_t value) { uint8_t type = (value & PCI_ENUM_TYPE_MASK) >> PCI_ENUM_TYPE_SHIFT; @@ -380,7 +407,8 @@ static int pci_pre_enum_cb(uint8_t bus, uint8_t dev, uint8_t fun) #ifdef WOLFBOOT_TGL if (bus != 0) return 0; - if (dev == 0x1e) { + /* don't change UART mapping */ + if (dev == 0x1e && (fun == 0 || fun == 1)) { return 1; } /* PMC BARs shouldn't be programmed as per FSP integration guide */ @@ -420,6 +448,7 @@ static int pci_program_bar(uint8_t bus, uint8_t dev, uint8_t fun, return -1; is_prefetch = 0; + (void)is_prefetch; bar_off = PCI_BAR0_OFFSET + bar_idx * 4; orig_bar = pci_config_read32(bus, dev, fun, bar_off); pci_config_write32(bus, dev, fun, bar_off, 0xffffffff); @@ -498,6 +527,7 @@ static int pci_program_bar(uint8_t bus, uint8_t dev, uint8_t fun, return ret; } +#if defined(DEBUG_PCI) static void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun) { uint16_t vid, did; @@ -505,9 +535,17 @@ static void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun) vid = pci_config_read16(bus, dev, fun, PCI_VENDOR_ID_OFFSET); did = pci_config_read16(bus, dev, fun, PCI_DEVICE_ID_OFFSET); - PCI_DEBUG_PRINTF("PCI enum: dev: %x:%x.%x vid: %x did: %x\r\n", + PCI_DEBUG_PRINTF("\r\n\r\nPCI: %x:%x.%x %x:%x\r\n", bus, dev, fun, (int)vid, (int)did); } +#else +static inline void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun) +{ + (void)bus; + (void)dev; + (void)fun; +}; +#endif static int pci_program_bars(uint8_t bus, uint8_t dev, uint8_t fun, struct pci_enum_info *info) @@ -535,8 +573,6 @@ static int pci_program_bars(uint8_t bus, uint8_t dev, uint8_t fun, return 0; } -static uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info); - #ifdef DEBUG_PCI static void pci_dump_bridge(uint8_t bus, uint8_t dev, uint8_t fun) { @@ -579,12 +615,12 @@ static int pci_program_bridge(uint8_t bus, uint8_t dev, uint8_t fun, uint32_t orig_cmd; int ret; - PCI_DEBUG_PRINTF("bridge: %x.%x.%x\r\n", - (int)bus, (int)dev, (int)fun); orig_cmd = pci_config_read16(bus, dev, fun, PCI_COMMAND_OFFSET); pci_config_write16(bus, dev, fun, PCI_COMMAND_OFFSET, 0); info->curr_bus_number++; + PCI_DEBUG_PRINTF("Bridge: %x.%x.%x (using bus number: %d)\r\n", + (int)bus, (int)dev, (int)fun, info->curr_bus_number); pci_config_write8(bus, dev, fun, PCI_PRIMARY_BUS, bus); pci_config_write8(bus, dev, fun, PCI_SECONDARY_BUS, info->curr_bus_number); @@ -691,27 +727,33 @@ static int pci_program_bridge(uint8_t bus, uint8_t dev, uint8_t fun, return -1; } -static uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info) +uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info) { uint16_t vendor_id, device_id, header_type; uint32_t vd_code, reg; uint32_t dev, fun; int ret; + PCI_DEBUG_PRINTF("enumerating bus %d\r\n", bus); + for (dev = 0; dev < PCI_ENUM_MAX_DEV; dev++) { - vd_code = pci_config_read32(bus, dev, 0, 0x0); + vd_code = pci_config_read32(bus, dev, 0, PCI_VENDOR_ID_OFFSET); if (vd_code == 0xFFFFFFFF) { + PCI_DEBUG_PRINTF("Skipping %x:%x\r\n", bus, dev); /* No device here. */ continue; } for (fun = 0; fun < PCI_ENUM_MAX_FUN; fun++) { - if (pci_pre_enum_cb(bus, dev, fun)) + if (pci_pre_enum_cb(bus, dev, fun)) { + PCI_DEBUG_PRINTF("skipping fun %x:%x.%x\r\n", bus, dev, fun); continue; + } vd_code = pci_config_read32(bus, dev, fun, PCI_VENDOR_ID_OFFSET); if (vd_code == 0xFFFFFFFF) { + PCI_DEBUG_PRINTF("Skipping %x:%x.%x\r\n", bus, dev, fun); /* No device here, try next function*/ continue; } @@ -725,8 +767,10 @@ static uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info) pci_program_bridge(bus, dev, fun, info); } /* just one function */ - if (!(header_type & PCI_HEADER_TYPE_MULTIFUNC_MASK)) + if ((fun == 0) && !(header_type & PCI_HEADER_TYPE_MULTIFUNC_MASK)) { + PCI_DEBUG_PRINTF("one function only device\r\n"); break; + } } } @@ -734,7 +778,26 @@ static uint32_t pci_enum_bus(uint8_t bus, struct pci_enum_info *info) return 0; } -int pci_enum_do() +int pci_pre_enum(void) +{ + uint32_t reg; + + reg = pci_config_read32(0, 0, 0, CAPID0_A_0_0_0_PCI); + wolfBoot_printf("cap a %d\r\n", reg); + wolfBoot_printf("ddt disabled %d\r\n", reg & DTT_DEVICE_DISABLE); + reg &= ~(DTT_DEVICE_DISABLE); + pci_config_write32(0, 0, 0, CAPID0_A_0_0_0_PCI, reg); + reg = pci_config_read32(0, 0, 0, DEVICE_ENABLE); + wolfBoot_printf("device enable: %d\r\n", reg); + reg |= (1 << 7); + pci_config_write32(0, 0, 0, DEVICE_ENABLE, reg); + reg = pci_config_read32(0, 0, 0, DEVICE_ENABLE); + wolfBoot_printf("device enable: %d\r\n", reg); + + return 0; +} + +int pci_enum_do(void) { struct pci_enum_info enum_info; int ret; @@ -747,6 +810,12 @@ int pci_enum_do() enum_info.io = PCI_IO32_BASE; enum_info.curr_bus_number = 0; + ret = pci_pre_enum(); + if (ret != 0) { + wolfBoot_printf("pci_pre_enum error: %d\r\n", ret); + return ret; + } + ret = pci_enum_bus(0, &enum_info); PCI_DEBUG_PRINTF("PCI Memory Mapped I/O range [0x%x,0x%x] (0x%x)\r\n", From c6d961ed28ffaa6dd20773525cae25bdd870c762 Mon Sep 17 00:00:00 2001 From: David Garske Date: Fri, 26 Jan 2024 12:08:23 -0800 Subject: [PATCH 02/11] Improve PCIe code. --- hal/nxp_p1021.c | 8 +- hal/nxp_t1024.c | 339 ++++++++++++++++++++++++++++-------------------- include/fdt.h | 1 + src/fdt.c | 30 ++++- src/pci.c | 49 +++---- 5 files changed, 261 insertions(+), 166 deletions(-) diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index 63e04b503..ee69cc31a 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -975,10 +975,10 @@ void hal_early_init(void) static int hal_pcie_init(void) { /* Map LAW for PCIe */ - set_law(0, 0, CONFIG_SYS_PCIE1_MEM_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_512MB, 1), - set_law(1, 0, CONFIG_SYS_PCIE1_IO_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_64KB, 1), - set_law(2, 0, CONFIG_SYS_PCIE2_MEM_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_512MB, 1), - set_law(3, 0, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB, 1), + set_law(0, 0, CONFIG_SYS_PCIE1_MEM_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_512MB, 1); + set_law(1, 0, CONFIG_SYS_PCIE1_IO_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_64KB, 1); + set_law(2, 0, CONFIG_SYS_PCIE2_MEM_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_512MB, 1); + set_law(3, 0, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB, 1); /* Map TLB for PCIe */ set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0, diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 8fb8e4547..544ce553f 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -119,18 +119,19 @@ static void hal_flash_unlock_sector(uint32_t sector); #define DCFG_DMA2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x584)) /* PCI Express LIODN base register */ -#define PCI_BASE(n) (CCSRBAR + 0x240000 + ((n-1) * 0x10000)) -#define PCIE_CONFIG_ADDR(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x00)) /* PEXx_PEX_CONFIG_ADDR - configuration address */ -#define PCIE_CONFIG_DATA(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x04)) /* PEXx_PEX_CONFIG_DATA - configuration data */ -#define PCIE_LIODN(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x40)) /* PEXx_PEX_LBR */ -#define PCIE_BLK_REV1(n) ((volatile uint32_t*)(PCI_BASE(n) + 0xBF8)) /* PEXx_PEX_IP_BLK_REV1 */ -#define PCIE_BLK_REV2(n) ((volatile uint32_t*)(PCI_BASE(n) + 0xBFC)) /* PEXx_PEX_IP_BLK_REV1 */ +#define PCIE_MAX_CONTROLLERS 3 +#define PCIE_BASE(n) (CCSRBAR + 0x240000 + ((n-1) * 0x10000)) +#define PCIE_CONFIG_ADDR(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x00)) /* PEXx_PEX_CONFIG_ADDR - configuration address */ +#define PCIE_CONFIG_DATA(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x04)) /* PEXx_PEX_CONFIG_DATA - configuration data */ +#define PCIE_LIODN(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0x40)) /* PEXx_PEX_LBR */ +#define PCIE_BLK_REV1(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0xBF8)) /* PEXx_PEX_IP_BLK_REV1 */ +#define PCIE_BLK_REV2(n) ((volatile uint32_t*)(PCIE_BASE(n) + 0xBFC)) /* PEXx_PEX_IP_BLK_REV1 */ /* PCIe Output Windows (max 5) */ -#define PCIE_OTAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC00 + ((w) * 32))) /* PEXx_PEXOTARn - outbound translation address */ -#define PCIE_OTEAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC04 + ((w) * 32))) /* PEXx_PEXOTEARn - outbound translation extended address */ -#define PCIE_OWBAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC08 + ((w) * 32))) /* PEXx_PEXOWBARn - outbound window base address */ -#define PCIE_OWAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xC10 + ((w) * 32))) /* PEXx_PEXOWARn - outbound window attributes */ +#define PCIE_OTAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC00 + ((w) * 32))) /* PEXx_PEXOTARn - outbound translation address */ +#define PCIE_OTEAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC04 + ((w) * 32))) /* PEXx_PEXOTEARn - outbound translation extended address */ +#define PCIE_OWBAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC08 + ((w) * 32))) /* PEXx_PEXOWBARn - outbound window base address */ +#define PCIE_OWAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xC10 + ((w) * 32))) /* PEXx_PEXOWARn - outbound window attributes */ #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 #define POWAR_MEM_READ 0x00040000 @@ -138,14 +139,21 @@ static void hal_flash_unlock_sector(uint32_t sector); #define POWAR_MEM_WRITE 0x00004000 /* PCIe Input Windows (max 4 - seq is 3,2,1,0) */ -#define PCIE_ITAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD80 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXITARn - inbound translation address */ -#define PCIE_IWBAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD88 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBARn - inbound window base address */ -#define PCIE_IWBEAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD8C + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBEARn- inbound window base extended address */ -#define PCIE_IWAR(n, w) ((volatile uint32_t*)(PCI_BASE(n) + 0xD90 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWARn - inbound window attributes */ +#define PCIE_ITAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD80 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXITARn - inbound translation address */ +#define PCIE_IWBAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD88 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBARn - inbound window base address */ +#define PCIE_IWBEAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD8C + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWBEARn- inbound window base extended address */ +#define PCIE_IWAR(n, w) ((volatile uint32_t*)(PCIE_BASE(n) + 0xD90 + ((3-((w) & 0x3)) * 32))) /* PEXx_PEXIWARn - inbound window attributes */ #define PIWAR_EN 0x80000000 +#define PIWAR_DIEN 0x40000000 #define PIWAR_PF 0x20000000 -#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_TRGT_PCI1 0x00000000 +#define PIWAR_TRGT_PCI2 0x00100000 +#define PIWAR_TRGT_PCI3 0x00200000 +#define PIWAR_TRGT_CCSR 0x00E00000 +#define PIWAR_TRGT_LOCAL 0x00F00000 +#define PIWAR_READ 0x00040000 #define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE 0x00004000 #define PIWAR_WRITE_SNOOP 0x00005000 /* Buffer Manager */ @@ -1167,6 +1175,10 @@ void hal_early_init(void) (1 << 2) /* DIU (LCD) */ )); + set32(DCFG_DEVDISR3, + (1 << 30) /* Disable PEX2 (PCIe2) */ + ); + hal_ddr_init(); } @@ -1177,12 +1189,16 @@ void hal_early_init(void) #define PCI_CONFIG_ADDR_PORT 0xcf8 #define PCI_CONFIG_DATA_PORT 0xcfc static int pcie_bus = 0; +/* See T1024RM 27.12.1.2.3 Byte order for configuration transactions */ void io_write32(uint16_t port, uint32_t value) { if (port == PCI_CONFIG_ADDR_PORT) { set32(PCIE_CONFIG_ADDR(pcie_bus), value); } else if (port == PCI_CONFIG_DATA_PORT) { + #ifdef BIG_ENDIAN_ORDER + value = __builtin_bswap32(value); + #endif set32(PCIE_CONFIG_DATA(pcie_bus), value); } } @@ -1190,46 +1206,55 @@ uint32_t io_read32(uint16_t port) { uint32_t value = 0; if (port == PCI_CONFIG_ADDR_PORT) { - value = get32(PCIE_CONFIG_ADDR(1)); + value = get32(PCIE_CONFIG_ADDR(pcie_bus)); } else if (port == PCI_CONFIG_DATA_PORT) { - value = get32(PCIE_CONFIG_DATA(1)); + value = get32(PCIE_CONFIG_DATA(pcie_bus)); + #ifdef BIG_ENDIAN_ORDER + value = __builtin_bswap32(value); + #endif } return value; } -#define PCI_MMIO32_LENGTH (1024UL * 1024U * 1024U) -#define PCI_MMIO32_PREFETCH_LENGTH (1024UL * 1024U * 1024U) - -#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x00000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_IO_PHYS_HIGH 0xF -#define CONFIG_SYS_PCIE1_IO_PHYS 0xF8000000 -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_PHYS - -#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x10000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_IO_PHYS_HIGHT 0xF -#define CONFIG_SYS_PCIE2_IO_PHYS 0xF8010000 -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_PHYS - -#define CONFIG_SYS_PCIE3_MEM_PHYS_HIGH 0xC -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x20000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xA0000000 -#define CONFIG_SYS_PCIE3_IO_PHYS_HIGH 0xF -#define CONFIG_SYS_PCIE3_IO_PHYS 0xF8020000 -#define CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE3_IO_PHYS +#define CONFIG_PCIE_MEM_BUS 0xE0000000 +#define CONFIG_PCIE_IO_BASE 0x2000 +#define CONFIG_PCIE_MEM_LENGTH (0x10000000) +#define CONFIG_PCIE_MEM_PREFETCH_LENGTH (0x100000) + +#define CONFIG_PCIE1_MEM_PHYS_HIGH 0xCULL +#define CONFIG_PCIE1_MEM_PHYS 0x00000000 +#define CONFIG_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_PCIE1_IO_PHYS_HIGH 0xFULL +#define CONFIG_PCIE1_IO_PHYS 0xF8000000 +#define CONFIG_PCIE1_IO_VIRT CONFIG_PCIE1_IO_PHYS + +#define CONFIG_PCIE2_MEM_PHYS_HIGH 0xCULL +#define CONFIG_PCIE2_MEM_PHYS 0x10000000 +#define CONFIG_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_PCIE2_IO_PHYS_HIGH 0xFULL +#define CONFIG_PCIE2_IO_PHYS 0xF8010000 +#define CONFIG_PCIE2_IO_VIRT CONFIG_PCIE2_IO_PHYS + +#define CONFIG_PCIE3_MEM_PHYS_HIGH 0xCULL +#define CONFIG_PCIE3_MEM_PHYS 0x20000000 +#define CONFIG_PCIE3_MEM_VIRT 0xA0000000 +#define CONFIG_PCIE3_IO_PHYS_HIGH 0xFULL +#define CONFIG_PCIE3_IO_PHYS 0xF8020000 +#define CONFIG_PCIE3_IO_VIRT CONFIG_PCIE3_IO_PHYS static int hal_pcie_init(void) { int ret; int bus, i; - int law_start = 14; + int law_idx = 7; + int tlb_idx = 14; /* next available TLB (after DDR) */ struct pci_enum_info enum_info; + uint64_t mem_phys_h, io_phys_h; + uint32_t mem_phys, io_phys; + uint32_t mem_virt, io_virt; - for (pcie_bus=1; pcie_bus<=3; pcie_bus++) { + for (pcie_bus=1; pcie_bus<=PCIE_MAX_CONTROLLERS; pcie_bus++) { /* Check device disable register */ if (get32(DCFG_DEVDISR3) & (1 << (32-pcie_bus))) { wolfBoot_printf("PCIe %d: Disabled\n", pcie_bus); @@ -1238,110 +1263,126 @@ static int hal_pcie_init(void) /* Read block revision */ wolfBoot_printf("PCIe %d: Base 0x%x, Rev 0x%x\n", - pcie_bus, PCI_BASE(pcie_bus), + pcie_bus, PCIE_BASE(pcie_bus), get32(PCIE_BLK_REV1(pcie_bus))); /* Setup PCIe memory regions */ - memset(&enum_info, 0, sizeof(enum_info)); if (pcie_bus == 1) { - enum_info.mem = CONFIG_SYS_PCIE1_MEM_VIRT; - enum_info.io = CONFIG_SYS_PCIE1_IO_VIRT; - - /* Map TLB for PCIe */ - set_tlb(1, law_start++, CONFIG_SYS_PCIE1_MEM_VIRT, - CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, law_start++, CONFIG_SYS_PCIE1_MEM_VIRT, - CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + mem_virt = CONFIG_PCIE1_MEM_VIRT; + io_virt = CONFIG_PCIE1_IO_VIRT; + mem_phys_h = CONFIG_PCIE1_MEM_PHYS_HIGH; + mem_phys = CONFIG_PCIE1_MEM_PHYS; + io_phys_h = CONFIG_PCIE1_IO_PHYS_HIGH; + io_phys = CONFIG_PCIE1_IO_PHYS; } else if (pcie_bus == 2) { - enum_info.mem = CONFIG_SYS_PCIE2_MEM_VIRT; - enum_info.io = CONFIG_SYS_PCIE2_IO_VIRT; - - /* Map TLB for PCIe */ - set_tlb(1, law_start++, CONFIG_SYS_PCIE2_MEM_VIRT, - CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, law_start++, CONFIG_SYS_PCIE2_MEM_VIRT, - CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + mem_virt = CONFIG_PCIE2_MEM_VIRT; + io_virt = CONFIG_PCIE2_IO_VIRT; + mem_phys_h = CONFIG_PCIE2_MEM_PHYS_HIGH; + mem_phys = CONFIG_PCIE2_MEM_PHYS; + io_phys_h = CONFIG_PCIE2_IO_PHYS_HIGH; + io_phys = CONFIG_PCIE2_IO_PHYS; } else if (pcie_bus == 3) { - enum_info.mem = CONFIG_SYS_PCIE3_MEM_VIRT; - enum_info.io = CONFIG_SYS_PCIE3_IO_VIRT; - - /* Map TLB for PCIe */ - set_tlb(1, law_start++, CONFIG_SYS_PCIE3_MEM_VIRT, - CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, law_start++, CONFIG_SYS_PCIE3_MEM_VIRT, - CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS_HIGH, - (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + mem_virt = CONFIG_PCIE3_MEM_VIRT; + io_virt = CONFIG_PCIE3_IO_VIRT; + mem_phys_h = CONFIG_PCIE3_MEM_PHYS_HIGH; + mem_phys = CONFIG_PCIE3_MEM_PHYS; + io_phys_h = CONFIG_PCIE3_IO_PHYS_HIGH; + io_phys = CONFIG_PCIE3_IO_PHYS; } - enum_info.mem_limit = enum_info.mem + (PCI_MMIO32_LENGTH - 1); - enum_info.mem_pf = (enum_info.mem + PCI_MMIO32_PREFETCH_LENGTH); - enum_info.mem_pf_limit = PCI_MMIO32_PREFETCH_LENGTH; - - /* Setup PCIe Output Windows */ - if (pcie_bus == 1) { - set32( PCIE_OTAR(pcie_bus, 0), 0x0); - set32(PCIE_OTEAR(pcie_bus, 0), 0x0); - set32( PCIE_OWAR(pcie_bus, 0), 0x80044027); - - set32( PCIE_OTAR(pcie_bus, 1), 0xE0000); - set32(PCIE_OTEAR(pcie_bus, 1), 0x0); - set32(PCIE_OWBAR(pcie_bus, 1), 0xC00000); /* MEM_PHYS >> 12 */ - set32( PCIE_OWAR(pcie_bus, 1), 0x8004401B); - set32( PCIE_OTAR(pcie_bus, 2), 0x0); - set32(PCIE_OTEAR(pcie_bus, 2), 0x0); - set32(PCIE_OWBAR(pcie_bus, 2), 0xFF8000); /* IO_PHYS >> 12 */ - set32( PCIE_OWAR(pcie_bus, 2), 0x8008800F); + /* LAW_TRGT_PCIE1 = 0, LAW_TRGT_PCIE2 = 1, LAW_TRGT_PCIE1 = 2 */ + set_law(law_idx++, mem_phys_h, mem_phys, pcie_bus-1, LAW_SIZE_256MB, 1); + set_law(law_idx++, io_phys_h, io_phys, pcie_bus-1, LAW_SIZE_64KB, 1); + + /* Map TLB for PCIe */ + set_tlb(1, tlb_idx++, mem_virt, + mem_phys, mem_phys_h, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, + BOOKE_PAGESZ_256M, 1); + set_tlb(1, tlb_idx++, io_virt, + io_phys, io_phys_h, + (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, + BOOKE_PAGESZ_64K, 1); + + /* PCI I/O Base */ + memset(&enum_info, 0, sizeof(enum_info)); + enum_info.curr_bus_number = 0; + enum_info.mem = CONFIG_PCIE_MEM_BUS; + enum_info.mem_limit = enum_info.mem + (CONFIG_PCIE_MEM_LENGTH - 1); + enum_info.mem_pf = (enum_info.mem + CONFIG_PCIE_MEM_PREFETCH_LENGTH); + enum_info.mem_pf_limit = enum_info.mem_pf + + (CONFIG_PCIE_MEM_PREFETCH_LENGTH - 1); + enum_info.io = CONFIG_PCIE_IO_BASE; - } - else if (pcie_bus == 3) { - set32( PCIE_OTAR(pcie_bus, 0), 0x0); - set32(PCIE_OWBAR(pcie_bus, 0), 0x0); - set32( PCIE_OWAR(pcie_bus, 0), 0x80044027); - - set32( PCIE_OTAR(pcie_bus, 1), 0xE0000); - set32(PCIE_OTEAR(pcie_bus, 1), 0x0); - set32(PCIE_OWBAR(pcie_bus, 1), 0xC20000); /* MEM_PHYS >> 12 */ - set32( PCIE_OWAR(pcie_bus, 1), 0x8004401B); - - set32( PCIE_OTAR(pcie_bus, 2), 0x0); - set32(PCIE_OTEAR(pcie_bus, 2), 0x0); - set32(PCIE_OWBAR(pcie_bus, 2), 0xFF8020); /* IO_PHYS >> 12 */ - set32( PCIE_OWAR(pcie_bus, 2), 0x8008800F); - } + /* Setup PCIe Output Windows */ + /* See T1024RM: 27.12.1.5 PCI Express outbound ATMUs */ + set32( PCIE_OTAR(pcie_bus, 0), 0x0); + set32(PCIE_OTEAR(pcie_bus, 0), 0x0); + set32( PCIE_OWAR(pcie_bus, 0), (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | LAW_SIZE_1TB)); + + /* Outbound Memory */ + set32( PCIE_OTAR(pcie_bus, 1), (CONFIG_PCIE_MEM_BUS >> 12)); + set32(PCIE_OTEAR(pcie_bus, 1), 0x0); + set32(PCIE_OWBAR(pcie_bus, 1), ((mem_phys_h << 32 | mem_phys) >> 12)); + set32( PCIE_OWAR(pcie_bus, 1), (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | LAW_SIZE_256MB)); + + /* Outbound IO */ + set32( PCIE_OTAR(pcie_bus, 2), 0x0); + set32(PCIE_OTEAR(pcie_bus, 2), 0x0); + set32(PCIE_OWBAR(pcie_bus, 2), ((io_phys_h << 32) | io_phys) >> 12); + set32( PCIE_OWAR(pcie_bus, 2), (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | LAW_SIZE_64KB)); + + /* Disabled */ + set32( PCIE_OTAR(pcie_bus, 3), 0x0); + set32(PCIE_OTEAR(pcie_bus, 3), 0x0); + set32(PCIE_OWBAR(pcie_bus, 3), 0x0); + set32( PCIE_OWAR(pcie_bus, 3), 0x0); /* Setup PCIe Input Windows */ - set32( PCIE_ITAR(pcie_bus, 0), 0xFFE000); - set32( PCIE_IWAR(pcie_bus, 0), 0x80E44017); - - set32( PCIE_ITAR(pcie_bus, 1), 0x0); - set32( PCIE_IWBAR(pcie_bus, 1), 0x0); - set32( PCIE_IWAR(pcie_bus, 1), 0xA0F5501E); - - set32( PCIE_ITAR(pcie_bus, 2), 0x0); - set32( PCIE_IWBAR(pcie_bus, 2), 0x1000000); + /* See T1024RM: 27.12.1.6 PCI Express inbound ATMUs */ + /* CCSRBAR */ + set32( PCIE_ITAR(pcie_bus, 0), (CCSRBAR_PHYS >> 12)); + set32( PCIE_IWAR(pcie_bus, 0), (PIWAR_EN | PIWAR_TRGT_CCSR | + PIWAR_READ | PIWAR_WRITE | LAW_SIZE_16MB)); + + /* Map DDR to PCIe */ + set32( PCIE_ITAR(pcie_bus, 1), (DDR_ADDRESS >> 12)); + set32( PCIE_IWBAR(pcie_bus, 1), (DDR_ADDRESS >> 12)); + set32(PCIE_IWBEAR(pcie_bus, 1), 0x0); + set32( PCIE_IWAR(pcie_bus, 1), (PIWAR_EN | PIWAR_PF | + PIWAR_TRGT_LOCAL | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | LAW_SIZE_2GB)); + + /* Map DDR High (64GB) to PCIe */ + set32( PCIE_ITAR(pcie_bus, 2), (DDR_ADDRESS >> 12)); + set32( PCIE_IWBAR(pcie_bus, 2), ((64ull*1024*1024*1024) >> 12)); set32(PCIE_IWBEAR(pcie_bus, 2), 0x0); - set32( PCIE_IWAR(pcie_bus, 2), 0xA0F5501E); + set32( PCIE_IWAR(pcie_bus, 2), (PIWAR_EN | PIWAR_PF | + PIWAR_TRGT_LOCAL | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | LAW_SIZE_2GB)); + /* Disabled */ set32( PCIE_ITAR(pcie_bus, 3), 0x0); set32( PCIE_IWBAR(pcie_bus, 3), 0x0); set32(PCIE_IWBEAR(pcie_bus, 3), 0x0); - set32( PCIE_IWAR(pcie_bus, 3), 0x20F44027); + set32( PCIE_IWAR(pcie_bus, 3), (PIWAR_PF | PIWAR_TRGT_LOCAL | + PIWAR_READ | PIWAR_WRITE | LAW_SIZE_1TB)); - /* TODO: setup PCSRBAR/PEXCSRBAR */ + /* Check if link is active */ - ret = pci_enum_bus(0, &enum_info); - if (ret != 0) { - wolfBoot_printf("PCIe %d: Enum failed %d\n", pcie_bus, ret); - } } + + /* Only enumerate PCIe 3 */ + pcie_bus = 3; + ret = pci_enum_bus(0, &enum_info); + if (ret != 0) { + wolfBoot_printf("PCIe %d: Enum failed %d\n", pcie_bus, ret); + } + return ret; } #endif @@ -2165,9 +2206,9 @@ int hal_dts_fixup(void* dts_addr) p += sizeof(uint64_t); *(uint64_t*)p = cpu_to_fdt64(DDR_SIZE); p += sizeof(uint64_t); - fdt_setprop(fdt, off, "reg", ranges, (int)(p - ranges)); wolfBoot_printf("FDT: Set memory, start=0x%x, size=0x%x\n", DDR_ADDRESS, (uint32_t)DDR_SIZE); + fdt_setprop(fdt, off, "reg", ranges, (int)(p - ranges)); } /* fixup CPU status and, release address and enable method */ @@ -2294,9 +2335,7 @@ int hal_dts_fixup(void* dts_addr) } /* PCIe Ranges */ - i = 0; - off = fdt_node_offset_by_compatible(fdt, -1, "fsl,qoriq-pcie"); - while (off != -FDT_ERR_NOTFOUND) { + for (i=1; i<=PCIE_MAX_CONTROLLERS; i++) { uint32_t dma_ranges[] = { /* TYPE BUS START PHYS SIZE */ (FDT_PCI_MEM32), @@ -2306,19 +2345,43 @@ int hal_dts_fixup(void* dts_addr) (FDT_PCI_PREFETCH | FDT_PCI_MEM32), 0x10, 0x00, 0x00, 0x00, 0x00, 0x80000000 }; - uint32_t bus_range[2]; + uint32_t bus_range[2], base; bus_range[0] = 0; - bus_range[1] = i; - - wolfBoot_printf("FDT: PCI%d: Offset %d\n", i, off); + bus_range[1] = i-1; - /* Set "dma-ranges" */ - fdt_setprop(fdt, off, "dma-ranges", dma_ranges, sizeof(dma_ranges)); - /* Set "bus-range" */ - fdt_setprop(fdt, off, "bus-range", bus_range, sizeof(bus_range)); + /* find offset for pci controlller base register */ + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,qoriq-pcie"); + while (off != -FDT_ERR_NOTFOUND) { + reg = (uint32_t*)fdt_getprop(fdt, off, "reg", NULL); + if (reg == NULL) + break; + reg++; /* skip first part of 64-bit */ + base = fdt32_to_cpu(*reg); + if (base == (uint32_t)PCIE_BASE(i)) { + break; + } + off = fdt_node_offset_by_compatible(fdt, off, "fsl,qoriq-pcie"); + } + if (off == -FDT_ERR_NOTFOUND) + break; - i++; - off = fdt_node_offset_by_compatible(fdt, off, "fsl,qoriq-pcie"); + /* Set ranges or disable if not enabled */ + wolfBoot_printf("FDT: pcie%d@%x, Offset %d\n", i, base, off); + if (get32(DCFG_DEVDISR3) & (1 << (32-i))) { + /* If device disabled, remove node */ + wolfBoot_printf("FDT: PCI%d Disabled, removing\n", i); + off = fdt_del_node(fdt, off); + } + else { + /* Set "dma-ranges" */ + wolfBoot_printf("FDT: Set %s@%d (%d), %s\n", + "pcie", i, off, "dma-ranges"); + fdt_setprop(fdt, off, "dma-ranges", dma_ranges, sizeof(dma_ranges)); + /* Set "bus-range" */ + wolfBoot_printf("FDT: Set %s@%d (%d), %s\n", + "pcie", i, off, "bus-ranges"); + fdt_setprop(fdt, off, "bus-range", bus_range, sizeof(bus_range)); + } } #endif /* !BUILD_LOADER_STAGE1 */ return 0; diff --git a/include/fdt.h b/include/fdt.h index 60d804eb5..08986e075 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -143,6 +143,7 @@ int fdt_find_devtype(void* fdt, int startoff, const char* node); int fdt_node_check_compatible(const void *fdt, int nodeoffset, const char *compatible); int fdt_node_offset_by_compatible(const void *fdt, int startoffset, const char *compatible); int fdt_add_subnode(void* fdt, int parentoff, const char* name); +int fdt_del_node(void *fdt, int nodeoffset); /* helpers to fix/append a property to a node */ int fdt_fixup_str(void* fdt, int off, const char* node, const char* name, const char* str); diff --git a/src/fdt.c b/src/fdt.c index 17da097db..e03cbbb8c 100644 --- a/src/fdt.c +++ b/src/fdt.c @@ -69,6 +69,10 @@ static inline const void *fdt_offset_ptr_(const void *fdt, int offset) { return (const char*)fdt + fdt_off_dt_struct(fdt) + offset; } +static inline void *fdt_offset_ptr_w_(const void *fdt, int offset) +{ + return (char*)fdt + fdt_off_dt_struct(fdt) + offset; +} static inline int fdt_data_size_(void *fdt) { /* the last portion of a FDT is the DT string, so use its offset and size to @@ -347,7 +351,7 @@ static int fdt_add_property_(void *fdt, int nodeoffset, const char *name, return namestroff; } - *prop = (void*)(uintptr_t)fdt_offset_ptr_(fdt, nextoffset); + *prop = fdt_offset_ptr_w_(fdt, nextoffset); proplen = sizeof(**prop) + FDT_TAGALIGN(len); err = fdt_splice_struct_(fdt, *prop, 0, proplen); @@ -647,7 +651,7 @@ int fdt_add_subnode(void* fdt, int parentoff, const char *name) tag = fdt_next_tag(fdt, offset, &nextoffset); } while ((tag == FDT_PROP) || (tag == FDT_NOP)); - nh = (struct fdt_node_header*)fdt_offset_ptr_(fdt, offset); + nh = (struct fdt_node_header*)fdt_offset_ptr_w_(fdt, offset); nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; err = fdt_splice_struct_(fdt, nh, 0, nodelen); @@ -662,6 +666,28 @@ int fdt_add_subnode(void* fdt, int parentoff, const char *name) return err; } +int fdt_del_node(void *fdt, int nodeoffset) +{ + int err; + int offset, endoffset; + int depth = 0; + + err = fdt_check_header(fdt); + if (err != 0) + return err; + + /* find end of node */ + endoffset = nodeoffset; + while ((endoffset >= 0) && (depth >= 0)) { + endoffset = fdt_next_node(fdt, endoffset, &depth); + } + if (endoffset < 0) + return endoffset; + + return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset), + endoffset - nodeoffset, 0); +} + /* adjust the actual total size in the FDT header */ int fdt_shrink(void* fdt) diff --git a/src/pci.c b/src/pci.c index 3f9f275f7..d1f2f151c 100644 --- a/src/pci.c +++ b/src/pci.c @@ -64,16 +64,16 @@ #define PCI_IO32_BASE 0x2000 #endif /* PCI_IO32_BASE */ -#define PCI_ENUM_MAX_DEV 32 -#define PCI_ENUM_MAX_FUN 8 +#define PCI_ENUM_MAX_DEV 32 +#define PCI_ENUM_MAX_FUN 8 #define PCI_ENUM_MAX_BARS 6 -#define PCI_ENUM_MMIND_MASK (0x1) -#define PCI_ENUM_TYPE_MASK (0x1 << 1 | 0x1 << 2) -#define PCI_ENUM_TYPE_SHIFT 1 -#define PCI_ENUM_TYPE_64bit (0x1 << 1) -#define PCI_ENUM_TYPE_32bit (0x1) -#define PCI_ENUM_IS_PREFETCH (0x1 << 3) +#define PCI_ENUM_MMIND_MASK (0x1) +#define PCI_ENUM_TYPE_MASK (0x1 << 1 | 0x1 << 2) +#define PCI_ENUM_TYPE_SHIFT 1 +#define PCI_ENUM_TYPE_64bit (0x1 << 1) +#define PCI_ENUM_TYPE_32bit (0x1) +#define PCI_ENUM_IS_PREFETCH (0x1 << 3) #define PCI_ENUM_MM_BAR_MASK ~(0xf) #define PCI_ENUM_IO_BAR_MASK ~(0x3) @@ -189,21 +189,14 @@ static void pci_ecam_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, #define PCI_CONFIG_ADDR_PORT 0xcf8 #define PCI_CONFIG_DATA_PORT 0xcfc -/* Shifts & masks for CONFIG_ADDRESS register */ - -#define PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT 31 -#define PCI_CONFIG_ADDRESS_BUS_SHIFT 16 -#define PCI_CONFIG_ADDRESS_DEVICE_SHIFT 11 -#define PCI_CONFIG_ADDRESS_FUNCTION_SHIFT 8 -#define PCI_CONFIG_ADDRESS_OFFSET_MASK 0xFF - #define PCI_IO_CONFIG_ADDR(bus, dev, fn, off) \ (uint32_t)( \ - (1 << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ + (1UL << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ (bus << PCI_CONFIG_ADDRESS_BUS_SHIFT) | \ (dev << PCI_CONFIG_ADDRESS_DEVICE_SHIFT) | \ (fn << PCI_CONFIG_ADDRESS_FUNCTION_SHIFT) | \ - (off & PCI_CONFIG_ADDRESS_OFFSET_MASK)) + ((off & 0xF00) << 16) | \ + (off & PCI_CONFIG_ADDRESS_OFFSET_MASK)) static uint32_t pci_io_config_read32(uint32_t bus, uint32_t dev, uint32_t func, uint32_t off) @@ -238,11 +231,12 @@ static uint16_t pci_io_config_read16(uint32_t bus, uint32_t dev, uint32_t func, address = pci_align32_address(address, &aligned32); data = pci_io_config_read32(bus, dev, func, address); + //PCI_DEBUG_PRINTF("CONFIG_READ16: address %x, data %x (aligned32 %d)\n", address, data, aligned32); if (!aligned32) data >>= PCI_DATA_HI16_SHIFT; else data &= PCI_DATA_LO16_MASK; - + //PCI_DEBUG_PRINTF("\tCONFIG_READ16: data %x\n", data); return (uint16_t)data; } @@ -256,8 +250,10 @@ static void pci_io_config_write16(uint32_t bus, uint32_t dev, uint32_t func, /* off must be 16 bit aligned */ if ((dst_addr & PCI_ADDR_16BIT_ALIGNED_MASK) != 0) return; + dst_addr = pci_align32_address(dst_addr, &aligned32); reg = pci_io_config_read32(bus, dev, func, dst_addr); + //PCI_DEBUG_PRINTF("CONFIG_WRITE16: address %x, data %x (aligned32 %d)\n", dst_addr, val, aligned32); if (aligned32) { reg &= PCI_DATA_HI16_MASK; reg |= val; @@ -265,6 +261,7 @@ static void pci_io_config_write16(uint32_t bus, uint32_t dev, uint32_t func, reg &= PCI_DATA_LO16_MASK; reg |= (val << PCI_DATA_HI16_SHIFT); } + //PCI_DEBUG_PRINTF("\tCONFIG_WRITE16: data %x\n", reg); pci_io_config_write32(bus, dev, func, dst_addr, reg); } #endif /* PCI_USE_ECAM */ @@ -315,11 +312,13 @@ void pci_config_write8(uint8_t bus, uint32_t reg; off_aligned = align_down(off, 4); + reg = pci_config_read32(bus, dev, fun, off_aligned); shift = (off & PCI_ADDR_32BIT_ALIGNED_MASK) * 8; mask = 0xff << shift; - reg = pci_config_read32(bus, dev, fun, off_aligned); + //PCI_DEBUG_PRINTF("CONFIG_WRITE8: address %x, data %x (mask %x, shift %d)\n", off_aligned, value, mask, shift); reg &= ~(mask); reg |= (value << shift); + //PCI_DEBUG_PRINTF("\tCONFIG_WRITE8: data %x\n", reg); pci_config_write32(bus, dev, fun, off_aligned, reg); } @@ -330,11 +329,14 @@ uint8_t pci_config_read8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off) uint32_t reg; off_aligned = align_down(off, 4); + reg = pci_config_read32(bus, dev, fun, off_aligned); shift = (off & PCI_ADDR_32BIT_ALIGNED_MASK) * 8; mask = 0xff << shift; - reg = pci_config_read32(bus, dev, fun, off_aligned); + //PCI_DEBUG_PRINTF("CONFIG_READ8: address %x, data %x (mask %x, shift %d)\n", off_aligned, reg, mask, shift); reg &= mask; - return (reg >> shift); + reg = (reg >> shift); + //PCI_DEBUG_PRINTF("\tCONFIG_READ8: data %x\n", reg); + return reg; } uint64_t pci_get_mmio_addr(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t bar) @@ -624,6 +626,9 @@ static int pci_program_bridge(uint8_t bus, uint8_t dev, uint8_t fun, pci_config_write8(bus, dev, fun, PCI_PRIMARY_BUS, bus); pci_config_write8(bus, dev, fun, PCI_SECONDARY_BUS, info->curr_bus_number); + PCI_DEBUG_PRINTF("Info: bus %d, mem %p-%p, io %p, pf %p-%p\n", + info->curr_bus_number, info->mem, info->mem_limit, info->io, info->mem_pf, info->mem_pf_limit); + /* temporarly allows all conf transaction on the bus range * (curr_bus_number,0xff) to scan the bus behind the bridge */ pci_config_write8(bus, dev, fun, PCI_SUB_SEC_BUS, 0xff); From 38f88b7fdad6faf49599348c7b295062d60789c7 Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 31 Jan 2024 16:32:55 -0800 Subject: [PATCH 03/11] Fix for T1024 CPLD. Reads: ``` CPLD BOARD_ID: 0x41503031 CPLD PLD_VER: 0x42 ``` --- hal/nxp_t1024.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 544ce553f..99a31aa5f 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -430,23 +430,23 @@ static void hal_flash_unlock_sector(uint32_t sector); /* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */ enum ifc_amask_sizes { - IFC_AMASK_64KB = 0xFFFF, - IFC_AMASK_128KB = 0xFFFE, - IFC_AMASK_256KB = 0xFFFC, - IFC_AMASK_512KB = 0xFFF8, - IFC_AMASK_1MB = 0xFFF0, - IFC_AMASK_2MB = 0xFFE0, - IFC_AMASK_4MB = 0xFFC0, - IFC_AMASK_8MB = 0xFF80, - IFC_AMASK_16MB = 0xFF00, - IFC_AMASK_32MB = 0xFE00, - IFC_AMASK_64MB = 0xFC00, - IFC_AMASK_128MB = 0xF800, - IFC_AMASK_256MB = 0xF000, - IFC_AMASK_512MB = 0xE000, - IFC_AMASK_1GB = 0xC000, - IFC_AMASK_2GB = 0x8000, - IFC_AMASK_4GB = 0x0000, + IFC_AMASK_64KB = 0xFFFF0000, + IFC_AMASK_128KB = 0xFFFE0000, + IFC_AMASK_256KB = 0xFFFC0000, + IFC_AMASK_512KB = 0xFFF80000, + IFC_AMASK_1MB = 0xFFF00000, + IFC_AMASK_2MB = 0xFFE00000, + IFC_AMASK_4MB = 0xFFC00000, + IFC_AMASK_8MB = 0xFF800000, + IFC_AMASK_16MB = 0xFF000000, + IFC_AMASK_32MB = 0xFE000000, + IFC_AMASK_64MB = 0xFC000000, + IFC_AMASK_128MB = 0xF8000000, + IFC_AMASK_256MB = 0xF0000000, + IFC_AMASK_512MB = 0xE0000000, + IFC_AMASK_1GB = 0xC0000000, + IFC_AMASK_2GB = 0x80000000, + IFC_AMASK_4GB = 0x00000000, }; /* NOR Flash */ @@ -1404,7 +1404,7 @@ static void hal_cpld_ifc_init(uint32_t base, uint32_t base_high, uint8_t ifc) /* CPLD IFC Definitions (CS2) */ set32(IFC_CSPR_EXT(ifc), base_high); set32(IFC_CSPR(ifc), (IFC_CSPR_PHYS_ADDR(base) | - IFC_CSPR_PORT_SIZE_8 | + IFC_CSPR_PORT_SIZE_16 | IFC_CSPR_MSEL_GPCM | IFC_CSPR_V)); set32(IFC_AMASK(ifc), IFC_AMASK_64KB); From e33f51cdfded8a4d0d5fe0553de9dd7cb73d3307 Mon Sep 17 00:00:00 2001 From: David Garske Date: Thu, 1 Feb 2024 10:43:30 -0800 Subject: [PATCH 04/11] Improvements for CPLD. Patch for PCIe from TigerLake. --- hal/nxp_t1024.c | 85 +++++++++++++++++++++++++++++++++++++++---------- hal/nxp_t2080.c | 34 ++++++++++---------- src/pci.c | 10 ++++-- 3 files changed, 93 insertions(+), 36 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 99a31aa5f..bc7800b90 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -104,9 +104,14 @@ static void hal_flash_unlock_sector(uint32_t sector); #define DCFG_DEVDISR4 ((volatile uint32_t*)(DCFG_BASE + 0x7CUL)) /* Device disable register */ #define DCFG_DEVDISR5 ((volatile uint32_t*)(DCFG_BASE + 0x80UL)) /* Device disable register */ #define DCFG_COREDISR ((volatile uint32_t*)(DCFG_BASE + 0x94UL)) /* Core Enable/Disable */ +#define DCFG_RCWSR(n) ((volatile uint32_t*)(DCFG_BASE + 0x100UL + ((n) * 4))) /* Reset Control Word Status Register (0-15) */ #define DCFG_BRR ((volatile uint32_t*)(DCFG_BASE + 0xE4UL)) /* Boot Release Register (DCFG_CCSR_BRR) */ #define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */ +/* RCW */ +#define RCWSR4_SRDS1_PRTCL 0xFF800000 +#define RCWSR4_SRDS1_PRTCL_SHIFT 23 + /* Logical I/O Device Number */ #define DCFG_USB1LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x520)) #define DCFG_USB2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x524)) @@ -666,13 +671,12 @@ enum ifc_amask_sizes { #define POWER_STATUS_ADDRR 0x0400 #define MPU_INT_STATUS_ADDR 0x0402 #define MPU_INT_ENABLE_ADDR 0x0404 -#define MPU_CONTROL_ADDR 0x042E -#define MPU_RESET_ADDR 0x0430 -#define PCI_STATUS_ADDR 0x0432 -#define HS_CSR_ADDR 0x103C -#define CPCI_GA_ADDRS 0x103E -#define CPCI_INTX_ADDR 0x1040 -#define PLD_CURRENT_VERSION 0x1042 +#define MPU_CONTROL_ADDR 0x0430 +#define MPU_RESET_ADDR 0x0432 +#define PCI_STATUS_ADDR 0x0434 +#define HS_CSR_ADDR 0x1040 +#define CPCI_GA_ADDRS 0x1042 +#define CPCI_INTX_ADDR 0x1044 #define CPLD_LBMAP_MASK 0x3F #define CPLD_BANK_SEL_MASK 0x07 @@ -687,7 +691,9 @@ enum ifc_amask_sizes { #define CPLD_OVERRIDE_BOOT_EN 0x01 #define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ -#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + n)) +#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + (n))) +#define CPLD_READ(reg) get16(CPLD_DATA(((reg)))) +#define CPLD_WRITE(reg, value) set16(CPLD_DATA((reg), (value))) /* eSPI */ @@ -1193,9 +1199,11 @@ static int pcie_bus = 0; void io_write32(uint16_t port, uint32_t value) { if (port == PCI_CONFIG_ADDR_PORT) { + //wolfBoot_printf("WRITE32 Addr %x\n", value); set32(PCIE_CONFIG_ADDR(pcie_bus), value); } else if (port == PCI_CONFIG_DATA_PORT) { + //wolfBoot_printf("WRITE32 Data %x\n", value); #ifdef BIG_ENDIAN_ORDER value = __builtin_bswap32(value); #endif @@ -1207,12 +1215,14 @@ uint32_t io_read32(uint16_t port) uint32_t value = 0; if (port == PCI_CONFIG_ADDR_PORT) { value = get32(PCIE_CONFIG_ADDR(pcie_bus)); + //wolfBoot_printf("READ32 Addr %x\n", value); } else if (port == PCI_CONFIG_DATA_PORT) { value = get32(PCIE_CONFIG_DATA(pcie_bus)); #ifdef BIG_ENDIAN_ORDER value = __builtin_bswap32(value); #endif + //wolfBoot_printf("READ32 Data %x\n", value); } return value; } @@ -1253,6 +1263,27 @@ static int hal_pcie_init(void) uint64_t mem_phys_h, io_phys_h; uint32_t mem_phys, io_phys; uint32_t mem_virt, io_virt; + uint32_t rcw4, srds_prtcl_s1; + uint16_t cpld_pci; + + /* Configure Lane B */ + cpld_pci = CPLD_READ(PCI_STATUS_ADDR); + rcw4 = get32(DCFG_RCWSR(4)); + srds_prtcl_s1 = (rcw4 & RCWSR4_SRDS1_PRTCL) >> RCWSR4_SRDS1_PRTCL_SHIFT; + wolfBoot_printf("CPLD PCI 0x%x, RCW4 0x%x, SRDS1_PRTCL 0x%x\n", + cpld_pci, rcw4, srds_prtcl_s1); + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci & ~CPLD_PCIE_SGMII_MUX); + wolfBoot_printf("Route Lane B->PCIE\n"); + } + else { + /* Route Lane B to SGMII */ + set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci | CPLD_PCIE_SGMII_MUX); + wolfBoot_printf("Route Lane B->SGMII\n"); + } + cpld_pci = CPLD_READ(PCI_STATUS_ADDR); + wolfBoot_printf("CPLD PCI 0x%x\n", cpld_pci); for (pcie_bus=1; pcie_bus<=PCIE_MAX_CONTROLLERS; pcie_bus++) { /* Check device disable register */ @@ -1411,12 +1442,32 @@ static void hal_cpld_ifc_init(uint32_t base, uint32_t base_high, uint8_t ifc) set32(IFC_CSOR(ifc), 0); } #endif + +#if defined(ENABLE_CPLD) && defined(DEBUG) +void hal_cpld_dump(void) +{ + wolfBoot_printf("\n--------------------\n"); + wolfBoot_printf("CPLD Dump\n"); + wolfBoot_printf("BOARD_ID_L_Addr = 0x%04x\n", CPLD_READ(BOARD_ID_L_ADDR)); + wolfBoot_printf("BOARD_ID_H_Addr = 0x%04x\n", CPLD_READ(BOARD_ID_H_ADDR)); + wolfBoot_printf("PLD_VER_Addr = 0x%04x\n", CPLD_READ(PLD_VER_ADDR)); + wolfBoot_printf("Power_Status_Addrr = 0x%04x\n", CPLD_READ(POWER_STATUS_ADDRR)); + wolfBoot_printf("MPU_Int_Status_Addr = 0x%04x\n", CPLD_READ(MPU_INT_STATUS_ADDR)); + wolfBoot_printf("MPU_Int_Enable_Addr = 0x%04x\n", CPLD_READ(MPU_INT_ENABLE_ADDR)); + wolfBoot_printf("MPU_Control_Addr = 0x%04x\n", CPLD_READ(MPU_CONTROL_ADDR)); + wolfBoot_printf("MPU_Reset_Addr = 0x%04x\n", CPLD_READ(MPU_RESET_ADDR)); + wolfBoot_printf("PCI_Status_Addr = 0x%04x\n", CPLD_READ(PCI_STATUS_ADDR)); + wolfBoot_printf("HS_CSR_Addr = 0x%04x\n", CPLD_READ(HS_CSR_ADDR)); + wolfBoot_printf("CPCI_GA_Addr = 0x%04x\n", CPLD_READ(CPCI_GA_ADDRS)); + wolfBoot_printf("CPCI_INTx_Addr = 0x%04x\n", CPLD_READ(CPCI_INTX_ADDR)); + wolfBoot_printf("\n--------------------\n"); +} +#endif + static void hal_cpld_init(void) { #ifdef ENABLE_CPLD - #ifdef DEBUG - uint32_t fw; - #endif + uint32_t reg; /* CPLD (APU) IFC 2 - LAW 2, TLB 1.11 */ hal_cpld_ifc_init(CPLD_BASE, CPLD_BASE_PHYS_HIGH, 2); @@ -1435,12 +1486,14 @@ static void hal_cpld_init(void) (MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); + reg = CPLD_READ(BOARD_ID_L_ADDR) << 16; + reg |= CPLD_READ(BOARD_ID_H_ADDR); + wolfBoot_printf("CPLD BOARD_ID: 0x%x\n", reg); + reg = CPLD_READ(PLD_VER_ADDR); + wolfBoot_printf("CPLD PLD_VER: 0x%x\n", reg); + #ifdef DEBUG - fw = get16(CPLD_DATA(BOARD_ID_L_ADDR)) << 16; - fw |= get16(CPLD_DATA(BOARD_ID_H_ADDR)); - wolfBoot_printf("CPLD BOARD_ID: 0x%x\n", fw); - fw = get16(CPLD_DATA(PLD_VER_ADDR)); - wolfBoot_printf("CPLD PLD_VER: 0x%x\n", fw); + hal_cpld_dump(); #endif #endif /* ENABLE_CPLD */ } diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index ea0f4eb65..00b7d1f01 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -105,23 +105,23 @@ /* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */ enum ifc_amask_sizes { - IFC_AMASK_64KB = 0xFFFF, - IFC_AMASK_128KB = 0xFFFE, - IFC_AMASK_256KB = 0xFFFC, - IFC_AMASK_512KB = 0xFFF8, - IFC_AMASK_1MB = 0xFFF0, - IFC_AMASK_2MB = 0xFFE0, - IFC_AMASK_4MB = 0xFFC0, - IFC_AMASK_8MB = 0xFF80, - IFC_AMASK_16MB = 0xFF00, - IFC_AMASK_32MB = 0xFE00, - IFC_AMASK_64MB = 0xFC00, - IFC_AMASK_128MB = 0xF800, - IFC_AMASK_256MB = 0xF000, - IFC_AMASK_512MB = 0xE000, - IFC_AMASK_1GB = 0xC000, - IFC_AMASK_2GB = 0x8000, - IFC_AMASK_4GB = 0x0000, + IFC_AMASK_64KB = 0xFFFF0000, + IFC_AMASK_128KB = 0xFFFE0000, + IFC_AMASK_256KB = 0xFFFC0000, + IFC_AMASK_512KB = 0xFFF80000, + IFC_AMASK_1MB = 0xFFF00000, + IFC_AMASK_2MB = 0xFFE00000, + IFC_AMASK_4MB = 0xFFC00000, + IFC_AMASK_8MB = 0xFF800000, + IFC_AMASK_16MB = 0xFF000000, + IFC_AMASK_32MB = 0xFE000000, + IFC_AMASK_64MB = 0xFC000000, + IFC_AMASK_128MB = 0xF8000000, + IFC_AMASK_256MB = 0xF0000000, + IFC_AMASK_512MB = 0xE0000000, + IFC_AMASK_1GB = 0xC0000000, + IFC_AMASK_2GB = 0x80000000, + IFC_AMASK_4GB = 0x00000000, }; diff --git a/src/pci.c b/src/pci.c index d1f2f151c..39624fa86 100644 --- a/src/pci.c +++ b/src/pci.c @@ -50,14 +50,18 @@ #define PCI_DATA_HI16_MASK (0xffff0000) #define PCI_DATA_HI16_SHIFT (16) +/* PCI address space starts at 0x80000000 (2GB), on TGL ECAM starts at + * 0xC0000000 (3GB). So there is 1 GB under the 4GB boundary available. By + * default allocate 128MB for normal memory and 896MB for prefetchable + * memory. */ #ifndef PCI_MMIO32_BASE #define PCI_MMIO32_BASE 0x80000000ULL -#define PCI_MMIO32_LENGTH (1024U * 1024U * 1024U) +#define PCI_MMIO32_LENGTH (128U * 1024U * 1024U) #endif /* PCI_MMIO32_BASE */ #ifndef PCI_MMIO32_PREFETCH_BASE -#define PCI_MMIO32_PREFETCH_BASE (PCI_MMIO32_BASE + (1024ULL * 1024ULL * 1024ULL)) -#define PCI_MMIO32_PREFETCH_LENGTH (1024UL * 1024U * 1024U) +#define PCI_MMIO32_PREFETCH_BASE (PCI_MMIO32_BASE + PCI_MMIO32_LENGTH) +#define PCI_MMIO32_PREFETCH_LENGTH (896U * 1024U * 1024U) #endif /* PCI_MMIO32_PREFETCH_BASE */ #ifndef PCI_IO32_BASE From 90c5ada05bb7f40c44e0dda6291b192a29f7f73a Mon Sep 17 00:00:00 2001 From: David Garske Date: Thu, 1 Feb 2024 11:54:14 -0800 Subject: [PATCH 05/11] CPLD Fixes. Add MRAM support. --- hal/nxp_t1024.c | 64 +++++++++++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 18 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index bc7800b90..d5c6ac084 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -50,6 +50,7 @@ #define ENABLE_CPLD #define ENABLE_QE /* QUICC Engine */ #define ENABLE_FMAN + #define ENABLE_MRAM #if defined(WOLFBOOT_TPM) || defined(TEST_TPM) #define ENABLE_ESPI /* SPI for TPM */ @@ -692,8 +693,13 @@ enum ifc_amask_sizes { #define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ #define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + (n))) -#define CPLD_READ(reg) get16(CPLD_DATA(((reg)))) -#define CPLD_WRITE(reg, value) set16(CPLD_DATA((reg), (value))) +#define CPLD_READ(reg) get16(CPLD_DATA(reg)) +#define CPLD_WRITE(reg, value) set16(CPLD_DATA(reg), value) + +/* MRAM */ +#define MRAM_BASE 0xFF800000 +#define MRAM_BASE_PHYS_HIGH 0xFULL + /* eSPI */ @@ -1257,7 +1263,7 @@ static int hal_pcie_init(void) { int ret; int bus, i; - int law_idx = 7; + int law_idx = 8; int tlb_idx = 14; /* next available TLB (after DDR) */ struct pci_enum_info enum_info; uint64_t mem_phys_h, io_phys_h; @@ -1274,12 +1280,12 @@ static int hal_pcie_init(void) cpld_pci, rcw4, srds_prtcl_s1); if (srds_prtcl_s1 == 0x95) { /* Route Lane B to PCIE */ - set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci & ~CPLD_PCIE_SGMII_MUX); + CPLD_WRITE(PCI_STATUS_ADDR, cpld_pci & ~CPLD_PCIE_SGMII_MUX); wolfBoot_printf("Route Lane B->PCIE\n"); } else { /* Route Lane B to SGMII */ - set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci | CPLD_PCIE_SGMII_MUX); + CPLD_WRITE(PCI_STATUS_ADDR, cpld_pci | CPLD_PCIE_SGMII_MUX); wolfBoot_printf("Route Lane B->SGMII\n"); } cpld_pci = CPLD_READ(PCI_STATUS_ADDR); @@ -1418,31 +1424,48 @@ static int hal_pcie_init(void) } #endif -#ifdef ENABLE_CPLD -static void hal_cpld_ifc_init(uint32_t base, uint32_t base_high, uint8_t ifc) +#if defined(ENABLE_CPLD) || defined(ENABLE_MRAM) +static void hal_ifc_init(uint8_t ifc, uint32_t base, uint32_t base_high, + uint32_t port_sz, uint32_t amask) { /* CPLD IFC Timing Parameters */ set32(IFC_FTIM0(ifc), (IFC_FTIM0_GPCM_TACSE(14UL) | - IFC_FTIM0_GPCM_TEADC(14UL) | - IFC_FTIM0_GPCM_TEAHC(14UL))); + IFC_FTIM0_GPCM_TEADC(14UL) | + IFC_FTIM0_GPCM_TEAHC(14UL))); set32(IFC_FTIM1(ifc), (IFC_FTIM1_GPCM_TACO(14UL) | - IFC_FTIM1_GPCM_TRAD(31UL))); + IFC_FTIM1_GPCM_TRAD(31UL))); set32(IFC_FTIM2(ifc), (IFC_FTIM2_GPCM_TCS(14UL) | - IFC_FTIM2_GPCM_TCH(8UL) | - IFC_FTIM2_GPCM_TWP(31UL))); + IFC_FTIM2_GPCM_TCH(8UL) | + IFC_FTIM2_GPCM_TWP(31UL))); set32(IFC_FTIM3(ifc), 0); /* CPLD IFC Definitions (CS2) */ set32(IFC_CSPR_EXT(ifc), base_high); set32(IFC_CSPR(ifc), (IFC_CSPR_PHYS_ADDR(base) | - IFC_CSPR_PORT_SIZE_16 | - IFC_CSPR_MSEL_GPCM | - IFC_CSPR_V)); - set32(IFC_AMASK(ifc), IFC_AMASK_64KB); + port_sz | + IFC_CSPR_MSEL_GPCM | + IFC_CSPR_V)); + set32(IFC_AMASK(ifc), amask); set32(IFC_CSOR(ifc), 0); } #endif +#ifdef ENABLE_MRAM +static void hal_mram_init(void) +{ + /* MRAM IFC Timing Parameters */ + hal_ifc_init(1, MRAM_BASE, MRAM_BASE_PHYS_HIGH, + IFC_CSPR_PORT_SIZE_8, IFC_AMASK_1MB); + + /* MRAM IFC 1 - LAW 7, TLB 1.4 */ + set_law(7, MRAM_BASE_PHYS_HIGH, MRAM_BASE, LAW_TRGT_IFC, LAW_SIZE_1MB, 1); + set_tlb(1, 4, MRAM_BASE, + MRAM_BASE, MRAM_BASE_PHYS_HIGH, + (MAS3_SX | MAS3_SW | MAS3_SR), + (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_1M, 1); +} +#endif + #if defined(ENABLE_CPLD) && defined(DEBUG) void hal_cpld_dump(void) { @@ -1470,7 +1493,8 @@ static void hal_cpld_init(void) uint32_t reg; /* CPLD (APU) IFC 2 - LAW 2, TLB 1.11 */ - hal_cpld_ifc_init(CPLD_BASE, CPLD_BASE_PHYS_HIGH, 2); + hal_ifc_init(2, CPLD_BASE, CPLD_BASE_PHYS_HIGH, + IFC_CSPR_PORT_SIZE_16, IFC_AMASK_64KB); set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, LAW_TRGT_IFC, LAW_SIZE_64KB, 1); set_tlb(1, 11, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, @@ -1478,7 +1502,8 @@ static void hal_cpld_init(void) (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1); /* CPLD (MPU) IFC 3 - LAW 6, TLB 1.10 */ - hal_cpld_ifc_init(CPLD_MPU_BASE, CPLD_MPU_BASE_PHYS_HIGH, 3); + hal_ifc_init(3, CPLD_MPU_BASE, CPLD_MPU_BASE_PHYS_HIGH, + IFC_CSPR_PORT_SIZE_16, IFC_AMASK_64KB); set_law(6, CPLD_MPU_BASE_PHYS_HIGH, CPLD_MPU_BASE, LAW_TRGT_IFC, LAW_SIZE_64KB, 1); set_tlb(1, 10, CPLD_MPU_BASE, @@ -2032,6 +2057,9 @@ void hal_init(void) hal_liodn_init(); hal_flash_init(); hal_cpld_init(); +#ifdef ENABLE_MRAM + hal_mram_init(); +#endif #ifdef ENABLE_PCIE if (hal_pcie_init() != 0) { wolfBoot_printf("PCIe: init failed!\n"); From 98ed8e1468da28c428f7f54c47f1105cf0483478 Mon Sep 17 00:00:00 2001 From: David Garske Date: Thu, 1 Feb 2024 13:57:27 -0800 Subject: [PATCH 06/11] Cleanups. --- hal/nxp_t1024.c | 10 ++++++++-- src/boot_ppc.c | 1 + src/pci.c | 15 ++++----------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index d5c6ac084..02e1d8dd6 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -1408,9 +1408,14 @@ static int hal_pcie_init(void) set32( PCIE_IWAR(pcie_bus, 3), (PIWAR_PF | PIWAR_TRGT_LOCAL | PIWAR_READ | PIWAR_WRITE | LAW_SIZE_1TB)); - /* Check if link is active */ - + #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ + #define PCI_LTSSM_L0 0x16 /* L0 state */ + /* TODO: Check if link is active. Read config PCI_LTSSM */ + #if 0 + link = pci_config_read16(0, 0, 0, PCI_LTSSM); + enabled = (link >= PCI_LTSSM_L0); + #endif } /* Only enumerate PCIe 3 */ @@ -2465,6 +2470,7 @@ int hal_dts_fixup(void* dts_addr) } } #endif /* !BUILD_LOADER_STAGE1 */ + (void)dts_addr; return 0; } #endif /* MMU */ diff --git a/src/boot_ppc.c b/src/boot_ppc.c index e63b1ece6..941cadb57 100644 --- a/src/boot_ppc.c +++ b/src/boot_ppc.c @@ -108,6 +108,7 @@ void __attribute((weak)) hal_early_init(void) #ifdef MMU int __attribute((weak)) hal_dts_fixup(void* dts_addr) { + (void)dts_addr; return 0; } #endif diff --git a/src/pci.c b/src/pci.c index 39624fa86..f39b7b0d4 100644 --- a/src/pci.c +++ b/src/pci.c @@ -235,12 +235,10 @@ static uint16_t pci_io_config_read16(uint32_t bus, uint32_t dev, uint32_t func, address = pci_align32_address(address, &aligned32); data = pci_io_config_read32(bus, dev, func, address); - //PCI_DEBUG_PRINTF("CONFIG_READ16: address %x, data %x (aligned32 %d)\n", address, data, aligned32); if (!aligned32) data >>= PCI_DATA_HI16_SHIFT; else data &= PCI_DATA_LO16_MASK; - //PCI_DEBUG_PRINTF("\tCONFIG_READ16: data %x\n", data); return (uint16_t)data; } @@ -257,7 +255,6 @@ static void pci_io_config_write16(uint32_t bus, uint32_t dev, uint32_t func, dst_addr = pci_align32_address(dst_addr, &aligned32); reg = pci_io_config_read32(bus, dev, func, dst_addr); - //PCI_DEBUG_PRINTF("CONFIG_WRITE16: address %x, data %x (aligned32 %d)\n", dst_addr, val, aligned32); if (aligned32) { reg &= PCI_DATA_HI16_MASK; reg |= val; @@ -265,7 +262,6 @@ static void pci_io_config_write16(uint32_t bus, uint32_t dev, uint32_t func, reg &= PCI_DATA_LO16_MASK; reg |= (val << PCI_DATA_HI16_SHIFT); } - //PCI_DEBUG_PRINTF("\tCONFIG_WRITE16: data %x\n", reg); pci_io_config_write32(bus, dev, func, dst_addr, reg); } #endif /* PCI_USE_ECAM */ @@ -319,10 +315,8 @@ void pci_config_write8(uint8_t bus, reg = pci_config_read32(bus, dev, fun, off_aligned); shift = (off & PCI_ADDR_32BIT_ALIGNED_MASK) * 8; mask = 0xff << shift; - //PCI_DEBUG_PRINTF("CONFIG_WRITE8: address %x, data %x (mask %x, shift %d)\n", off_aligned, value, mask, shift); reg &= ~(mask); reg |= (value << shift); - //PCI_DEBUG_PRINTF("\tCONFIG_WRITE8: data %x\n", reg); pci_config_write32(bus, dev, fun, off_aligned, reg); } @@ -336,10 +330,8 @@ uint8_t pci_config_read8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t off) reg = pci_config_read32(bus, dev, fun, off_aligned); shift = (off & PCI_ADDR_32BIT_ALIGNED_MASK) * 8; mask = 0xff << shift; - //PCI_DEBUG_PRINTF("CONFIG_READ8: address %x, data %x (mask %x, shift %d)\n", off_aligned, reg, mask, shift); reg &= mask; reg = (reg >> shift); - //PCI_DEBUG_PRINTF("\tCONFIG_READ8: data %x\n", reg); return reg; } @@ -420,6 +412,10 @@ static int pci_pre_enum_cb(uint8_t bus, uint8_t dev, uint8_t fun) /* PMC BARs shouldn't be programmed as per FSP integration guide */ if (dev == 31 && fun == 2) return 1; +#else + (void)bus; + (void)dev; + (void)fun; #endif /* WOLFBOOT_TGL */ return 0; } @@ -630,9 +626,6 @@ static int pci_program_bridge(uint8_t bus, uint8_t dev, uint8_t fun, pci_config_write8(bus, dev, fun, PCI_PRIMARY_BUS, bus); pci_config_write8(bus, dev, fun, PCI_SECONDARY_BUS, info->curr_bus_number); - PCI_DEBUG_PRINTF("Info: bus %d, mem %p-%p, io %p, pf %p-%p\n", - info->curr_bus_number, info->mem, info->mem_limit, info->io, info->mem_pf, info->mem_pf_limit); - /* temporarly allows all conf transaction on the bus range * (curr_bus_number,0xff) to scan the bus behind the bridge */ pci_config_write8(bus, dev, fun, PCI_SUB_SEC_BUS, 0xff); From b8c68a6e90b1e59f7a40f861d39c3f93acb5ddc5 Mon Sep 17 00:00:00 2001 From: David Garske Date: Mon, 5 Feb 2024 13:10:36 -0800 Subject: [PATCH 07/11] Fix for T1024 CPU core clock calculation. --- docs/Targets.md | 1 + hal/nxp_t1024.c | 34 ++++++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/docs/Targets.md b/docs/Targets.md index 5a32dc354..b8ec9066e 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -1381,6 +1381,7 @@ Default NOR Flash Memory Layout (64MB) (128KB block, 1K page) | Swap Sector | 0xEC0F0000 | 0x00010000 ( 64 KB) | | Free | 0xEC100000 | 0x00100000 ( 1 MB) | | Update (OS) | 0xEC200000 | 0x01E00000 ( 30 MB) | +| Ethenet Config | 0xED0E0000 | 0x00000400 ( 1 KB) | | Application (OS) | 0xEE000000 | 0x01E00000 ( 30 MB) | | QUICC | 0xEFE00000 | 0x00100000 ( 1 MB) | | DPAA (FMAN) | 0xEFF00000 | 0x00020000 (128 KB) | diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 02e1d8dd6..3ba949179 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -192,8 +192,16 @@ static void hal_flash_unlock_sector(uint32_t sector); /* T1024RM: 4.6.5 */ -#define CLOCKING_BASE (CCSRBAR + 0xE1000) -#define CLOCKING_PLLPGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC00UL)) /* Platform PLL general status register */ +#define CLOCKING_BASE (CCSRBAR + 0xE1000) +#define CLOCKING_CLKCCSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x000UL + ((n) * 0x20))) /* Core cluster n clock control/status register */ +#define CLOCKING_CLKCGHWACSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x010UL + ((n) * 0x20))) /* Clock generator n hardware accelerator control/status */ +#define CLOCKING_PLLCNGSR(n) ((volatile uint32_t*)(CLOCKING_BASE + 0x800UL + ((n) * 0x20))) /* PLL cluster n general status register */ +#define CLOCKING_CLKPCSR ((volatile uint32_t*)(CLOCKING_BASE + 0xA00UL)) /* Platform clock domain control/status register */ +#define CLOCKING_PLLPGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC00UL)) /* Platform PLL general status register */ +#define CLOCKING_PLLDGSR ((volatile uint32_t*)(CLOCKING_BASE + 0xC20UL)) /* DDR PLL general status register */ + +#define CLKC0CSR_CLKSEL(n) (((n) >> 27) & 0xF) /* 0000=Cluster PLL1 Output, 0001=Cluster PKK1 divide-by-2 */ +#define PLLCGSR_CGF(n) (((n) >> 1) & 0x3F) /* Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL */ #define RCPM_BASE (CCSRBAR + 0xE2000) #define RCPM_PCTBENR ((volatile uint32_t*)(RCPM_BASE + 0x1A0)) /* Physical Core Time Base Enable Bit 0=Core 0 */ @@ -749,17 +757,26 @@ enum ifc_amask_sizes { #ifdef ENABLE_BUS_CLK_CALC +static uint32_t hal_get_core_clk(void) +{ + /* compute core clock (system input * ratio) */ + uint32_t core_clk; + uint32_t core_ratio = get32(CLOCKING_PLLCNGSR(0)); /* see CGA_PLL1_RAT in RCW */ + /* shift by 1 and mask */ + core_ratio = ((core_ratio >> 1) & 0x3F); + core_clk = SYS_CLK * core_ratio; + return core_clk; +} static uint32_t hal_get_plat_clk(void) { - /* compute platform clock (system input * ratio) */ + /* compute core clock (system input * ratio) */ uint32_t plat_clk; uint32_t plat_ratio = get32(CLOCKING_PLLPGSR); /* see SYS_PLL_RAT in RCW */ - /* mask and shift by 1 to get platform ratio */ - plat_ratio = ((plat_ratio & 0x3E) >> 1); /* default is 4 (4:1) */ + /* shift by 1 and mask */ + plat_ratio = ((plat_ratio >> 1) & 0x1F); plat_clk = SYS_CLK * plat_ratio; return plat_clk; } - static uint32_t hal_get_bus_clk(void) { /* compute bus clock (platform clock / 2) */ @@ -767,8 +784,9 @@ static uint32_t hal_get_bus_clk(void) return bus_clk; } #else +#define hal_get_core_clk() (uint32_t)(SYS_CLK * 14) #define hal_get_plat_clk() (uint32_t)(SYS_CLK * 4) -#define hal_get_bus_clk() (uint32_t)(hal_get_plat_clk() / 2) +#define hal_get_bus_clk() (uint32_t)(hal_get_plat_clk() / 2) #endif #define TIMEBASE_CLK_DIV 16 @@ -2319,7 +2337,7 @@ int hal_dts_fixup(void* dts_addr) fdt_fixup_val64(fdt, off, "cpu", "cpu-release-addr", core_spin_table); fdt_fixup_str(fdt, off, "cpu", "enable-method", "spin-table"); fdt_fixup_val(fdt, off, "cpu", "timebase-frequency", TIMEBASE_HZ); - fdt_fixup_val(fdt, off, "cpu", "clock-frequency", hal_get_plat_clk()); + fdt_fixup_val(fdt, off, "cpu", "clock-frequency", hal_get_core_clk()); fdt_fixup_val(fdt, off, "cpu", "bus-frequency", hal_get_plat_clk()); off = fdt_find_devtype(fdt, off, "cpu"); From aa9e274480c97f17e1b0347c489f4ff73706e391 Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 6 Feb 2024 14:17:02 -0800 Subject: [PATCH 08/11] Adjust NXP T1024 flash layout, so existing device tree location does not have to move. --- config/examples/nxp-t1024.config | 10 +++++----- docs/Targets.md | 16 +++++++++------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/config/examples/nxp-t1024.config b/config/examples/nxp-t1024.config index 895f9f5b7..8cbd03389 100644 --- a/config/examples/nxp-t1024.config +++ b/config/examples/nxp-t1024.config @@ -37,15 +37,15 @@ WOLFBOOT_ORIGIN=0xEFF40000 # wolfBoot partition size (custom) BOOTLOADER_PARTITION_SIZE=0xC0000 -# Application Partition Size -WOLFBOOT_PARTITION_SIZE?=0x01E00000 +# Application Partition Size (15MB) +WOLFBOOT_PARTITION_SIZE?=0xF00000 # Location in Flash for Application Partition WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEE000000 # Load Partition to RAM Address WOLFBOOT_LOAD_ADDRESS?=0x70000000 # Location in Flash for Update Partition -WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEC200000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEEF00000 # Location of temporary sector used during updates WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEC0F0000 @@ -58,8 +58,8 @@ WOLFBOOT_STAGE1_FLASH_ADDR=0xEFFFC000 WOLFBOOT_STAGE1_LOAD_ADDR=0x7FF00000 # DTS (Device Tree) -WOLFBOOT_DTS_BOOT_ADDRESS?=0xEC020000 -WOLFBOOT_DTS_UPDATE_ADDRESS?=0xEC040000 +WOLFBOOT_DTS_BOOT_ADDRESS?=0xEC800000 +WOLFBOOT_DTS_UPDATE_ADDRESS?=0xEC820000 # DTS Load to RAM Address WOLFBOOT_LOAD_DTS_ADDRESS?=0x7F100000 diff --git a/docs/Targets.md b/docs/Targets.md index b8ec9066e..0374254e9 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -1375,14 +1375,16 @@ Default NOR Flash Memory Layout (64MB) (128KB block, 1K page) | Description | Address | Size | | ----------------- | ---------- | ------------------- | | RCW | 0xEC000000 | 0x00020000 (128 KB) | -| Primary (FDT) | 0xEC020000 | 0x00020000 (128 KB) | -| Update (FDT) | 0xEC040000 | 0x00020000 (128 KB) | -| Free | 0xEC060000 | 0x00090000 (576 KB) | +| Free | 0xEC020000 | 0x000D0000 (832 KB) | | Swap Sector | 0xEC0F0000 | 0x00010000 ( 64 KB) | -| Free | 0xEC100000 | 0x00100000 ( 1 MB) | -| Update (OS) | 0xEC200000 | 0x01E00000 ( 30 MB) | -| Ethenet Config | 0xED0E0000 | 0x00000400 ( 1 KB) | -| Application (OS) | 0xEE000000 | 0x01E00000 ( 30 MB) | +| Free | 0xEC100000 | 0x00700000 ( 7 MB) | +| FDT (Primary) | 0xEC800000 | 0x00020000 (128 KB) | +| FDT (Update) | 0xEC820000 | 0x00020000 (128 KB) | +| Free | 0xEC840000 | 0x008A0000 ( 8MB) | +| Ethenet Config | 0xED0E0000 | 0x00000400 ( 1 KB) | +| Free | 0xED100000 | 0x00F00000 ( 15 MB) | +| Application (OS) | 0xEE000000 | 0x00F00000 ( 15 MB) | +| Update (OS) | 0xEEF00000 | 0x00F00000 ( 15 MB) | | QUICC | 0xEFE00000 | 0x00100000 ( 1 MB) | | DPAA (FMAN) | 0xEFF00000 | 0x00020000 (128 KB) | | wolfBoot | 0xEFF40000 | 0x000BC000 (752 KB) | From 9dcd7b08a2b3c1b047b4d50556660e1c9d881805 Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 6 Feb 2024 15:51:15 -0800 Subject: [PATCH 09/11] Fix for eSDHC to update FDT with status and clock. Fix eSPI base address. --- hal/nxp_t1024.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 3ba949179..f8704d2a5 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -708,6 +708,9 @@ enum ifc_amask_sizes { #define MRAM_BASE 0xFF800000 #define MRAM_BASE_PHYS_HIGH 0xFULL +/* eSDHC */ +#define ESDHC_BASE (CCSRBAR + 0x114000) + /* eSPI */ @@ -715,7 +718,7 @@ enum ifc_amask_sizes { #define ESPI_MAX_RX_LEN (1 << 16) #define ESPI_FIFO_WORD 4 -#define ESPI_BASE (CCSRBAR + 0x7000) +#define ESPI_BASE (CCSRBAR + 0x110000) #define ESPI_SPMODE ((volatile uint32_t*)(ESPI_BASE + 0x00)) /* controls eSPI general operation mode */ #define ESPI_SPIE ((volatile uint32_t*)(ESPI_BASE + 0x04)) /* controls interrupts and report events */ #define ESPI_SPIM ((volatile uint32_t*)(ESPI_BASE + 0x08)) /* enables/masks interrupts */ @@ -1432,7 +1435,7 @@ static int hal_pcie_init(void) /* TODO: Check if link is active. Read config PCI_LTSSM */ #if 0 link = pci_config_read16(0, 0, 0, PCI_LTSSM); - enabled = (link >= PCI_LTSSM_L0); + enabled = (link >= PCI_LTSSM_L0); #endif } @@ -2487,6 +2490,14 @@ int hal_dts_fixup(void* dts_addr) fdt_setprop(fdt, off, "bus-range", bus_range, sizeof(bus_range)); } } + + /* fix SDHC */ + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,esdhc"); + if (off != !FDT_ERR_NOTFOUND) { + fdt_fixup_val(fdt, off, "sdhc@", "clock-frequency", hal_get_bus_clk()); + fdt_fixup_str(fdt, off, "cpu", "status", "okay"); + } + #endif /* !BUILD_LOADER_STAGE1 */ (void)dts_addr; return 0; From bed1e7df8f3caeb35afa09824d7e696335ce2cd6 Mon Sep 17 00:00:00 2001 From: David Garske Date: Thu, 8 Feb 2024 16:23:12 -0800 Subject: [PATCH 10/11] Added NXP T1024 mEMAC, MDIO and PHY setup. Setting PHY fixes Integrity OS Ethernet issues and task crash. Example Output: ``` PHY 2: SGMII, Mac DC:A7:D9:0:6:F6 PHY 2: TI DP83867 (OUI 80028, Mdl 23, Rev 1) PHY 1: SGMII, Mac DC:A7:D9:0:6:F5 PHY 1: TI DP83867 (OUI 80028, Mdl 23, Rev 1) PHY 3: RGMII, Mac DC:A7:D9:0:6:F7 PHY 3: TI DP83867 (OUI 80028, Mdl 23, Rev 1) PHY 4: RGMII, Mac DC:A7:D9:0:6:F8 PHY 4: TI DP83867 (OUI 80028, Mdl 23, Rev 1) ``` --- hal/nxp_t1024.c | 676 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 665 insertions(+), 11 deletions(-) diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index f8704d2a5..557a253a8 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -34,6 +34,7 @@ /* Debugging */ /* #define DEBUG_FLASH */ /* #define DEBUG_ESPI 1 */ +/* #define DEBUG_PHY */ #define ENABLE_IFC #define ENABLE_BUS_CLK_CALC @@ -50,6 +51,7 @@ #define ENABLE_CPLD #define ENABLE_QE /* QUICC Engine */ #define ENABLE_FMAN + #define ENABLE_PHY #define ENABLE_MRAM #if defined(WOLFBOOT_TPM) || defined(TEST_TPM) @@ -185,8 +187,10 @@ static void hal_flash_unlock_sector(uint32_t sector); #define QCSP_ISDR(n) ((volatile uint32_t*)(QMAN_BASE_PHYS + 0x1000E08 + ((n) * 0x1000))) /* SCGG (Supplemental Configuration Unit) T1024RM 6.1 */ -#define SCFG_BASE (CCSRBAR + 0xFC000) -#define SCFG_QEIOCLKCR ((volatile uint32_t*)(DCFG_BASE + 0x400UL)) +#define SCFG_BASE (CCSRBAR + 0xFC000) +#define SCFG_QEIOCLKCR ((volatile uint32_t*)(DCFG_BASE + 0x400UL)) +#define SCFG_EMIIOCR ((volatile uint32_t*)(DCFG_BASE + 0x404UL)) +#define SCFG_SDHCIOVSEL ((volatile uint32_t*)(DCFG_BASE + 0x408UL)) #define SCFG_QEIOCLKCR_CLK11 0x04000000 /* IO_CLK[11] = GPIO_4[16] */ @@ -367,6 +371,64 @@ static void hal_flash_unlock_sector(uint32_t sector); #define FMAN_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ #define FMAN_IRAM_READY 0x80000000 +/* mEMAC (Multirate Ethernet Media Access Controller) 1-4 */ +#define FMAN_MEMAC_BASE(n) (FMAN_BASE + 0xE0000UL + (((n-1) & 0x3) * 0x2000)) +#define FMAN_MEMAC_CMD_CFG(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x008)) +#define FMAN_MEMAC_MAC_ADDR_0(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x00C)) +#define FMAN_MEMAC_MAC_ADDR_1(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x010)) +#define FMAN_MEMAC_MAXFRMG(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x014)) +#define FMAN_MEMAC_HTBLE_CTRL(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x02C)) +#define FMAN_MEMAC_IEVENT(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x040)) +#define FMAN_MEMAC_IMASK(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x04C)) + +#define FMAN_MEMAC_IF_MODE(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x300)) +#define FMAN_MEMAC_IF_STATUS(n) ((volatile uint32_t*)(FMAN_MEMAC_BASE(n) + 0x304)) + +/* FMAN_MEMAC_CMD_CFG - Command and configuration register */ +#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC RX path enable */ +#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC TX path enable */ +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x00020000 /* Payload length check disable */ + +/* FMAN_MEMAC_IF_MODE - Interface Mode Register */ +#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ +#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */ +#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */ +#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */ +#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */ +#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ +#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ +#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ +#define IF_MODE_RG 0x00000004 /* 1- RGMII */ +#define IF_MODE_RM 0x00000008 /* 1- RGMII */ + +/* Dedicated MDIO EM1/EM2 Interface for PHY configurion */ +#define FMAC_MDIO_BASE(n) (FMAN_BASE + 0xFC000UL + (((n-1) & 0x1) * 0x1000)) +#define FMAN_MDIO_CFG(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x030)) +#define FMAN_MDIO_CTRL(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x034)) +#define FMAN_MDIO_DATA(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x038)) +#define FMAN_MDIO_ADDR(n) ((volatile uint32_t*)(FMAC_MDIO_BASE(n) + 0x03C)) + +#define MDIO_STAT_CLKDIV(x) ((((x)>>1) & 0xFF) << 8) /* valid range 5-511: ratio = (2 * CLKDIV) + 1 */ +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_STAT_PRE (1 << 5) +#define MDIO_STAT_EN_C45 (1 << 6) /* Enable Clause 45 support. */ +#define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) /* MDIO is driven by master on MDC negative edge */ + +#define MDIO_CTL_DEV_ADDR(x) ( (x) & 0x1F) +#define MDIO_CTL_PORT_ADDR(x) (((x) & 0x1F) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_ADDR(x) ((x) & 0xFFFF) + +#define MDIO_DATA(x) ((x) & 0xFFFF) +#define MDIO_DATA_BSY (1UL << 31) + + /* T1024 PC16552D Dual UART */ #define BAUD_RATE 115200 @@ -1907,7 +1969,6 @@ static void fman_upload_microcode(const struct qe_firmware *firmware, /* Enable microcode */ set32(FMAN_IRAM_IREADY, FMAN_IRAM_READY); - } /* Upload a microcode to the I-RAM at a specific address */ @@ -1929,6 +1990,596 @@ static int fman_upload_firmware(const struct qe_firmware *firmware) return 0; } +/* ----------- PHY ----------- */ +#ifdef ENABLE_PHY +/* TI DP83867 */ +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xA +#define DP83867_RGMIIDCTL_3_00_NS 0xB +#define DP83867_RGMIIDCTL_3_25_NS 0xC +#define DP83867_RGMIIDCTL_3_50_NS 0xD +#define DP83867_RGMIIDCTL_3_75_NS 0xE +#define DP83867_RGMIIDCTL_4_00_NS 0xF + +#define DP83867_DEVADDR 0x1F + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define MII_DP83867_CFG2 0x14 +#define MII_DP83867_BISCR 0x16 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 +#define DP83867_IO_MUX_CFG 0x0170 + +#define DP83867_SW_RESET (1 << 15) +#define DP83867_SW_RESTART (1 << 14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN (1 << 15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN (1 << 14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN (1 << 13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN (1 << 12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN (1 << 11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN (1 << 10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN (1 << 8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN (1 << 4) +#define MII_DP83867_MICR_WOL_INT_EN (1 << 3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN (1 << 2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN (1 << 1) +#define MII_DP83867_MICR_JABBER_INT_EN (1 << 0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN (1 << 1) +#define DP83867_RGMII_RX_CLK_DELAY_EN (1 << 0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_MDI_CROSSOVER 5 +#define DP83867_MDI_CROSSOVER_AUTO 2 +#define DP83867_MDI_CROSSOVER_MDIX 2 +#define DP83867_PHYCTRL_SGMIIEN 0x0800 +#define DP83867_PHYCTRL_RXFIFO_SHIFT 12 +#define DP83867_PHYCTRL_TXFIFO_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +/* CFG2 bits */ +#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040 +#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080 +#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100 +#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800 +#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000 +#define MII_DP83867_CFG2_MASK 0x003F + +#define MII_MMD_CTRL 0x0D /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0E /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1F /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/* User setting - can be taken from DTS */ +#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS +#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS +#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB + +/* IO_MUX_CFG bits */ +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1F + +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 +#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1F + +/* Generic MII registers */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYIDR1 0x02 /* PHYS ID 1 */ +#define MII_PHYIDR2 0x03 /* PHYS ID 2 */ + +/* Basic mode control register */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + + +enum phy_interface { + PHY_INTERFACE_MODE_NONE, + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_SGMII_2500, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, +}; + +/* TODO: Ethenet MAC should be dynamic value */ +static const uint8_t DEFAULT_MAC_ADDR[6] = {0xDC, 0xA7, 0xD9, 0x00, 0x06, 0xF4}; + +struct phy_device { + uint8_t phyaddr; + enum phy_interface interface; + uint8_t mac_addr[6]; +}; +static struct phy_device phydevs[5]; + +#define MDIO_PRTAD_NONE (-1) +#define MDIO_DEVAD_NONE (-1) + +/* Use EMI1 */ +#define MDIO_PHY_EMI 1 + +/* IEEE 802.3: Clause 45 (XFI/1000Base-KX) and Clause 22 (SGMII, QSGMII) */ +static int hal_phy_write(struct phy_device *phydev, int dev_addr, int regnum, + uint16_t value) +{ + uint32_t reg, clause = 45; + +#ifdef DEBUG_PHY + wolfBoot_printf("EM%d MDIO%d Write: Dev %d, Reg %d, Val 0x%x\n", + MDIO_PHY_EMI, phydev->phyaddr, dev_addr, regnum, value); +#endif + + reg = get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)); + if (dev_addr == MDIO_DEVAD_NONE) { + clause = 22; + dev_addr = regnum; + set32(FMAN_MDIO_CFG(MDIO_PHY_EMI), reg &= ~MDIO_STAT_EN_C45); + } + else { + set32(FMAN_MDIO_CFG(MDIO_PHY_EMI), reg |= MDIO_STAT_EN_C45); + } + /* Wait till bus is available */ + while (get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)) & MDIO_STAT_BSY); + + /* Set the port and dev addresses */ + reg = MDIO_CTL_PORT_ADDR(phydev->phyaddr) | MDIO_CTL_DEV_ADDR(dev_addr); + set32(FMAN_MDIO_CTRL(MDIO_PHY_EMI), reg); + + /* Set register address */ + if (clause == 45) { + set32(FMAN_MDIO_ADDR(MDIO_PHY_EMI), MDIO_ADDR(regnum)); + } + + /* Wait till bus is available */ + while (get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)) & MDIO_STAT_BSY); + + /* Write value */ + set32(FMAN_MDIO_DATA(MDIO_PHY_EMI), MDIO_DATA(value)); + + /* Wait till write is complete */ + while (get32(FMAN_MDIO_DATA(MDIO_PHY_EMI)) & MDIO_DATA_BSY); + + return 0; +} + +static int hal_phy_read(struct phy_device *phydev, int dev_addr, int regnum) +{ + uint32_t reg, clause = 45, mdio_dev_addr = dev_addr; + + reg = get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)); + if (dev_addr == MDIO_DEVAD_NONE) { + clause = 22; + mdio_dev_addr = regnum; + set32(FMAN_MDIO_CFG(MDIO_PHY_EMI), reg &= ~MDIO_STAT_EN_C45); + } + else { + set32(FMAN_MDIO_CFG(MDIO_PHY_EMI), reg |= MDIO_STAT_EN_C45); + } + /* Wait till bus is available */ + while (get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)) & MDIO_STAT_BSY); + + /* Set the port and dev addresses */ + reg = MDIO_CTL_PORT_ADDR(phydev->phyaddr) | MDIO_CTL_DEV_ADDR(mdio_dev_addr); + set32(FMAN_MDIO_CTRL(MDIO_PHY_EMI), reg); + + /* Set register address */ + if (clause == 45) { + set32(FMAN_MDIO_ADDR(MDIO_PHY_EMI), MDIO_ADDR(regnum)); + } + + /* Wait till bus is available */ + while (get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)) & MDIO_STAT_BSY); + + /* Start read */ + reg |= MDIO_CTL_READ; + set32(FMAN_MDIO_CTRL(MDIO_PHY_EMI), reg); + + /* Wait till read is complete */ + while (get32(FMAN_MDIO_DATA(MDIO_PHY_EMI)) & MDIO_DATA_BSY); + + /* Check for error */ + reg = get32(FMAN_MDIO_CFG(MDIO_PHY_EMI)); + if (reg & MDIO_STAT_RD_ER) { + return 0xFFFF; /* Failure */ + } + + /* Get data */ + reg = get32(FMAN_MDIO_DATA(MDIO_PHY_EMI)); + +#ifdef DEBUG_PHY + wolfBoot_printf("EM%d MDIO%d Read: Dev %d, Reg %d, Val 0x%x\n", + MDIO_PHY_EMI, phydev->phyaddr, dev_addr, regnum, MDIO_DATA(reg)); +#endif + + return MDIO_DATA(reg); +} + +static inline int phy_interface_is_rgmii(struct phy_device *phydev) +{ + return (phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID); +} + +static inline int phy_interface_is_sgmii(struct phy_device *phydev) +{ + return (phydev->interface >= PHY_INTERFACE_MODE_SGMII && + phydev->interface <= PHY_INTERFACE_MODE_QSGMII); +} + +int hal_phy_read_indirect(struct phy_device *phydev, + int port_addr, int dev_addr) +{ + uint16_t value = -1; + + /* Write the desired MMD Devad */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, DP83867_DEVADDR); + + /* Write the desired MMD register address */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, port_addr); + + /* Select the Function : DATA with no post increment */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, + (DP83867_DEVADDR | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); + +#ifdef DEBUG_PHY + wolfBoot_printf("PHY Ind Read: port_addr=%d, dev_addr=%d, value=0x%x\n", + port_addr, dev_addr, value); +#endif + return value; +} + +void hal_phy_write_indirect(struct phy_device *phydev, + int port_addr, int dev_addr, uint16_t value) +{ + /* Write the desired MMD Devad */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, dev_addr); + + /* Write the desired MMD register address */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, port_addr); + + /* Select the Function : DATA with no post increment */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, + (dev_addr | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, value); + +#ifdef DEBUG_PHY + wolfBoot_printf("PHY Ind Write: port_addr=%d, dev_addr=%d, value=0x%x\n", + port_addr, dev_addr, value); +#endif +} + +static const char* hal_phy_interface_str(enum phy_interface interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + return "RGMII"; + case PHY_INTERFACE_MODE_XGMII: + return "XGMII"; + case PHY_INTERFACE_MODE_SGMII: + return "SGMII"; + default: + break; + } + return "Unknown"; +} + +static const char* hal_phy_vendor_str(uint32_t id) +{ + switch (id) { + case 0x2000a231: + return "TI DP83867"; + default: + break; + } + return "Unknown"; +} + +/* Support for TI DP83867IS */ +static int hal_phy_init(struct phy_device *phydev) +{ + int ret = 0; + uint32_t val, val2; + + /* Set MAC address */ + /* Example MAC 0x12345678ABCD is: + * MAC_ADDR0 of 0x78563412 + * MAC_ADDR1 of 0x0000CDAB */ + memcpy(phydev->mac_addr, DEFAULT_MAC_ADDR, sizeof(DEFAULT_MAC_ADDR)); + phydev->mac_addr[5] += phydev->phyaddr; + + wolfBoot_printf("PHY %d: %s, Mac %x:%x:%x:%x:%x:%x\n", + phydev->phyaddr, hal_phy_interface_str(phydev->interface), + phydev->mac_addr[0], phydev->mac_addr[1], + phydev->mac_addr[2], phydev->mac_addr[3], + phydev->mac_addr[4], phydev->mac_addr[5]); + + /* Mask all interrupt */ + set32(FMAN_MEMAC_IMASK(phydev->phyaddr), 0x00000000); + + /* Clear all events */ + set32(FMAN_MEMAC_IEVENT(phydev->phyaddr), 0xFFFFFFFF); + + /* Set maximum RX length */ + set32(FMAN_MEMAC_MAXFRMG(phydev->phyaddr), 0x800); + + /* Disable multi-cast */ + set32(FMAN_MEMAC_HTBLE_CTRL(phydev->phyaddr), 0); + + /* Setup mEMAC */ + val = (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); + set32(FMAN_MEMAC_CMD_CFG(phydev->phyaddr), val); + + /* Set MAC Addresss */ + val = ((phydev->mac_addr[3] << 24) | (phydev->mac_addr[2] << 16) | \ + (phydev->mac_addr[1] << 8) | phydev->mac_addr[0]); + val2 = ((phydev->mac_addr[5] << 8) | phydev->mac_addr[4]); + set32(FMAN_MEMAC_MAC_ADDR_0(phydev->phyaddr), val); + set32(FMAN_MEMAC_MAC_ADDR_1(phydev->phyaddr), val2); + + /* Set interface mode */ + val = get32(FMAN_MEMAC_IF_MODE(phydev->phyaddr)); + switch (phydev->interface) { + case PHY_INTERFACE_MODE_GMII: + val &= ~IF_MODE_MASK; + val |= IF_MODE_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + val |= (IF_MODE_GMII | IF_MODE_RG); + break; + case PHY_INTERFACE_MODE_RMII: + val |= (IF_MODE_GMII | IF_MODE_RM); + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + val &= ~IF_MODE_MASK; + val |= IF_MODE_GMII; + break; + case PHY_INTERFACE_MODE_XGMII: + val &= ~IF_MODE_MASK; + val |= IF_MODE_XGMII; + break; + default: + break; + } + /* Enable automatic speed selection */ + val |= IF_MODE_EN_AUTO; + set32(FMAN_MEMAC_IF_MODE(phydev->phyaddr), val); + + /* Set clock div = 258 and neg = 1 */ + set32(FMAN_MDIO_CFG(MDIO_PHY_EMI), (MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG)); + + /* Read the PHY ID's */ + val = (uint16_t)hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYIDR1); + val <<= 16; + val |= (uint16_t)hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYIDR2); + //0x2000a231 + wolfBoot_printf("PHY %d: %s (OUI %x, Mdl %x, Rev %x)\n", + phydev->phyaddr, hal_phy_vendor_str(val), + (val >> 10), ((val >> 4) & 0x3F), (val & 0xF) + ); + + /* Reset the PHY */ + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + val |= DP83867_SW_RESTART; + hal_phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, val); + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); +#ifdef DEBUG_PHY + wolfBoot_printf("DP83867_CTRL=0x%x\n", val); +#endif + + if (phy_interface_is_rgmii(phydev)) { + val = ((DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | + (DP83867_PHYCR_FIFO_DEPTH_4_B_NIB << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + ret = hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val); + #ifdef DEBUG_PHY + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL); + wolfBoot_printf("MII_DP83867_PHYCTRL=0x%x\n", val); + #endif + } + else if (phy_interface_is_sgmii(phydev)) { + val = (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000); + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, val); + #ifdef DEBUG_PHY + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + wolfBoot_printf("MII_BMCR=0x%x\n", val); + #endif + + val = hal_phy_read(phydev, phydev->phyaddr, MII_DP83867_CFG2); + val &= MII_DP83867_CFG2_MASK; + val |= (MII_DP83867_CFG2_SPEEDOPT_10EN | + MII_DP83867_CFG2_SGMII_AUTONEGEN | + MII_DP83867_CFG2_SPEEDOPT_ENH | + MII_DP83867_CFG2_SPEEDOPT_CNT | + MII_DP83867_CFG2_SPEEDOPT_INTLOW); + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, val); + #ifdef DEBUG_PHY + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2); + wolfBoot_printf("MII_DP83867_CFG2=0x%x\n", val); + #endif + hal_phy_write_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, 0x0); + val = (DP83867_PHYCTRL_SGMIIEN | + (DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER) | + (DP83867_PHYCR_FIFO_DEPTH_4_B_NIB << DP83867_PHYCTRL_RXFIFO_SHIFT) | + (DP83867_PHYCR_FIFO_DEPTH_4_B_NIB << DP83867_PHYCTRL_TXFIFO_SHIFT)); + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val); + #ifdef DEBUG_PHY + val = hal_phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL); + wolfBoot_printf("MII_DP83867_PHYCTRL=0x%x\n", val); + #endif + hal_phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); + } + + if (ret == 0 && phy_interface_is_rgmii(phydev)) { + val = hal_phy_read_indirect(phydev, DP83867_RGMIICTL, MDIO_DEVAD_NONE); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + } + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + } + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + } + hal_phy_write_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, val); + #ifdef DEBUG_PHY + val = hal_phy_read_indirect(phydev, DP83867_RGMIICTL, MDIO_DEVAD_NONE); + wolfBoot_printf("DP83867_RGMIICTL=0x%x\n", val); + #endif + + val = (DP83867_RGMIIDCTL_1_75_NS | + (DP83867_RGMIIDCTL_1_75_NS << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + hal_phy_write_indirect(phydev, DP83867_RGMIIDCTL, DP83867_DEVADDR, val); + #ifdef DEBUG_PHY + val = hal_phy_read_indirect(phydev, DP83867_RGMIIDCTL, MDIO_DEVAD_NONE); + wolfBoot_printf("RGMIIDCTL delay=0x%x\n", val); + #endif + +#if DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN >= 0 + #ifdef DEBUG_PHY + wolfBoot_printf("Impedance Match 0x%x\n", DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN); + #endif + #ifdef DEBUG_PHY + val = hal_phy_read_indirect(phydev, DP83867_IO_MUX_CFG, MDIO_DEVAD_NONE); + wolfBoot_printf("IOMUX (before)=0x%x\n", val); + #endif + + /* CLK_O_SEL=Channel D transmit clock, IO_IMPEDANCE_CTRL=0x1F (max) */ + val = 0x0B1F; + hal_phy_write_indirect(phydev, DP83867_IO_MUX_CFG, DP83867_DEVADDR, val); + #ifdef DEBUG_PHY + val = hal_phy_read_indirect(phydev, DP83867_IO_MUX_CFG, MDIO_DEVAD_NONE); + wolfBoot_printf("IOMUX (after)=%x\n", val); + #endif +#endif + } + return ret; +} + + +#define RGMII_PHY1_ADDR 0x4 +#define RGMII_PHY2_ADDR 0x3 +#define SGMII_PHY2_ADDR 0x1 +#define SGMII_PHY1_ADDR 0x2 +#define SGMII_AQR_PHY_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x1 + +#define FM1_DTSEC1 0 +#define FM1_DTSEC2 1 +#define FM1_DTSEC3 2 +#define FM1_DTSEC4 3 +#define FM1_10GEC1 4 + +static int hal_ethernet_init(void) +{ + int ret, i; + uint32_t reg; + + memset(phydevs, 0, sizeof(phydevs)); + + /* Set the on-board RGMII PHY addresses */ + phydevs[FM1_DTSEC4].interface = PHY_INTERFACE_MODE_RGMII; + phydevs[FM1_DTSEC4].phyaddr = RGMII_PHY1_ADDR; + phydevs[FM1_DTSEC3].interface = PHY_INTERFACE_MODE_RGMII; + phydevs[FM1_DTSEC3].phyaddr = RGMII_PHY2_ADDR; + + reg = get32(DCFG_RCWSR(4)); + reg = (reg & RCWSR4_SRDS1_PRTCL) >> RCWSR4_SRDS1_PRTCL_SHIFT; + if (reg == 0x95) { + /* Use 10G XFI with Aquantia AQR105 PHY */ + phydevs[FM1_10GEC1].interface = PHY_INTERFACE_MODE_XGMII; + phydevs[FM1_10GEC1].phyaddr = FM1_10GEC1_PHY_ADDR; + } + else { /* 0x5b or 0x119 */ + /* Use SGMII */ + phydevs[FM1_DTSEC1].interface = PHY_INTERFACE_MODE_SGMII; + phydevs[FM1_DTSEC1].phyaddr = SGMII_PHY1_ADDR; + phydevs[FM1_DTSEC2].interface = PHY_INTERFACE_MODE_SGMII; + phydevs[FM1_DTSEC2].phyaddr = SGMII_PHY2_ADDR; + } + + /* Init PHY for each device */ + for (i=0; i<(int)(sizeof(phydevs)/sizeof(struct phy_device)); i++) { + if (phydevs[i].phyaddr != 0) { + ret = hal_phy_init(&phydevs[i]); + if (ret != 0) { + wolfBoot_printf("PHY %d: Failed! %d\n", phydevs[i].phyaddr, ret); + } + } + } + + return 0; +} +#endif /* ENABLE_PHY */ + #define FMAN_DMA_LIODN 973 static int hal_fman_init(void) @@ -1954,6 +2605,11 @@ static int hal_fman_init(void) ((FMAN_DMA_LIODN << 16) | FMAN_DMA_LIODN)); } } + +#ifdef ENABLE_PHY + hal_ethernet_init(); +#endif + return ret; } #endif /* ENABLE_FMAN */ @@ -2286,9 +2942,6 @@ int hal_dts_fixup(void* dts_addr) uint32_t *reg; const char* prev_compat; - /* TODO: Ethenet MAC should be dynamic value */ - uint8_t mac_addr[6] = {0xDC, 0xA7, 0xD9, 0x00, 0x07, 0x10}; - /* verify the FTD is valid */ off = fdt_check_header(dts_addr); if (off != 0) { @@ -2430,14 +3083,15 @@ int hal_dts_fixup(void* dts_addr) wolfBoot_printf("FDT: Ethernet%d: Offset %d\n", i, off); - /* Set Ethernet MAC addresses (incrementing) */ + /* Set Ethernet MAC addresses */ wolfBoot_printf("FDT: Set %s@%d (%d), %s=%x:%x:%x:%x:%x:%x\n", "ethernet", i, off, "local-mac-address", - mac_addr[0], mac_addr[1], mac_addr[2], - mac_addr[3], mac_addr[4], mac_addr[5]); - fdt_setprop(fdt, off, "local-mac-address", mac_addr, sizeof(mac_addr)); + phydevs[i].mac_addr[0], phydevs[i].mac_addr[1], + phydevs[i].mac_addr[2], phydevs[i].mac_addr[3], + phydevs[i].mac_addr[4], phydevs[i].mac_addr[5]); + fdt_setprop(fdt, off, "local-mac-address", + phydevs[i].mac_addr, sizeof(phydevs[i].mac_addr)); - mac_addr[5]++; off = fdt_node_offset_by_compatible(fdt, off, "fsl,fman-memac"); } From f7c1b71270497b320cdbd2c6ef2a07fc33a3c557 Mon Sep 17 00:00:00 2001 From: David Garske Date: Mon, 12 Feb 2024 09:56:56 -0800 Subject: [PATCH 11/11] Peer review feedback. --- docs/Targets.md | 2 +- hal/nxp_t1024.c | 16 ++++++++++------ src/pci.c | 7 +------ 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/docs/Targets.md b/docs/Targets.md index 0374254e9..0f2bc0b24 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -1907,7 +1907,7 @@ make # The next script needs to be run from wolboot root folder and assumes your # kernel is in th root folder, named bzImage # If this is not the case, change the path in the script accordingly -tools/x86_64/qemu/make_hd.sh +tools/x86_fsp/qemu/make_hd.sh # Run wolfBoot + Linux in qemu tools/scripts/qemu64/qemu64.sh diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 557a253a8..86b8ea698 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -2331,10 +2331,11 @@ static const char* hal_phy_interface_str(enum phy_interface interface) return "Unknown"; } +#define PHY_TIDP83867_PHYIDR 0x2000A231 static const char* hal_phy_vendor_str(uint32_t id) { switch (id) { - case 0x2000a231: + case PHY_TIDP83867_PHYIDR: return "TI DP83867"; default: break; @@ -2506,8 +2507,6 @@ static int hal_phy_init(struct phy_device *phydev) #if DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN >= 0 #ifdef DEBUG_PHY wolfBoot_printf("Impedance Match 0x%x\n", DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN); - #endif - #ifdef DEBUG_PHY val = hal_phy_read_indirect(phydev, DP83867_IO_MUX_CFG, MDIO_DEVAD_NONE); wolfBoot_printf("IOMUX (before)=0x%x\n", val); #endif @@ -2538,6 +2537,7 @@ static int hal_phy_init(struct phy_device *phydev) #define FM1_DTSEC4 3 #define FM1_10GEC1 4 + static int hal_ethernet_init(void) { int ret, i; @@ -2551,15 +2551,19 @@ static int hal_ethernet_init(void) phydevs[FM1_DTSEC3].interface = PHY_INTERFACE_MODE_RGMII; phydevs[FM1_DTSEC3].phyaddr = RGMII_PHY2_ADDR; + /* SRDS_PRTCL_S1 Bits 128-183 - SerDes protocol select - SerDes 1 */ + /* See T1024RM - 30.1.1.1.2 SerDes Protocols + * Figure 30-1 Supported SerDes Options */ reg = get32(DCFG_RCWSR(4)); reg = (reg & RCWSR4_SRDS1_PRTCL) >> RCWSR4_SRDS1_PRTCL_SHIFT; if (reg == 0x95) { - /* Use 10G XFI with Aquantia AQR105 PHY */ + /* 0x095: A=XFI1 10G Aquantia AQR105 PHY, B=PCIe3, C=PCIe2, D=PCIe1 */ phydevs[FM1_10GEC1].interface = PHY_INTERFACE_MODE_XGMII; phydevs[FM1_10GEC1].phyaddr = FM1_10GEC1_PHY_ADDR; } - else { /* 0x5b or 0x119 */ - /* Use SGMII */ + else { + /* 0x05B: A=PCIe1, B=PCIe3, C=SGMII2, D=SGMII1 */ + /* 0x119: A=Aurora, B=PCIe3, C=SGMII2, D=PCIe1 */ phydevs[FM1_DTSEC1].interface = PHY_INTERFACE_MODE_SGMII; phydevs[FM1_DTSEC1].phyaddr = SGMII_PHY1_ADDR; phydevs[FM1_DTSEC2].interface = PHY_INTERFACE_MODE_SGMII; diff --git a/src/pci.c b/src/pci.c index f39b7b0d4..8ee37fcab 100644 --- a/src/pci.c +++ b/src/pci.c @@ -541,12 +541,7 @@ static void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun) bus, dev, fun, (int)vid, (int)did); } #else -static inline void pci_dump_id(uint8_t bus, uint8_t dev, uint8_t fun) -{ - (void)bus; - (void)dev; - (void)fun; -}; +#define pci_dump_id(bus, dev, fun) do{}while(0) #endif static int pci_program_bars(uint8_t bus, uint8_t dev, uint8_t fun,