Analytical method for FPGA evaluation

[ketan170102030]

Hi Prof. Betz , Apart from using COFFE tool for evaluation of FPGA architecture, are there some analytical methods to determine area and delay numbers that we provide in VTR architecture description ? Can you provide some pointers or reference guide for them if such method exists ? Also is there any relation between height of block and area in MWTA that we specify in VTR architecture description ?