-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathfh101rf.yaml
1442 lines (1328 loc) · 35 KB
/
fh101rf.yaml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
---
name: FH101RF
author: "Jonah Imfeld, Silvano Cortesi"
notice: |
Licensed under LGPL-3.0
File Version: 1.0.1
defaults:
layout_bitwidth: 8
layouts:
BANDS:
bitwidth: 3
layout:
BAND_433:
bits: [0]
doc: True means on for 433MHz band.
accepts: !Bool
BAND_868:
bits: [1]
doc: True means on for 868/915MHz band.
accepts: !Bool
BAND_2G4:
bits: [2]
doc: True means on for 2.4GHz band.
accepts: !Bool
BRANCHES:
bitwidth: 3
layout:
WEAK:
bits: [0]
doc: True means weak branch on.
accepts: !Bool
MEDIUM:
bits: [1]
doc: True means medium branch on (+8dB of weak).
accepts: !Bool
STRONG:
bits: [2]
doc: True means strong branch on (+16dB of weak).
accepts: !Bool
IRQ_SOURCE:
bitwidth: 8
layout:
ID_MATCH:
bits: [0]
doc: The 16-bit ID in FDD mode matches (register ID_HI, ID_LO).
accepts: !Bool
FIFO_OVERFLOW:
bits: [1]
doc: FIFO overflow.
accepts: !Bool
FIFO_FULL:
bits: [2]
doc: FIFO buffer full.
accepts: !Bool
CORREL_MATCH:
bits: [3]
doc: OOK data matches the correlation sequence.
accepts: !Bool
ID_MATCH_AND_FIFO_FULL:
bits: [4]
doc: 16-bit ID in FDD mode matches and FIFO buffer full.
accepts: !Bool
ID_MATCH_AND_LDR:
bits: [5]
doc: 16-bit ID in FDD mode matches and LDR was entered.
accepts: !Bool
RTC_TIMER_ALARM:
bits: [6]
doc: RTC timer alarm.
accepts: !Bool
CYCLIC_TIMER_ALARM:
bits: [7]
doc: Cyclic timer alarm.
accepts: !Bool
RTC:
bitwidth: 4
layout:
RTCSH0:
bits: [0]
doc: Selects the short RTC counter #0 (RTCSH0).
accepts: !Bool
RTCSH1:
bits: [1]
doc: Selects the short RTC counter #1 (RTCSH1).
accepts: !Bool
RTCLG0:
bits: [2]
doc: Selects the long RTC counter #0 (RTCLG0).
accepts: !Bool
RTCLG1:
bits: [3]
doc: Selects the long RTC counter #1 (RTCLG1).
accepts: !Bool
enums:
SAMPLE_RATE:
enum:
SR_32_768:
val: 0x0
doc: 32768 Hz. 0.977ms code-sequence-duration.
SR_16_384:
val: 0x1
doc: 16384 Hz. 1.957ms code-sequence-duration.
SR_8_192:
val: 0x2
doc: 32768 Hz. 0.977ms code-sequence-duration.
SR_4_096:
val: 0x3
doc: 4096 Hz. 7.813ms code-sequence-duration.
SR_2_048:
val: 0x4
doc: 2048 Hz. 15.625ms code-sequence-duration.
SR_1_024:
val: 0x5
doc: 1024 Hz. 31.25ms code-sequence-duration.
SR_0_512:
val: 0x6
doc: 512 Hz. 62.5ms code-sequence-duration.
SR_0_256:
val: 0x7
doc: 256 Hz. 125ms code-sequence-duration.
FDD_MODE:
enum:
SLOW:
val: 0x0
doc: Slow mode.
FAST:
val: 0x1
doc: Fast mode.
EXIT_COND:
enum:
NO_REASON:
val: 0x0
doc: RX resetted or FDD is disabled - Initial state.
TIMEOUT:
val: 0x1
doc: Timeout - No fast code A or B received.
ID_FAIL:
val: 0x2
doc: ID match failed - 16-bit ID did not match.
FORCE_QUIT:
val: 0x3
doc: FO_QUIT was set - user forced slow mode.
FIFO_LEN:
enum:
BIT16:
val: 0x0
doc: 16-bit FIFO.
BIT24:
val: 0x1
doc: 24-bit FIFO.
BIT32:
val: 0x2
doc: 32-bit FIFO.
BIT40:
val: 0x3
doc: 40-bit FIFO.
BIN_CODE:
enum:
A:
val: 0
doc: mls A
B:
val: 1
doc: mls B
C:
val: 2
doc: mls C
D:
val: 3
doc: mls D
A_inv:
val: 4
doc: mls A inv
B_inv:
val: 5
doc: mls B inv
A_seq:
val: 6
doc: m-sequence A
B_seq:
val: 7
doc: m-sequence B
ZERO_31:
val: 8
doc: 31 zeros
ONE_8:
val: 9
doc: 8 ones
ONE_16:
val: 10
doc: 16 ones
ONE_24:
val: 11
doc: 24 ones
ONE_31:
val: 12
doc: 31 ones
ZOZO:
val: 13
doc: 0101 pattern
OOZZ:
val: 14
doc: 1100 pattern
OOOZZZ:
val: 15
doc: 111000 pattern
registers:
NFA433_SLOW: !Register
adr: 0x00
reset_val: 0x05
doc: Set the sample-rate for preamble-listening (LDR-mode with FDD/IDM enabled) or single-sequence wake-up (FDD disabled) in the 433-MHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
NFA433_FAST: !Register
adr: 0x01
reset_val: 0x00
doc: Set the sample-rate for FDD-mode data reception in the 433-MHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
NFA868_SLOW: !Register
adr: 0x02
reset_val: 0x05
doc: Set the sample-rate for preamble-listening (LDR-mode with FDD/IDM enabled) or single-sequence wake-up (FDD disabled) in the 868-MHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
NFA868_FAST: !Register
adr: 0x03
reset_val: 0x00
doc: Set the sample-rate for FDD-mode data reception in the 868-MHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
NFA2G4_SLOW: !Register
adr: 0x04
reset_val: 0x05
doc: Set the sample-rate for preamble-listening (LDR-mode with FDD/IDM enabled) or single-sequence wake-up (FDD disabled) in the 2.4-GHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
NFA2G4_FAST: !Register
adr: 0x05
reset_val: 0x00
doc: Set the sample-rate for FDD-mode data reception in the 2.4-GHz band.
layout: !Layout
DATA:
bits: [0-2]
access: [W]
accepts: !SharedEnum SAMPLE_RATE
CALIB_STATUS: !Register
adr: 0x06
reset_val: 0x00
doc: Indicates status of all calibration processes.
layout: !Layout
OFFSET_CAL_IN_PROG:
bits: [3]
access: [R]
doc: Indicates Offset calubration in progress.
accepts: !Bool
SPG_CAL_IN_PROG:
bits: [2]
access: [R]
doc: Indicates SPG calibration in progress.
accepts: !Bool
LCO_CAL_IN_PROG:
bits: [1]
access: [R]
doc: Indicates LCO calibration in progress.
accepts: !Bool
CAL_IN_PROG:
bits: [0]
access: [R]
doc: Indicates general calibration process in progress.
accepts: !Bool
CALIB_CTRL: !Register
adr: 0x07
reset_val: 0x0E
doc: Control register for starting calibration processes.
layout: !Layout
OFFSET_CAL:
bits: [3]
access: [R,W]
doc: Control bit for initiating offset calibration.
accepts: !Bool
SPG_CAL:
bits: [2]
access: [R,W]
doc: Control bit for initiating SPG calibration.
accepts: !Bool
LCO_CAL:
bits: [1]
access: [R,W]
doc: Control bit for initiating LCO calibration.
accepts: !Bool
CAL_START:
bits: [0]
access: [R,W]
doc: Starts the calibration process.
accepts: !Bool
N_SPG_TARGET: !Register
adr: 0x09
reset_val: 0x31
doc: Target register for the Signal Processing Gain setting. Set to 0x46 during SPG calibration.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_433_HI: !Register
adr: 0x0B
reset_val: 0x0E
doc: Sets the high byte (15:8) target freqency for the 433-MHz band. N_LCO_TARGET_<band> × 4 × 32,768 Hz; Values between 3304 and 3891. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_433_LO: !Register
adr: 0x0C
reset_val: 0x20
doc: Sets the low byte (7:0) target freqency for the 433-MHz band. N_LCO_TARGET_<band> × 4 × 32,768 Hz; Values between 3304 and 3891.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_868_HI: !Register
adr: 0x0D
reset_val: 0x0D
doc: Sets the high byte (15:8) target freqency for the 868/915-MHz band. N_LCO_TARGET_<band> × 8 × 32,768 Hz; Values between 3281 and 3738. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_868_LO: !Register
adr: 0x0E
reset_val: 0x87
doc: Sets the low byte (7:0) target freqency for the 868/915-MHz band. N_LCO_TARGET_<band> × 8 × 32,768 Hz; Values between 3281 and 3738.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_2G4_HI: !Register
adr: 0x0F
reset_val: 0x12
doc: Sets the high byte (15:8) target freqency for the 2.4-GHz band. N_LCO_TARGET_<band> × 16 × 32,768 Hz; Values between 4482 and 4833. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
N_LCO_TARGET_2G4_LO: !Register
adr: 0x10
reset_val: 0xCE
doc: Sets the low byte (7:0) target freqency for the 2.4-GHz band. N_LCO_TARGET_<band> × 16 × 32,768 Hz; Values between 4482 and 4833.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
LCO_FREQ_433_HI: !Register
adr: 0x14
reset_val: 0x00
doc: Holds the current frequency of the 433-MHz band, high byte (15:8). Read the registers in the given order from 0x14 to 0x19. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
LCO_FREQ_433_LO: !Register
adr: 0x15
reset_val: 0x00
doc: Holds the current frequency of the 433-MHz band, low byte (7:0). Read the registers in the given order from 0x14 to 0x19.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
LCO_FREQ_868_HI: !Register
adr: 0x16
reset_val: 0x00
doc: Holds the current frequency of the 868/915-MHz band, high byte (15:8). Read the registers in the given order from 0x14 to 0x19. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
LCO_FREQ_868_LO: !Register
adr: 0x17
reset_val: 0x00
doc: Holds the current frequency of the 868/915-MHz band, low byte (7:0). Read the registers in the given order from 0x14 to 0x19.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
LCO_FREQ_2G4_HI: !Register
adr: 0x18
reset_val: 0x00
doc: Holds the current frequency of the 2.4-GHz band, high byte (15:8). Read the registers in the given order from 0x14 to 0x19. (According to register table in DS v1.3b, only 12:8).
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
LCO_FREQ_2G4_LO: !Register
adr: 0x19
reset_val: 0x00
doc: Holds the current frequency of the 2.4-GHz band, low byte (7:0). Read the registers in the given order from 0x14 to 0x19.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
D_CORNER_CTRL: !Register
adr: 0x23
reset_val: 0x00
doc: Set to 0x02 at power-up.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
BAND_BRANCH_CTRL: !Register
adr: 0x24
reset_val: 0x77
doc: Selects the active bands and branches (RF-sensitivity).
layout: !Layout
ACTIVE_BRANCHES:
bits: [2-0]
access: [W]
doc: Selects the active detection branches.
accepts: !SharedLayout BRANCHES
ACTIVE_BANDS:
bits: [4-6]
access: [W]
doc: Selects the active bands.
accepts: !SharedLayout BANDS
CODE_SELECT: !Register
adr: 0x28
reset_val: 0x10
doc: Selects the correlation patterns for code A and B.
layout: !Layout
A:
bits: [0-3]
access: [W]
doc: Selects the correlation pattern for code A.
accepts: !SharedEnum BIN_CODE
B:
bits: [4-7]
access: [W]
doc: Selects the correlation pattern for code B.
accepts: !SharedEnum BIN_CODE
KORREL_THRESH_A: !Register
adr: 0x29
reset_val: 0x1A
doc: Sets the threshold for a code A match. Useful values are between 0x19 and 0x1E. Lower values correspond to more tolerated bit errors (can lead to false wake-up detections).
layout: !Layout
DATA:
bits: [0-4]
access: [R,W]
accepts: !UInt
KORREL_THRESH_B: !Register
adr: 0x2A
reset_val: 0x1A
doc: Sets the threshold for a code B match. Useful values are between 0x19 and 0x1E. Lower values correspond to more tolerated bit errors (can lead to false wake-up detections).
layout: !Layout
DATA:
bits: [0-4]
access: [R,W]
accepts: !UInt
KORREL_STATE: !Register
adr: 0x2B
reset_val: 0xC0
doc:
layout: !Layout
KORREL_BRANCHES_A:
bits: [0-2]
doc: Indicates receiver branch that had contributed for Code A recognition
access: [R]
accepts: !SharedLayout BRANCHES
KORREL_BRANCHES_B:
bits: [3-5]
doc: Indicates receiver branch that had contributed for Code B recognition
access: [R]
accepts: !SharedLayout BRANCHES
KORREL_BRANCHES_LATEST:
bits: [6-7]
doc: Indicates frequency band for latest correlator
access: [R]
accepts: !Enum
BAND_433:
doc: Band 433MHz matched.
val: 0x00
BAND_868:
doc: Band 868/915MHz matched.
val: 0x01
BAND_2G4:
doc: Band 2.4GHz matched.
val: 0x02
KORREL_VAL: !Register
adr: 0x2C
reset_val: 0x00
doc: Indicates the match level for code A and B. A value of 15 indicates no bit errors, a value of 0 indicates 15 bit errors.
layout: !Layout
A:
bits: [0-3]
doc: Indicates the match level for code A. Refreshed after a positive Code A match. Typically >5
access: [R]
accepts: !UInt
B:
bits: [4-7]
doc: Indicates the match level for code B. Refreshed after a positive Code B match. Typically >5
access: [R]
accepts: !UInt
FDD_ENABLE: !Register
adr: 0x2D
reset_val: 0x07
doc: Enable the fast data decoder for a given band.
layout: !Layout
FDD_BANDS:
bits: [0-2]
access: [W]
accepts: !SharedLayout BANDS
FDD_ACTIVE: !Register
adr: 0x2E
reset_val: 0x00
doc: Reads the FDD mode for each band.
layout: !Layout
BAND_2G4:
bits: [0]
access: [R]
accepts: !SharedEnum FDD_MODE
BAND_868:
bits: [1]
access: [R]
accepts: !SharedEnum FDD_MODE
BAND_433:
bits: [2]
access: [R]
accepts: !SharedEnum FDD_MODE
FO_QUIT: !Register
adr: 0x2F
reset_val: 0x00
doc: Forces the specified band to quit fast mode immediately.
layout: !Layout
QUIT_BANDS:
bits: [0-2]
access: [W]
accepts: !SharedLayout BANDS
FDD_EXIT_COND: !Register
adr: 0x30
reset_val: 0x00
doc: Holds the FDD exit condition for all the bands.
layout: !Layout
BAND_433:
bits: [0-1]
access: [R]
accepts: !SharedEnum EXIT_COND
BAND_868:
bits: [2-3]
access: [R]
accepts: !SharedEnum EXIT_COND
BAND_2G4:
bits: [4-5]
access: [R]
accepts: !SharedEnum EXIT_COND
IRQ_SELECT: !Register
adr: 0x31
reset_val: 0x01
doc: Selects the interrupt sources.
layout: !Layout
IRQ_SELECT:
bits: [0-7]
access: [W]
accepts: !SharedLayout IRQ_SOURCE
IRQ_STATUS: !Register
adr: 0x32
reset_val: 0x00
doc: Holds the status of the IRQ events.
layout: !Layout
IRQ_STATUS:
bits: [0-7]
access: [R]
accepts: !SharedLayout IRQ_SOURCE
IRQ_CLR: !Register
adr: 0x33
reset_val: 0x00
doc: Resets the corresponding IRQ event bit.
layout: !Layout
IRQ_CLR:
bits: [0-7]
access: [W]
accepts: !SharedLayout IRQ_SOURCE
IRQ_SET: !Register
adr: 0x34
reset_val: 0x00
doc: Sets the corresponding IRQ event bit (triggers IRQ events for debugging).
layout: !Layout
IRQ_SET:
bits: [0-7]
access: [W]
accepts: !SharedLayout IRQ_SOURCE
ID_HI: !Register
adr: 0x35
reset_val: 0x7D
doc: Sets the high byte of the match ID. 4-MSB form the group ID.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
ID_LO: !Register
adr: 0x36
reset_val: 0xA8
doc: Sets the low byte of the match ID.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
IDM_ENABLE: !Register
adr: 0x37
reset_val: 0x07
doc: Enables the ID match for a given band.
layout: !Layout
MATCH_BANDS:
bits: [0-2]
access: [W]
accepts: !SharedLayout BANDS
IDM_CTRL: !Register
adr: 0x38
reset_val: 0x00
doc: Slect the type of ID's accepted by the receiver.
layout: !Layout
CTRL:
bits: [0-1]
access: [W]
accepts: !Enum
IND_ONLY:
doc: only individual 16 bit ID.
val: 0x0
IND_GROUP:
doc: individual 16 bit ID or groupwise ID.
val: 0x1
BROAD_ONLY:
doc: only broadcast ID.
val: 0x2
IND_GROUP_BROAD:
doc: individual 16 bit ID, groupwise ID, or broadcast ID.
val: 0x3
IDM_CLR: !Register
adr: 0x39
reset_val: 0x00
doc: Clear the FDD_EXIT_COND register.
layout: !Layout
BRANCH:
bits: [0]
access: [W]
accepts: !Bool
IDM_BAND: !Register
adr: 0x3A
reset_val: 0x03
doc: Indicates the frequency band of the ID match event.
layout: !Layout
DATA:
bits: [0-1]
access: [R]
accepts: !Enum
BAND_433:
val: 0x0
BAND_868:
val: 0x1
BAND_2G4:
val: 0x2
IDM_REASON: !Register
adr: 0x3B
reset_val: 0x00
doc: Indicates the type of ID match event.
layout: !Layout
REASON:
bits: [0-1]
access: [R]
accepts: !Enum
UNKNOWN:
doc: Unspecified reason
val: 0x0
IND_MATCH:
doc: Individual ID
val: 0x1
GROUP_MATCH:
doc: Group ID
val: 0x2
BROAD_MATCH:
doc: Broadcast ID
val: 0x3
RTC_SELECT: !Register
adr: 0x3C
reset_val: 0x00
doc: Allows for selection of the desired timer modes.
layout: !Layout
RTC_SELECT:
bits: [0-3]
access: [W]
accepts: !SharedLayout RTC
CYCLTOP:
bits: [4]
access: [W]
doc: Selects the cyclic counter (CYCLTOP).
accepts: !Bool
RTC_STATUS: !Register
adr: 0x3D
reset_val: 0x00
doc: Indicates occurence of RTC events.
layout: !Layout
RTC_SELECT:
bits: [0-3]
access: [R]
accepts: !SharedLayout RTC
RTC_CLR: !Register
adr: 0x3E
reset_val: 0x00
doc: Clears the respective event entries in RTC_STATUS.
layout: !Layout
RTC_CLR:
bits: [0-3]
access: [W]
accepts: !SharedLayout RTC
RTCSH0_THRESH_HI: !Register
adr: 0x3F
reset_val: 0x00
doc: Upper (Bits 15:8) byte of the RTCSH0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCSH0_THRESH_LO: !Register
adr: 0x40
reset_val: 0x00
doc: Lower (Bits 7:0) byte of the RTCSH0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCSH1_THRESH_HI: !Register
adr: 0x41
reset_val: 0x00
doc: Upper (Bits 15:8) byte of the RTCSH1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCSH1_THRESH_LO: !Register
adr: 0x42
reset_val: 0x00
doc: Lower (Bits 7:0) byte of the RTCSH1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG0_THRESH_4: !Register
adr: 0x43
reset_val: 0x00
doc: Bits 39:32 of the RTCLG0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG0_THRESH_3: !Register
adr: 0x44
reset_val: 0x00
doc: Bits 31:24 of the RTCLG0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG0_THRESH_2: !Register
adr: 0x45
reset_val: 0x00
doc: Bits 23:16 of the RTCLG0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG0_THRESH_1: !Register
adr: 0x46
reset_val: 0x00
doc: Bits 15:8 of the RTCLG0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG0_THRESH_0: !Register
adr: 0x47
reset_val: 0x00
doc: Bits 7:0 of the RTCLG0 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG1_THRESH_4: !Register
adr: 0x48
reset_val: 0x00
doc: Bits 39:32 of the RTCLG1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG1_THRESH_3: !Register
adr: 0x49
reset_val: 0x00
doc: Bits 31:24 of the RTCLG1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG1_THRESH_2: !Register
adr: 0x4A
reset_val: 0x00
doc: Bits 23:16 of the RTCLG1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG1_THRESH_1: !Register
adr: 0x4B
reset_val: 0x00
doc: Bits 15:8 of the RTCLG1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
RTCLG1_THRESH_0: !Register
adr: 0x4C
reset_val: 0x00
doc: Bits 7:0 of the RTCLG1 threshold.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
CYCLPRESC: !Register
adr: 0x4D
reset_val: 0x00
doc: Cycle prescaler for cyclic counter, system clock divided by prescaler (therefore max 8:29.9922 minutes).
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
CYCLTOP_HI: !Register
adr: 0x4E
reset_val: 0x00
doc: Bits 15:8 defining the maximal cyclic counter value CYCLTOP before being reset to zero.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
CYCLTOP_LO: !Register
adr: 0x4F
reset_val: 0x00
doc: Bits 7:0 defining the maximal cyclic counter value CYCLTOP before being reset to zero.
layout: !Layout
DATA:
bits: [0-7]
access: [W]
accepts: !UInt
CNTR40_4: !Register
adr: 0x50
reset_val: 0x00
doc: Bits 39:32 of the system clock counter CNTR40.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
CNTR40_3: !Register
adr: 0x51
reset_val: 0x00
doc: Bits 31:24 of the system clock counter CNTR40.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
CNTR40_2: !Register
adr: 0x52
reset_val: 0x00
doc: Bits 23:16 of the system clock counter CNTR40.
layout: !Layout
DATA:
bits: [0-7]
access: [R]
accepts: !UInt
CNTR40_1: !Register
adr: 0x53