From fa6a57fa6a0eab3a7c55c46c31eaf9a0aa878ebd Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 19 Jul 2023 09:26:10 -0600 Subject: [PATCH] Enable power switch WDT on IT5570E boards Enable PWRSW WDT 2 and use the default timeout of 10 seconds. Allows forcing an EC reset in case it gets into an invalid state. Signed-off-by: Tim Crawford --- src/board/system76/addw2/gpio.c | 5 +++++ src/board/system76/addw3/gpio.c | 7 +++++-- src/board/system76/bonw14/gpio.c | 5 +++++ src/board/system76/bonw15/gpio.c | 7 +++++-- src/board/system76/darp7/gpio.c | 5 +++++ src/board/system76/darp8/gpio.c | 4 ++-- src/board/system76/galp5/gpio.c | 5 +++++ src/board/system76/galp6/gpio.c | 4 ++-- src/board/system76/gaze15/gpio.c | 5 +++++ src/board/system76/gaze16-3050/gpio.c | 5 +++++ src/board/system76/gaze16-3060/gpio.c | 5 +++++ src/board/system76/gaze17-3050/gpio.c | 5 +++++ src/board/system76/gaze17-3060/gpio.c | 5 +++++ src/board/system76/lemp10/gpio.c | 5 +++++ src/board/system76/lemp11/gpio.c | 4 ++-- src/board/system76/oryp11/gpio.c | 7 +++++-- src/board/system76/oryp6/gpio.c | 5 +++++ src/board/system76/oryp7/gpio.c | 5 +++++ src/board/system76/oryp8/gpio.c | 5 +++++ src/board/system76/oryp9/gpio.c | 4 ++-- 20 files changed, 88 insertions(+), 14 deletions(-) diff --git a/src/board/system76/addw2/gpio.c b/src/board/system76/addw2/gpio.c index b9a5171ca..57d2e5fac 100644 --- a/src/board/system76/addw2/gpio.c +++ b/src/board/system76/addw2/gpio.c @@ -43,6 +43,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/addw3/gpio.c b/src/board/system76/addw3/gpio.c index 581a42fcf..61b124c8c 100644 --- a/src/board/system76/addw3/gpio.c +++ b/src/board/system76/addw3/gpio.c @@ -35,6 +35,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs @@ -49,8 +54,6 @@ void gpio_init() { //TODO: what do these do? GCR1 = 0; GCR2 = 0; - GCR8 = 0x10; - GCR9 = 0x20; GCR10 = 0x02; GCR21 = 0; GCR22 = 0x80; diff --git a/src/board/system76/bonw14/gpio.c b/src/board/system76/bonw14/gpio.c index 523dad9ae..8665eb8d5 100644 --- a/src/board/system76/bonw14/gpio.c +++ b/src/board/system76/bonw14/gpio.c @@ -42,6 +42,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // renamed to EN_3V // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/bonw15/gpio.c b/src/board/system76/bonw15/gpio.c index befd4eec6..7e4339c3a 100644 --- a/src/board/system76/bonw15/gpio.c +++ b/src/board/system76/bonw15/gpio.c @@ -37,6 +37,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs @@ -51,8 +56,6 @@ void gpio_init() { //TODO: what do these do? GCR1 = 0; GCR2 = 0; - GCR8 = 0x10; - GCR9 = 0x20; GCR10 = 0x02; GCR21 = 0; GCR22 = 0x80; diff --git a/src/board/system76/darp7/gpio.c b/src/board/system76/darp7/gpio.c index 75c7c840f..50d01d760 100644 --- a/src/board/system76/darp7/gpio.c +++ b/src/board/system76/darp7/gpio.c @@ -43,6 +43,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/darp8/gpio.c b/src/board/system76/darp8/gpio.c index 4772bcee4..7571ded6d 100644 --- a/src/board/system76/darp8/gpio.c +++ b/src/board/system76/darp8/gpio.c @@ -41,9 +41,9 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); void gpio_init(void) { // PWRSW WDT 2 Enable 2 - //GCR9 = BIT(5); + GCR9 = BIT(5); // PWRSW WDT 2 Enable 1 - //GCR8 = BIT(4); + GCR8 = BIT(4); // Enable LPC reset on GPD2 GCR = 0b10 << 1; diff --git a/src/board/system76/galp5/gpio.c b/src/board/system76/galp5/gpio.c index de05d2d01..40f551333 100644 --- a/src/board/system76/galp5/gpio.c +++ b/src/board/system76/galp5/gpio.c @@ -44,6 +44,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/galp6/gpio.c b/src/board/system76/galp6/gpio.c index 817e587af..d90056d8f 100644 --- a/src/board/system76/galp6/gpio.c +++ b/src/board/system76/galp6/gpio.c @@ -43,9 +43,9 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); void gpio_init(void) { // PWRSW WDT 2 Enable 2 - //GCR9 = BIT(5); + GCR9 = BIT(5); // PWRSW WDT 2 Enable 1 - //GCR8 = BIT(4); + GCR8 = BIT(4); // Enable LPC reset on GPD2 GCR = 0b10 << 1; diff --git a/src/board/system76/gaze15/gpio.c b/src/board/system76/gaze15/gpio.c index 4ea9b770e..8ae48bf54 100644 --- a/src/board/system76/gaze15/gpio.c +++ b/src/board/system76/gaze15/gpio.c @@ -41,6 +41,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/gaze16-3050/gpio.c b/src/board/system76/gaze16-3050/gpio.c index 828c27c85..d80b00438 100644 --- a/src/board/system76/gaze16-3050/gpio.c +++ b/src/board/system76/gaze16-3050/gpio.c @@ -39,6 +39,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs diff --git a/src/board/system76/gaze16-3060/gpio.c b/src/board/system76/gaze16-3060/gpio.c index 9c665d058..a5e0d229c 100644 --- a/src/board/system76/gaze16-3060/gpio.c +++ b/src/board/system76/gaze16-3060/gpio.c @@ -40,6 +40,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs diff --git a/src/board/system76/gaze17-3050/gpio.c b/src/board/system76/gaze17-3050/gpio.c index 7d5cc5616..203d79ee7 100644 --- a/src/board/system76/gaze17-3050/gpio.c +++ b/src/board/system76/gaze17-3050/gpio.c @@ -39,6 +39,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs diff --git a/src/board/system76/gaze17-3060/gpio.c b/src/board/system76/gaze17-3060/gpio.c index ed30f2cfa..74dfcf684 100644 --- a/src/board/system76/gaze17-3060/gpio.c +++ b/src/board/system76/gaze17-3060/gpio.c @@ -39,6 +39,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs diff --git a/src/board/system76/lemp10/gpio.c b/src/board/system76/lemp10/gpio.c index 17cb04c64..387868a24 100644 --- a/src/board/system76/lemp10/gpio.c +++ b/src/board/system76/lemp10/gpio.c @@ -42,6 +42,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/lemp11/gpio.c b/src/board/system76/lemp11/gpio.c index e6ceba06f..99f743d28 100644 --- a/src/board/system76/lemp11/gpio.c +++ b/src/board/system76/lemp11/gpio.c @@ -43,9 +43,9 @@ void gpio_init(void) { //GCR22 = BIT(7); // PWRSW WDT 2 Enable 2 - //GCR9 = BIT(5); + GCR9 = BIT(5); // PWRSW WDT 2 Enable 1 - //GCR8 = BIT(4); + GCR8 = BIT(4); // Enable LPC reset on GPD2 GCR = 0b10 << 1; diff --git a/src/board/system76/oryp11/gpio.c b/src/board/system76/oryp11/gpio.c index 53089036f..89bfad2db 100644 --- a/src/board/system76/oryp11/gpio.c +++ b/src/board/system76/oryp11/gpio.c @@ -37,6 +37,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs @@ -51,8 +56,6 @@ void gpio_init() { //TODO: what do these do? GCR1 = 0; GCR2 = 0; - GCR8 = 0x10; - GCR9 = 0x20; GCR10 = 0x02; GCR21 = 0; GCR22 = 0x80; diff --git a/src/board/system76/oryp6/gpio.c b/src/board/system76/oryp6/gpio.c index ce9c99e40..37ef52431 100644 --- a/src/board/system76/oryp6/gpio.c +++ b/src/board/system76/oryp6/gpio.c @@ -41,6 +41,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/oryp7/gpio.c b/src/board/system76/oryp7/gpio.c index 10c9761a9..ac5462a47 100644 --- a/src/board/system76/oryp7/gpio.c +++ b/src/board/system76/oryp7/gpio.c @@ -40,6 +40,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Enable SMBus channel 4 diff --git a/src/board/system76/oryp8/gpio.c b/src/board/system76/oryp8/gpio.c index bb161469a..0e55d2869 100644 --- a/src/board/system76/oryp8/gpio.c +++ b/src/board/system76/oryp8/gpio.c @@ -38,6 +38,11 @@ struct Gpio __code XLP_OUT = GPIO(B, 4); // clang-format on void gpio_init() { + // PWRSW WDT 2 Enable 2 + GCR9 = BIT(5); + // PWRSW WDT 2 Enable 1 + GCR8 = BIT(4); + // Enable LPC reset on GPD2 GCR = 0x04; // Disable UARTs diff --git a/src/board/system76/oryp9/gpio.c b/src/board/system76/oryp9/gpio.c index 1e905abe7..94c8cf8d3 100644 --- a/src/board/system76/oryp9/gpio.c +++ b/src/board/system76/oryp9/gpio.c @@ -45,9 +45,9 @@ void gpio_init(void) { //GCR22 = BIT(7); // PWRSW WDT 2 Enable 2 - //GCR9 = BIT(5); + GCR9 = BIT(5); // PWRSW WDT 2 Enable 1 - //GCR8 = BIT(4); + GCR8 = BIT(4); // Enable LPC reset on GPD2 GCR = 0b10 << 1;