v1.8.9

What's Changed

• Update RTE to support easy emulation of instructions by @stnolting in #673
• ⚠️ constrain MTVAL CSR, add MTINST CSR by @stnolting in #674
• Add Smcntrpmf ISA extension by @stnolting in #676
• [OCD] add option to select DM legacy mode by @stnolting in #677
• [cpu] remove branch prediction logic by @stnolting in #678
• minor rtl edits and cleanups by @stnolting in #679
• [cpu] add execution monitor by @stnolting in #680
• [CFU] add support for CFU-internal CSRs by @stnolting in #681
• CPU hardware optimization by @stnolting in #683

Full Changelog: v1.8.8...v1.8.9

v1.8.8

What's Changed

• ⚠️ Remove CUSTOM_ID generic by @stnolting in #657
• 🐛 Make sure IMEM/DMEM sizes are a power of two by @stnolting in #658
• ⚠️ Rework SYSINFO module by @stnolting in #659
• [rtl] Cleanups and Optimizations by @stnolting in #660
• ⚠️ Major code edits / cleanups by @stnolting in #664
• [rtl] fix natural condition by @NikLeberg in #665
• minor cleanups by @stnolting in #669
• Remove Zicond ISA extension by @stnolting in #670
• ⚠️ Constrain/optimize MTVAL and MCOUNTEREN CSRs by @stnolting in #671
• [rtl] minor edits and cleanups by @stnolting in #672

Full Changelog: v1.8.7...v1.8.8

v1.8.7

What's Changed

• demo_blink_led_asm bugfix by @vivi202 in #639
• Minor rtl edits, cleanups and optimizations by @stnolting in #641
• Minor rtl edits by @stnolting in #646
• ⚠️ Rework SoC bus system and memory map by @stnolting in #648
• ⚠️ Remove UART sim-mode's 32-bit dump by @stnolting in #650
• ✨ Add support for RISC-V A ISA extension (atomic memory access) by @stnolting in #651
• Minor rtl edits by @stnolting in #652
• [rtl] Optimize bus system and customization options by @stnolting in #653
• 🐛 fixing some LR/SC design flaws by @stnolting in #654

New Contributors

• @vivi202 made their first contribution in #639

Full Changelog: v1.8.6...v1.8.7

v1.8.6

What's Changed

• [TRNG] software can now retrieve FIFO size by @stnolting in #616
• [DMA] add automatic trigger mode by @stnolting in #618
• 🐛 [linker script] fix section continuity issue by @stnolting in #626
• [SYSINFO] re-arrange bits by @stnolting in #627
• ✨ Re-add simplified stream link interface (SLINK) by @stnolting in #628
• ✨ add CRC unit by @stnolting in #632
• [makefile] extend GDB target by @stnolting in #634
• ⚠️ remove BUSKEEPER's status register by @stnolting in #635
• optimize CPU's control logic by @stnolting in #636
• 🧪 VHDL - use entity instantiation by @stnolting in #637

Full Changelog: v1.8.5...v1.8.6

v1.8.5

What's Changed

• ✨ add optional direct memory access controller (DMA) by @stnolting in #593
• [rtl] minor edits by @stnolting in #599
• 🐛 [rtl] fix bug in DMA by @stnolting in #601
• [rtl] minor edits; update to VUnit v5 by @stnolting in #605
• [rtl] rework SoC bus system by @stnolting in #607
• [rtl] minor rtl updates by @stnolting in #608
• 🐛 [FPU] fix bug in FPU trap handling by @stnolting in #609
• [CPU] move instruction address to mtval on ebreak exception by @stnolting in #611
• Add programmable TRNG interrupt by @stnolting in #615

Full Changelog: v1.8.4...v1.8.5

v1.8.4

What's Changed

• [PMP] add support for NA4 and NAPOT modes by @stnolting in #566
• [rtl] cleanups and optimizations by @stnolting in #569
• update XIRQ controller by @stnolting in #570
• [rtl] coding style edits and cleanups by @stnolting in #571
• Remove warnings by @emb4fun in #561
• Updated path for FreeRTOS example - FreeRTOS-Plus-TCP by @matty0005 in #574
• 🐛 FPU bug fix and rtl optimizations by @stnolting in #578
• [UART] add FIFO configuration to DATA register by @stnolting in #581
• 🐛⚠️ CPU bug-fixes, major cleanups and optimizations by @stnolting in #586
• Freertos xirq example by @matty0005 in #585
• [rtl] minor optimizations/cleanups of processor bus system by @stnolting in #591
• Added a test case to show the 1.0 + -1.0 instruction time-out under f… by @mikaelsky in #592

New Contributors

• @matty0005 made their first contribution in #574

Full Changelog: v1.8.3...v1.8.4

v1.8.3

What's Changed

• [rtl] minor edits, cleanups and optimization by @stnolting in #545
• [sw/lib] move register and bit definitions to according module header files by @emb4fun in #542
• ✨ add support for RISC-V 'Zicond' ISA extension by @stnolting in #546
• [docs] rework, update and cleanup entire documentation by @stnolting in #549
• Added support for USER_LIBS in the command SW makefile. by @vhdlnerd in #551
• [sw] bootloader: send wake up command to flash before trying to speak with it by @agamez in #552
• [rtl] reworks, cleanups and optimizations by @stnolting in #550
• [sw/example] demo_twi: remove comment requiring PWM module by @agamez in #554
• [sw/lib] move CSR definitions to separate file by @stnolting in #553
• [rtl] re-add VHDL process names by @stnolting in #555
• ✨ add time[h] CSRs by @stnolting in #556
• [rtl] cleanup top's generics by @stnolting in #557
• [rtl] cleanup, reworks and optimization by @stnolting in #559
• 🧪 Add processor data cache by @stnolting in #560
• ⚠️ [rtl] remove Zicsr generic, cleanups and optimizations by @stnolting in #562
• Bootloader Config Parameter to Enable UART0 HW Handshaking. by @vhdlnerd in #565

New Contributors

• @vhdlnerd made their first contribution in #551
• @agamez made their first contribution in #552

Full Changelog: v1.8.2...v1.8.3

v1.8.2

What's Changed

• [CFS] add another 64 interface registers by @stnolting in #503
• ⚠️ rename SPI & XIP module's top interface ports by @stnolting in #504
• Corrected the PWM address which was a typo. by @emb4fun in #506
• ✨ add SDI module (SPI device-class interface) by @stnolting in #505
• GPTMR: Change "variable style" by "pointer style" by @emb4fun in #511
• MTIME: Change "variable style" by "pointer style" by @emb4fun in #512
• NEOLED: Change "variable style" by "pointer style" by @emb4fun in #513
• GPIO: Change "variable style" by "pointer style" by @emb4fun in #510
• ONEWIRE: Change "variable style" by "pointer style" by @emb4fun in #514
• PWM: Change "variable style" by "pointer style" by @emb4fun in #515
• SDI: Change "variable style" by "pointer style" by @emb4fun in #516
• SPI: Change "variable style" by "pointer style" by @emb4fun in #517
• TRNG: Change "variable style" by "pointer style" by @emb4fun in #518
• TWI: Change "variable style" by "pointer style" by @emb4fun in #519
• WDT: Change "variable style" by "pointer style" by @emb4fun in #520
• XIP: Change "variable style" by "pointer style" by @emb4fun in #521
• XIRQ: Change "variable style" by "pointer style" by @emb4fun in #522
• CFS: Change "variable style" by "pointer style" by @emb4fun in #523
• DM: Change "variable style" by "pointer style" by @emb4fun in #524
• BUSKEEPER: Change "variable style" by "pointer style" by @emb4fun in #525
• Removed unused defines IO_REGx and IO_ROMx by @emb4fun in #527
• SYSINFO: Change "variable style" by "pointer style" by @emb4fun in #526
• Added test case in sw/example to demonstrate floating point normalize… by @mikaelsky in #528
• [rtl] minor GPTMR code reworks by @stnolting in #529
• Common neorv32 uart functions by @akaeba in #509
• [sw/uart] allow for escaped percent sign by @NikLeberg in #531
• ⚠️ Update / rework SPI module by @stnolting in #530
• SVD: Corrected typo by @emb4fun in #532
• ⚠️ rework UART modules by @stnolting in #533
• Update NEOLED module by @stnolting in #536
• [UART] re-integrate RTS/CTS hardware flow-control by @stnolting in #541
• [rtl] move ONEWIRE and TWI tri-state drivers out of core by @stnolting in #543

New Contributors

• @mikaelsky made their first contribution in #528

Full Changelog: v1.8.1...v1.8.2

v1.8.1

What's Changed

• [docs] add note about platform specific DTMs by @NikLeberg in #482
• 💄 [docs] update/rework figures by @stnolting in #483
• [rtl] Cleanup CPU interrupt controller by @stnolting in #484
• [rtl] rework mip csr by @stnolting in #486
• [rtl] CPU control optimization by @stnolting in #487
• [rtl] CPU: use record as main control bus type by @stnolting in #489
• [rtl] add co-processor timing monitor by @stnolting in #490
• [sw/lib/include/neorv32.h]: remove redundant uart typedef by @akaeba in #493
• ⚠️ Replace IO_GPIO_EN generic by @stnolting in #491
• [rtl] minor trap logic optimizations and fixes by @stnolting in #497
• Add run.py dump of VHDL-LS library mapping by @kraigher in #494
• [sw] add '_zicsr' to default MARCH configuration by @stnolting in #496
• 🐛 [rtl] fix bug in co-processor monitor by @stnolting in #500
• ⚠️ constrain & relocate PWM module by @stnolting in #501
• ⚠️ remove SLINK module by @stnolting in #502

New Contributors

• @NikLeberg made their first contribution in #482
• @kraigher made their first contribution in #494

Full Changelog: v1.8.0...v1.8.1

v1.8.0

What's Changed

• Remove signal initalizations by @tmeissner in #464
• Upgrade on-chip-debugger by @stnolting in #463
• ⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module by @stnolting in #465
• [sw] rename library functions by @stnolting in #467
• [rtl] OCD: update DTM and DM by @stnolting in #468
• Fix value of SYSINFO_SOC_IO_ONEWIRE in NEORV32_SYSINFO_SOC_enum by @tmeissner in #469
• [rtl] CPU: logic optimization by @stnolting in #470
• [sw/example/demo_spi_irq]: make read/write data pointer and busy flag… by @akaeba in #471
• [rtl] update TRNG by @stnolting in #472
• [rtl/test_setups] add on-chip debugger test setup by @stnolting in #473
• ⚠️ rework watchdog timer (WDT) by @stnolting in #474
• [rtl] VHDL cleanups by @stnolting in #476
• ⚠️ Rework CPU counters by @stnolting in #477
• [sw] cleanup and update software framework by @stnolting in #478

Full Changelog: v1.7.9...v1.8.0