From 005f770631079a051fc9a881f692ff980a8cd2d6 Mon Sep 17 00:00:00 2001 From: Kris Provoost Date: Mon, 6 Jan 2025 21:53:58 +0100 Subject: [PATCH 1/2] adding support for the Z7 Nano board --- vivado/z7-nano-test-setup/.gitignore | 3 + vivado/z7-nano-test-setup/README.md | 38 ++++++++++++ vivado/z7-nano-test-setup/create_project.tcl | 62 +++++++++++++++++++ vivado/z7-nano-test-setup/pin_constraints.xdc | 31 ++++++++++ vivado/z7-nano-test-setup/timings.xdc | 7 +++ 5 files changed, 141 insertions(+) create mode 100644 vivado/z7-nano-test-setup/.gitignore create mode 100644 vivado/z7-nano-test-setup/README.md create mode 100644 vivado/z7-nano-test-setup/create_project.tcl create mode 100644 vivado/z7-nano-test-setup/pin_constraints.xdc create mode 100644 vivado/z7-nano-test-setup/timings.xdc diff --git a/vivado/z7-nano-test-setup/.gitignore b/vivado/z7-nano-test-setup/.gitignore new file mode 100644 index 0000000..97d1942 --- /dev/null +++ b/vivado/z7-nano-test-setup/.gitignore @@ -0,0 +1,3 @@ +/vivado* +/.Xil +/work/* diff --git a/vivado/z7-nano-test-setup/README.md b/vivado/z7-nano-test-setup/README.md new file mode 100644 index 0000000..8a27c56 --- /dev/null +++ b/vivado/z7-nano-test-setup/README.md @@ -0,0 +1,38 @@ +# NEORV32 Test Setup for the Microphase Z7 Nano FPGA Board + +This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Microphase Z7 Nano board. +It uses the simplified +[`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor +top entity that provides a minimalistic interface (clock, reset, UART and 8 IO's). + +* FPGA Board: :books: [Microphase Z7 Nano FPGA Board](https://github.com/MicroPhase/fpga-docs/blob/master/schematic/Z7-NANO_R21.pdf) +* FPGA: Xilinx Artix-7 `c7z020clg400-2` +* Toolchain: Xilinx Vivado (tested with Vivado 2023.1) + +### FPGA Utilization + +``` +Total LUT's 2034 / 53,200 ( 3.82 % ) +Total registers 1400 / 106400 ( 1.32 % ) +Total Block RAM s 8 / 140 ( 5.71 % ) +``` + +## NEORV32 Configuration + +:information_source: +See the top entity +[`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for +configuration and entity details and oin_constraints.xdc for the according FPGA pin mapping. + +* CPU: `rv32imc_Zicsr` +* Memory: + * 16kB instruction memory (internal IMEM) + * 8kB data memory (internal DMEM) + * bootloader ROM +* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` +* Tested with version [`1.10.8.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 50 MHz from on-board oscillator +* Reset: Via dedicated on-board "RESET" button +* GPIO output port `gpio_o` + * bits 0..7 are connected to the expansion header +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the expansion header \ No newline at end of file diff --git a/vivado/z7-nano-test-setup/create_project.tcl b/vivado/z7-nano-test-setup/create_project.tcl new file mode 100644 index 0000000..8e051f7 --- /dev/null +++ b/vivado/z7-nano-test-setup/create_project.tcl @@ -0,0 +1,62 @@ +set board "z7-nano" + +# Create and clear output directory + +set loc_script [file normalize [info script]] +set loc_folder [file dirname $loc_script] +puts $loc_folder +cd $loc_folder + +set outputdir work +file mkdir $outputdir + +set files [glob -nocomplain "$outputdir/*"] +if {[llength $files] != 0} { + puts "deleting contents of $outputdir" + file delete -force {*}[glob -directory $outputdir *]; # clear folder contents +} else { + puts "$outputdir is empty" +} + +switch $board { + "z7-nano" { + set z7part "xc7z020clg400-2" + set z7prj ${board}-test-setup + } +} + +# Create project +create_project -part $z7part $z7prj $outputdir + +set_property target_language VHDL [current_project] +set_property simulator_language VHDL [current_project] + +# Define filesets + +## Core: NEORV32 +add_files [glob ./../../neorv32/rtl/core/*.vhd] +set_property library neorv32 [get_files [glob ./../../neorv32/rtl/core/*.vhd]] + +## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources +set fileset_design ./../../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd + +## Constraints +set fileset_constraints [glob ./*.xdc] + +## Simulation-only sources +set fileset_sim [list ./../../neorv32/sim/neorv32_tb.vhd ./../../neorv32/sim/sim_uart_rx.vhd] + +# Add source files + +## Design +add_files $fileset_design + +## Constraints +add_files -fileset constrs_1 $fileset_constraints + +## Simulation-only +add_files -fileset sim_1 $fileset_sim + +# Run synthesis, implementation and bitstream generation +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 diff --git a/vivado/z7-nano-test-setup/pin_constraints.xdc b/vivado/z7-nano-test-setup/pin_constraints.xdc new file mode 100644 index 0000000..a31b0c5 --- /dev/null +++ b/vivado/z7-nano-test-setup/pin_constraints.xdc @@ -0,0 +1,31 @@ +set_property PACKAGE_PIN N18 [get_ports clk_i] +set_property PACKAGE_PIN P14 [get_ports rstn_i] + +set_property IOSTANDARD LVCMOS33 [get_ports clk_i] +set_property IOSTANDARD LVCMOS33 [get_ports rstn_i] + + +set_property PACKAGE_PIN N17 [get_ports {gpio_o[7]}] +set_property PACKAGE_PIN R16 [get_ports {gpio_o[6]}] +set_property PACKAGE_PIN T17 [get_ports {gpio_o[5]}] +set_property PACKAGE_PIN T16 [get_ports {gpio_o[4]}] +set_property PACKAGE_PIN W18 [get_ports {gpio_o[3]}] +set_property PACKAGE_PIN Y18 [get_ports {gpio_o[2]}] +set_property PACKAGE_PIN Y16 [get_ports {gpio_o[1]}] +set_property PACKAGE_PIN V17 [get_ports {gpio_o[0]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[0]}] + + +set_property PACKAGE_PIN T10 [get_ports uart0_txd_o] +set_property PACKAGE_PIN T11 [get_ports uart0_rxd_i] + +set_property IOSTANDARD LVCMOS33 [get_ports uart0_txd_o] +set_property IOSTANDARD LVCMOS33 [get_ports uart0_rxd_i] diff --git a/vivado/z7-nano-test-setup/timings.xdc b/vivado/z7-nano-test-setup/timings.xdc new file mode 100644 index 0000000..8f52b7e --- /dev/null +++ b/vivado/z7-nano-test-setup/timings.xdc @@ -0,0 +1,7 @@ +# CLOCKS external + + create_clock -period 20.000 [get_ports clk_i] + +# False paths + + set_false_path -from [get_ports rstn_i] \ No newline at end of file From b8cacf9ffa2b645f1f615d35fb574b6e72c4b7b6 Mon Sep 17 00:00:00 2001 From: Kris Provoost Date: Mon, 6 Jan 2025 21:59:41 +0100 Subject: [PATCH 2/2] adding documentation --- README.md | 1 + vivado/z7-nano-test-setup/README.md | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index be2f5ee..6b864ec 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,7 @@ The setups using commercial toolchains provide pre-configured project files that | :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/arty-a7-test-setup) | Xilinx Vivado | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) | Xilinx Artix-7 `XC7A35TICSG324-1L` | [stnolting](https://github.com/stnolting) | | :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | | :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) | Xilinx Artix-7 `XC7A100TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | +| :file_folder: [`z7-nano-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/z7-nano-test-setup) | Xilinx Vivado | [Microphase Z7 Nano FPGA Board](https://github.com/MicroPhase/fpga-docs/blob/master/schematic/Z7-NANO_R21.pdf) | Xilinx ZynQ 7000 `c7z020clg400-2` | [provoostkris](https://github.com/provoostkris) | | :file_folder: [`on-chip-debugger-intel`](https://github.com/stnolting/neorv32-setups/tree/main/quartus/on-chip-debugger-intel) | Intel Quartus Prime | [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) | Intel Cyclone IV E `EP4CE15F23C8` | [NikLeberg](https://github.com/NikLeberg) | | :file_folder: [`tang-nano-9k`](https://github.com/stnolting/neorv32-setups/tree/main/gowineda/tang-nano-9k) | Gowin EDA | [Sipeed Tang Nano 9K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) | Gowin LittleBee GW1NR-9 `GW1NR-LV9QN88PC6/I5` | [IvanVeloz](https://github.com/IvanVeloz) diff --git a/vivado/z7-nano-test-setup/README.md b/vivado/z7-nano-test-setup/README.md index 8a27c56..534b47a 100644 --- a/vivado/z7-nano-test-setup/README.md +++ b/vivado/z7-nano-test-setup/README.md @@ -6,7 +6,7 @@ It uses the simplified top entity that provides a minimalistic interface (clock, reset, UART and 8 IO's). * FPGA Board: :books: [Microphase Z7 Nano FPGA Board](https://github.com/MicroPhase/fpga-docs/blob/master/schematic/Z7-NANO_R21.pdf) -* FPGA: Xilinx Artix-7 `c7z020clg400-2` +* FPGA: Xilinx ZynQ 7000 `c7z020clg400-2` * Toolchain: Xilinx Vivado (tested with Vivado 2023.1) ### FPGA Utilization