From fa4e58c604e456ae0bb4236186120250040ab04a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 10 Jan 2025 11:58:50 -0800 Subject: [PATCH] updates for future lcls-timing-core@v3.9.0 release --- hardware/XilinxVariumC1100/xdc/C1100Hsio.xdc | 2 ++ python/lcls2_pgp_fw_lib/shared/_TimingRx.py | 9 ++++--- shared/rtl/TimingPhyMonitor.vhd | 2 +- shared/rtl/UltraScale+/TimingRx.vhd | 26 +++++++++++++++++--- shared/rtl/UltraScale/TimingRx.vhd | 24 ++++++++++++++++-- shared/ruckus.tcl | 2 +- 6 files changed, 54 insertions(+), 11 deletions(-) diff --git a/hardware/XilinxVariumC1100/xdc/C1100Hsio.xdc b/hardware/XilinxVariumC1100/xdc/C1100Hsio.xdc index 9390b94..083e5ca 100644 --- a/hardware/XilinxVariumC1100/xdc/C1100Hsio.xdc +++ b/hardware/XilinxVariumC1100/xdc/C1100Hsio.xdc @@ -168,3 +168,5 @@ set_clock_groups -asynchronous \ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {U_HSIO/U_TimingRx/GEN_VEC[0].REAL_PCIE.U_GTY/LOCREF_G.U_TimingGtyCore/inst/gen_gtwizard_gtye4_top.TimingGty_fixedlat_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -group [get_clocks -of_objects [get_pins {U_HSIO/U_TimingRx/GEN_VEC[0].U_refClkDiv2/O}]] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {U_HSIO/U_TimingRx/GEN_VEC[1].REAL_PCIE.U_GTY/LOCREF_G.U_TimingGtyCore/inst/gen_gtwizard_gtye4_top.TimingGty_fixedlat_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -group [get_clocks -of_objects [get_pins {U_HSIO/U_TimingRx/GEN_VEC[1].U_refClkDiv2/O}]] + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins U_HSIO/U_TimingRx/U_stableClk/O]] -group [get_clocks -of_objects [get_pins U_axilClk/MmcmGen.U_Mmcm/CLKOUT0]] diff --git a/python/lcls2_pgp_fw_lib/shared/_TimingRx.py b/python/lcls2_pgp_fw_lib/shared/_TimingRx.py index dec4e90..57b0af1 100644 --- a/python/lcls2_pgp_fw_lib/shared/_TimingRx.py +++ b/python/lcls2_pgp_fw_lib/shared/_TimingRx.py @@ -16,6 +16,7 @@ import l2si_core import lcls2_pgp_fw_lib.shared as shared +import surf.xilinx as xil class TimingRx(pr.Device): def __init__( @@ -26,15 +27,15 @@ def __init__( **kwargs): super().__init__(**kwargs) - self.add(LclsTimingCore.GthRxAlignCheck( - name = "GthRxAlignCheck[0]", + self.add(xil.GtRxAlignCheck( + name = "GtRxAlignCheck[0]", offset = 0x0000_0000, expand = False, hidden = False, )) - self.add(LclsTimingCore.GthRxAlignCheck( - name = "GthRxAlignCheck[1]", + self.add(xil.GtRxAlignCheck( + name = "GtRxAlignCheck[1]", offset = 0x0001_0000, expand = False, hidden = False, diff --git a/shared/rtl/TimingPhyMonitor.vhd b/shared/rtl/TimingPhyMonitor.vhd index 80e564f..c800a9e 100644 --- a/shared/rtl/TimingPhyMonitor.vhd +++ b/shared/rtl/TimingPhyMonitor.vhd @@ -80,7 +80,7 @@ architecture rtl of TimingPhyMonitor is remTrigDropCnt => (others => (others => '0')), loopback => "000", cntRst => '0', - mmcmRst => '0', + mmcmRst => '1', rxUserRst => '0', txUserRst => '0', txPhyReset => '0', diff --git a/shared/rtl/UltraScale+/TimingRx.vhd b/shared/rtl/UltraScale+/TimingRx.vhd index cfa9ea8..d133742 100644 --- a/shared/rtl/UltraScale+/TimingRx.vhd +++ b/shared/rtl/UltraScale+/TimingRx.vhd @@ -184,6 +184,9 @@ architecture mapping of TimingRx is signal gtRxControlReset : sl; signal gtRxControlPllReset : sl; + signal stableClk : sl; + signal stableRst : sl; + ----------------------------------------------- -- Event Header Cache signals ----------------------------------------------- @@ -348,6 +351,23 @@ begin mAxiReadMasters => axilReadMasters, mAxiReadSlaves => axilReadSlaves); + U_stableClk : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 2) + port map ( + I => axilClk, + CE => '1', + CLR => '0', + O => stableClk); + + U_stableRst : entity surf.RstSync + generic map ( + TPD_G => TPD_G) + port map ( + clk => stableClk, + asyncRst => axilRst, + syncRst => stableRst); + ------------- -- GTH Module ------------- @@ -394,8 +414,8 @@ begin generic map ( TPD_G => TPD_G, EXTREF_G => false, + AXI_CLK_FREQ_G => AXIL_CLK_FREQ_G, AXIL_BASE_ADDR_G => AXIL_CONFIG_C(RX_PHY0_INDEX_C+i).baseAddr, - ADDR_BITS_G => 12, GTY_DRP_OFFSET_G => x"00001000") port map ( -- AXI-Lite Port @@ -405,8 +425,8 @@ begin axilReadSlave => axilReadSlaves(RX_PHY0_INDEX_C+i), axilWriteMaster => axilWriteMasters(RX_PHY0_INDEX_C+i), axilWriteSlave => axilWriteSlaves(RX_PHY0_INDEX_C+i), - stableClk => axilClk, - stableRst => axilRst, + stableClk => stableClk, + stableRst => stableRst, -- GTH FPGA IO gtRefClk => '0', -- Using GTGREFCLK instead gtRefClkDiv2 => refClkDiv2(i), diff --git a/shared/rtl/UltraScale/TimingRx.vhd b/shared/rtl/UltraScale/TimingRx.vhd index 5fe73ac..6b23479 100644 --- a/shared/rtl/UltraScale/TimingRx.vhd +++ b/shared/rtl/UltraScale/TimingRx.vhd @@ -184,6 +184,9 @@ architecture mapping of TimingRx is signal gtRxControlReset : sl; signal gtRxControlPllReset : sl; + signal stableClk : sl; + signal stableRst : sl; + ----------------------------------------------- -- Event Header Cache signals ----------------------------------------------- @@ -348,6 +351,23 @@ begin mAxiReadMasters => axilReadMasters, mAxiReadSlaves => axilReadSlaves); + U_stableClk : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 2) + port map ( + I => axilClk, + CE => '1', + CLR => '0', + O => stableClk); + + U_stableRst : entity surf.RstSync + generic map ( + TPD_G => TPD_G) + port map ( + clk => stableClk, + asyncRst => axilRst, + syncRst => stableRst); + ------------- -- GTH Module ------------- @@ -405,8 +425,8 @@ begin axilReadSlave => axilReadSlaves(RX_PHY0_INDEX_C+i), axilWriteMaster => axilWriteMasters(RX_PHY0_INDEX_C+i), axilWriteSlave => axilWriteSlaves(RX_PHY0_INDEX_C+i), - stableClk => axilClk, - stableRst => axilRst, + stableClk => stableClk, + stableRst => stableRst, -- GTH FPGA IO gtRefClk => '0', -- Using GTGREFCLK instead gtRefClkDiv2 => refClkDiv2(i), diff --git a/shared/ruckus.tcl b/shared/ruckus.tcl index 76ebfec..c9213d7 100644 --- a/shared/ruckus.tcl +++ b/shared/ruckus.tcl @@ -15,7 +15,7 @@ if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMO if { [SubmoduleCheck {l2si-core} {3.3.3} ] < 0 } {exit -1} if { [SubmoduleCheck {lcls-timing-core} {3.6.3} ] < 0 } {exit -1} if { [SubmoduleCheck {ruckus} {4.3.2} ] < 0 } {exit -1} - if { [SubmoduleCheck {surf} {2.31.0} ] < 0 } {exit -1} + if { [SubmoduleCheck {surf} {2.53.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0"