cannot understand ccache_sideband

[suhasskrishanmurthy]

Hi,
I was reading the zsbl linker script. In that I am unable understand ccache_sideband. which is used to store all the data sections and stack segment. Please can someone help in understanding this. any related links will be helpfull.

[jim-wilson]

The L2 cache can be configured as a cache or as on chip memory (LIM), or as a mixture. The zsbl loads the fsbl into LIM. It can't use DRAM as the fsbl needs to run first to initialize the DRAM. There is info on the L2 Cache and LIM in the FU540 manual. There is also a chapter on the boot process.