clean all unused references in the definition section

[drom]

No description provided.

[adeelliaquat-lm]

The busDefinitions section of definitions currently contains all the mappings of any portgroup. You are suggesting to remove the unused portgroup mappings, right?

The mappings are generated as a result of duh-portinf command. One way to do it is to tweak the duh-portinf, so its output base document doesn’t have unused portgroup mappings, to begin with. It will have all the unused references in the busInterfacesAlts section of the component, but not their respective portgroup mappings in the busDefinitions. What do you think?
An example base document is attached below for reference.

{
    "component": {
        "vendor": "sifive",
        "library": "blocks",
        "name": "pio",
        "version": "0.1.0",
        "busInterfaces": [
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_0-prefix_t_ctrl-slave-AXI4-Lite_rtl"},
            {"$ref": "#/definitions/bundleDefinitions/bundle-root"}
        ],
        "addressSpaces": [],
        "memoryMaps": [{
            "name": "CSR",
            addressBlocks: [{
                name: 'csrAddressBlock',
                baseAddress: 0,
                range: 1024, width: 32,
                usage: 'register',
                volatile: false, access: 'read-write',
                registers: [{
                    name: 'ODATA',
                    addressOffset: 0, size: 32,
                    displayName: 'Output Data Register',
                    fields: [{name: 'data', bitWidth: 32, bitOffset: 0}]
                }, {
                    name: 'OENABLE', addressOffset: 4, size: 32,
                    displayName: 'Data direction',
                    description: 'determines whether the pin is an input or an output. If the data direction bit is a 1, then the pin is an input',
                    fields: [{name: 'data', bitWidth: 32, bitOffset: 0}]
                }, {
                    name: 'IDATA', addressOffset: 8, size: 32,
                    displayName: 'Input data',
                    description: 'read the port pins',
                    fields: [{name: 'data', bitWidth: 32, bitOffset: 0}]
                }]
            }]
        }],
        "model": {
            "views": [],
            "ports": {
                "$ref": "#/definitions/ports"
            }
        },
        "fileSets": {},
        "pSchema": {
            "type": "object",
            "properties": {
                "addrWidth": {
                    "title": "Address bus width",
                    "type": "integer",
                    "minimum": 6,
                    "maximum": 32,
                    "default": 12
                },
                "dataWidth": {
                    "title": "Data bus width",
                    "type": "integer",
                    "minimum": 32,
                    "maximum": 64,
                    "default": 32
                },
                "pioWidth": {
                    "title": "Number of IO pads",
                    "type": "integer",
                    "minimum": 1,
                    "maximum": 32,
                    "default": 32
                },
                "writeStrobeWidth": {
                    "title": "Write strobe width",
                    "type": "integer",
                    "minimum": 1,
                    "maximum": 4,
                    "default": 4
                }
            }
        },
        "busInterfaceAlts": [
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_1-prefix_t_ctrl-slave-LMAXI4-Lite_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_2-prefix_t_ctrl-slave-AXI5-Lite_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_3-prefix_t_ctrl-master-AXI4-Lite_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_4-prefix_t_ctrl-master-LMAXI4-Lite_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_5-prefix_t_ctrl-slave-WO_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_6-prefix_t_ctrl-master-INTERRUPT_rtl"},
            {"$ref": "#/definitions/busDefinitions/busint-portgroup_0-mapping_7-prefix_t_ctrl-slave-INTERRUPT_rtl"}
        ]
    },
    "definitions": {
        "ports": {
            "t_ctrl_awvalid": 1,
            "t_ctrl_awready": -1,
            "t_ctrl_awaddr": "addrWidth",
            "t_ctrl_awprot": 3,
            "t_ctrl_wvalid": 1,
            "t_ctrl_wready": -1,
            "t_ctrl_wdata": "dataWidth",
            "t_ctrl_wstrb": "writeStrobeWidth",
            "t_ctrl_bvalid": -1,
            "t_ctrl_bready": 1,
            "t_ctrl_bresp": -2,
            "t_ctrl_arvalid": 1,
            "t_ctrl_arready": -1,
            "t_ctrl_araddr": "addrWidth",
            "t_ctrl_arprot": 3,
            "t_ctrl_rvalid": -1,
            "t_ctrl_rready": 1,
            "t_ctrl_rdata": "-(dataWidth)",
            "t_ctrl_rresp": -2,
            "irq0": -1,
            "irq1": -1,
            "odata": "-(pioWidth)",
            "oenable": "-(pioWidth)",
            "idata": "pioWidth",
            "clk": 1,
            "reset_n": 1
        },
        "pg_cnt": 1,
        "busDefinitions": {
            "busint-portgroup_0-mapping_0-prefix_t_ctrl-slave-AXI4-Lite_rtl": {
                "name": "t_ctrl",
                "interfaceMode": "slave",
                "busType": {
                    "vendor": "amba.com",
                    "library": "AMBA4",
                    "name": "AXI4-Lite",
                    "version": "r0p0_0"
                },
                "abstractionTypes": [
                    {
                        "viewRef": "RTLview",
                        "portMaps": {
                            "RREADY": "t_ctrl_rready",
                            "WREADY": "t_ctrl_wready",
                            "RRESP": "t_ctrl_rresp",
                            "ARREADY": "t_ctrl_arready",
                            "AWADDR": "t_ctrl_awaddr",
                            "AWPROT": "t_ctrl_awprot",
                            "AWVALID": "t_ctrl_awvalid",
                            "WSTRB": "t_ctrl_wstrb",
                            "AWREADY": "t_ctrl_awready",
                            "BREADY": "t_ctrl_bready",
                            "ARPROT": "t_ctrl_arprot",
                            "RDATA": "t_ctrl_rdata",
                            "RVALID": "t_ctrl_rvalid",
                            "ARVALID": "t_ctrl_arvalid",
                            "WVALID": "t_ctrl_wvalid",
                            "BRESP": "t_ctrl_bresp",
                            "BVALID": "t_ctrl_bvalid",
                            "WDATA": "t_ctrl_wdata",
                            "ARADDR": "t_ctrl_araddr"
                        }
                    }
                ]
            },
        },
        "busMappedPortGroups": [
            [
                "portgroup_0",
                [
                    [
                        "num_ports",
                        19
                    ],
                    [
                        "prefix",
                        "t_ctrl_"
                    ],
                    [
                        "num-direction-mismatch",
                        0
                    ],
                    [
                        "num-width-mismatch",
                        0
                    ]
                ]
            ]
        ],
        "bundleDefinitions": {
            "bundle-root": {
                "name": "root",
                "interfaceMode": null,
                "busType": "bundle",
                "abstractionTypes": [
                    {
                        "viewRef": "RTLview",
                        "portMaps": {
                            "irq": [
                                "irq0",
                                "irq1"
                            ],
                            "odata": "odata",
                            "oenable": "oenable",
                            "idata": "idata",
                            "clk": "clk",
                            "reset_n": "reset_n"
                        }
                    }
                ]
            }
        }
    }
}