From 3b76e293e322d4b5aacf6c5c389f0ee7fa74582c Mon Sep 17 00:00:00 2001 From: Pierre Blanchard <147173952+blapie@users.noreply.github.com> Date: Tue, 12 Mar 2024 15:31:38 +0000 Subject: [PATCH] Missing docs for RISC-V (PR #529) Update supported environment now that quad, dft and inline headers are in. Fixes #524 --- README.md | 7 ++++++- docs/index.xhtml | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 42021a11..5ae99fab 100644 --- a/README.md +++ b/README.md @@ -92,7 +92,6 @@ Generation of inline headers is also supported for most vector extensions. #### Work in progress -- DFT, Quad. and inline headers generations are not supported with RISC-V yet. - LTO is not tested in CI yet. ### Compiler support @@ -101,6 +100,12 @@ Results are displayed for gcc 11 and llvm 17, the compiler versions used in CI t Older versions should be supported too, while newer ones are either not tested or have known issues. +Some compiler versions simply do not support certain vector extensions, for instance SVE is only supported for gcc version 9 onwards. + +Similarly, the RISC-V interface in SLEEF is based on version 1.0 of the intrinsics, which is only supported from llvm version 17 and gcc version 14 onwards. + +Toolchain files provide some information on supported compiler versions. + ### OS support Only Linux distributions are currently tested in CI and thus officially supported. diff --git a/docs/index.xhtml b/docs/index.xhtml index 327658d7..8b0afaf0 100644 --- a/docs/index.xhtml +++ b/docs/index.xhtml @@ -145,6 +145,7 @@
  • AArch32 - NEON
  • PowerPC64 - VSX (POWER8), VSX-3 (POWER9)
  • System/390 - VXE (z14), VXE2 (z15)
    • +
  • RISC-V - RVV1, RVV2
  • CUDA
  • WebAssembly - SSE2
    • @@ -285,6 +286,14 @@ N/A N/A + + RISC-V (64-bit), Linux + + Supported + Supported + N/A + N/A + @@ -321,6 +330,16 @@ supported by Cygwin ABI.

    +

    + *4 Some compiler versions simply do not support certain vector + extensions, for instance SVE is only supported for gcc version 9 + onwards. Similarly, the RISC-V interface in SLEEF is based on + version 1.0 of the intrinsics, which is only supported from llvm + version 17 and gcc version 14 onwards. Toolchain files provide + some information on supported compiler versions. +

    + +