From a0c7bf36cb1521a50ddb69e26754ffd7cc8e5362 Mon Sep 17 00:00:00 2001
From: Andrey Zgarbul <zgarbul.andrey@gmail.com>
Date: Mon, 6 Jan 2025 15:18:30 +0300
Subject: [PATCH] Keep position when merge fields

---
 CHANGELOG-rust.md     |  8 +++++++-
 Cargo.toml            |  2 +-
 src/patch/register.rs | 15 +++++++++------
 3 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/CHANGELOG-rust.md b/CHANGELOG-rust.md
index 6db8a08..2aa6252 100644
--- a/CHANGELOG-rust.md
+++ b/CHANGELOG-rust.md
@@ -5,6 +5,11 @@ This changelog tracks the Rust `svdtools` project. See
 
 ## [Unreleased]
 
+## [v0.4.0] 2025-01-06
+
+* **breaking** Support "?~" in field `_modify` & `_derive`
+* Keep position when merge fields
+
 ## [v0.3.21] 2024-12-31
 
 * `_derive` field
@@ -195,7 +200,8 @@ Other changes:
 
 * Initial release with feature-parity with the Python project.
 
-[Unreleased]: https://github.com/rust-embedded/svdtools/compare/v0.3.21...HEAD
+[Unreleased]: https://github.com/rust-embedded/svdtools/compare/v0.4.0...HEAD
+[v0.4.0]: https://github.com/rust-embedded/svdtools/compare/v0.3.21...v0.4.0
 [v0.3.21]: https://github.com/rust-embedded/svdtools/compare/v0.3.20...v0.3.21
 [v0.3.20]: https://github.com/rust-embedded/svdtools/compare/v0.3.19...v0.3.20
 [v0.3.19]: https://github.com/rust-embedded/svdtools/compare/v0.3.18...v0.3.19
diff --git a/Cargo.toml b/Cargo.toml
index 46ef573..fff94e6 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "svdtools"
-version = "0.3.21"
+version = "0.4.0"
 repository = "https://github.com/rust-embedded/svdtools/"
 description = "Tool for modifying bugs in CMSIS SVD"
 authors = ["Andrey Zgarbul <zgarbul.andrey@gmail.com>", "MarcoIeni"]
diff --git a/src/patch/register.rs b/src/patch/register.rs
index cd85e4c..9b62b26 100644
--- a/src/patch/register.rs
+++ b/src/patch/register.rs
@@ -454,12 +454,13 @@ impl RegisterExt for Register {
                 "Could not find any fields to merge {rpath}:{key}. Present fields: {present}.`"
             ));
         }
-        let mut bitwidth = 0;
-        let mut bitoffset = u32::MAX;
-        let mut first = true;
-        let mut desc = None;
         if let Some(fields) = self.fields.as_mut() {
-            for f in fields.iter_mut() {
+            let mut bitwidth = 0;
+            let mut bitoffset = u32::MAX;
+            let mut pos = usize::MAX;
+            let mut first = true;
+            let mut desc = None;
+            for (i, f) in fields.iter_mut().enumerate() {
                 if names.contains(&f.name) {
                     if first {
                         desc.clone_from(&f.description);
@@ -467,10 +468,12 @@ impl RegisterExt for Register {
                     }
                     bitwidth += f.bit_range.width;
                     bitoffset = bitoffset.min(f.bit_range.offset);
+                    pos = pos.min(i);
                 }
             }
             fields.retain(|f| !names.contains(&f.name));
-            fields.push(
+            fields.insert(
+                pos,
                 FieldInfo::builder()
                     .name(name)
                     .description(desc)