From 2266921af568291973859bd94b2e202fe893fc44 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Tue, 19 Sep 2017 16:37:22 +0200
Subject: [PATCH 001/234] Initial commit.

---
 riscv-rt/.gitignore        |   2 +
 riscv-rt/Cargo.toml        |  13 ++
 riscv-rt/README.md         |  18 ++
 riscv-rt/build.rs          |  18 ++
 riscv-rt/link.x            |  83 +++++++++
 riscv-rt/src/lang_items.rs |  45 +++++
 riscv-rt/src/lib.rs        | 343 +++++++++++++++++++++++++++++++++++++
 7 files changed, 522 insertions(+)
 create mode 100644 riscv-rt/.gitignore
 create mode 100644 riscv-rt/Cargo.toml
 create mode 100644 riscv-rt/README.md
 create mode 100644 riscv-rt/build.rs
 create mode 100644 riscv-rt/link.x
 create mode 100644 riscv-rt/src/lang_items.rs
 create mode 100644 riscv-rt/src/lib.rs

diff --git a/riscv-rt/.gitignore b/riscv-rt/.gitignore
new file mode 100644
index 00000000..1e7caa9e
--- /dev/null
+++ b/riscv-rt/.gitignore
@@ -0,0 +1,2 @@
+Cargo.lock
+target/
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
new file mode 100644
index 00000000..ac543add
--- /dev/null
+++ b/riscv-rt/Cargo.toml
@@ -0,0 +1,13 @@
+[package]
+name = "riscv-rt"
+version = "0.1.0"
+repository = "https://github.com/dvc94ch/riscv-rt"
+authors = ["David Craven <david@craven.ch>"]
+categories = ["embedded", "no-std"]
+description = "Minimal runtime / startup for RISCV CPU's"
+keywords = ["riscv", "runtime", "startup"]
+license = "ISC"
+
+[dependencies]
+r0 = "0.2.1"
+riscv = "0.1.0"
diff --git a/riscv-rt/README.md b/riscv-rt/README.md
new file mode 100644
index 00000000..1adfd84c
--- /dev/null
+++ b/riscv-rt/README.md
@@ -0,0 +1,18 @@
+# `riscv-rt`
+
+> Minimal runtime / startup for RISCV CPU's.
+
+# License
+Copyright 2017 David Craven
+
+Permission to use, copy, modify, and/or distribute this software for any purpose
+with or without fee is hereby granted, provided that the above copyright notice
+and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
+FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
+OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
new file mode 100644
index 00000000..4cd56c63
--- /dev/null
+++ b/riscv-rt/build.rs
@@ -0,0 +1,18 @@
+// NOTE: Adapted from cortex-m/build.rs
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("link.x"))
+        .unwrap()
+        .write_all(include_bytes!("link.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    println!("cargo:rerun-if-changed=build.rs");
+    println!("cargo:rerun-if-changed=link.x");
+}
diff --git a/riscv-rt/link.x b/riscv-rt/link.x
new file mode 100644
index 00000000..6fb76b98
--- /dev/null
+++ b/riscv-rt/link.x
@@ -0,0 +1,83 @@
+/* NOTE: Adapted from cortex-m/link.x */
+INCLUDE memory.x
+
+PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
+
+SECTIONS
+{
+  PROVIDE(_stext = ORIGIN(FLASH));
+
+  .text _stext : ALIGN(4)
+  {
+    /* Put reset handler first in .text section so it ends up as the entry */
+    /* point of the program. */
+    KEEP(*(.init));
+    KEEP(*(.init.rust));
+    KEEP(*(.trap));
+    KEEP(*(.trap.rust));
+
+    *(.text .text.*);
+  } > FLASH
+
+  .rodata : ALIGN(4)
+  {
+    *(.rodata .rodata.*);
+    . = ALIGN(4);
+  } > FLASH
+
+  .bss : ALIGN(4)
+  {
+    _sbss = .;
+    *(.bss .bss.*);
+    . = ALIGN(4);
+    _ebss = .;
+  } > RAM
+
+  .data : ALIGN(4)
+  {
+    _sidata = LOADADDR(.data);
+    _sdata = .;
+    /* Must be called __global_pointer$ for linker relaxations to work. */
+    PROVIDE(__global_pointer$ = . + 0x800);
+    *(.data .data.*);
+    . = ALIGN(4);
+    _edata = .;
+  } > RAM AT > FLASH /* LLD fails on AT > FLASH */
+
+  /* fake output .got section */
+  /* Dynamic relocations are unsupported. This section is only used to detect
+     relocatable code in the input files and raise an error if relocatable code
+     is found */
+  .got :
+  {
+    _sgot = .;
+    KEEP(*(.got .got.*));
+    _egot = .;
+  } > RAM AT > FLASH /* LLD fails on AT > FLASH */
+
+  /* The heap starts right after the .bss + .data section ends */
+  _sheap = _edata;
+
+  /* Due to an unfortunate combination of legacy concerns,
+     toolchain drawbacks, and insufficient attention to detail,
+     rustc has no choice but to mark .debug_gdb_scripts as allocatable.
+     We really do not want to upload it to our target, so we
+     remove the allocatable bit. Unfortunately, it appears
+     that the only way to do this in a linker script is
+     the extremely obscure "INFO" output section type specifier. */
+  /* a rustc hack will force the program to read the first byte of this section,
+     so we'll set the (fake) start address of this section to something we're
+     sure can be read at runtime: the start of the .text section */
+  /* LLD fails to parse _stext (INFO) */
+  .debug_gdb_scripts _stext (INFO) : {
+    KEEP(*(.debug_gdb_scripts))
+  }
+}
+
+/* Do not exceed this mark in the error messages below                | */
+ASSERT(_sgot == _egot, "
+.got section detected in the input files. Dynamic relocations are not
+supported. If you are linking to C code compiled using the `gcc` crate
+then modify your build script to compile the C code _without_ the
+-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
+details.");
diff --git a/riscv-rt/src/lang_items.rs b/riscv-rt/src/lang_items.rs
new file mode 100644
index 00000000..20e0f3fe
--- /dev/null
+++ b/riscv-rt/src/lang_items.rs
@@ -0,0 +1,45 @@
+// NOTE: Adapted from cortex-m/src/lang_items.rs
+
+use riscv::asm;
+
+/// Default panic handler
+#[linkage = "weak"]
+#[lang = "panic_fmt"]
+unsafe extern "C" fn panic_fmt(
+    _: ::core::fmt::Arguments, // fmt
+    _: &'static str, // file
+    _: u32, // line
+    _: u32, // col
+) -> ! {
+    asm::ebreak();
+    loop {}
+}
+
+/// Lang item required to make the normal `main` work in applications
+// This is how the `start` lang item works:
+// When `rustc` compiles a binary crate, it creates a `main` function that looks
+// like this:
+//
+// ```
+// #[export_name = "main"]
+// pub extern "C" fn rustc_main(argc: isize, argv: *const *const u8) -> isize {
+//     start(main)
+// }
+// ```
+//
+// Where `start` is this function and `main` is the binary crate's `main`
+// function.
+//
+// The final piece is that the entry point of our program, the reset handler,
+// has to call `rustc_main`. That's covered by the `reset_handler` function in
+// root of this crate.
+#[lang = "start"]
+extern "C" fn start(
+    main: fn(),
+    _argc: isize,
+    _argv: *const *const u8,
+) -> isize {
+    main();
+
+    0
+}
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
new file mode 100644
index 00000000..f0d60bb2
--- /dev/null
+++ b/riscv-rt/src/lib.rs
@@ -0,0 +1,343 @@
+//! Minimal startup / runtime for RISCV CPU's
+//!
+//! # Features
+//!
+//! This crate provides
+//!
+//! - Before main initialization of the `.bss` and `.data` sections.
+//!
+//! - Before main initialization of the FPU (for targets that have a FPU).
+//!
+//! - A `panic_fmt` implementation that just calls abort that you can opt into
+//!   through the "abort-on-panic" Cargo feature. If you don't use this feature
+//!   you'll have to provide the `panic_fmt` lang item yourself. Documentation
+//!   [here][1]
+//!
+//! [1]: https://doc.rust-lang.org/unstable-book/language-features/lang-items.html
+//!
+//! - A minimal `start` lang item to support the standard `fn main()`
+//!   interface. (The processor goes to sleep after returning from `main`)
+//!
+//! - A linker script that encodes the memory layout of a generic RISC-V
+//!   microcontroller. This linker script is missing some information that must
+//!   be supplied through a `memory.x` file (see example below).
+//!
+//! - A `_sheap` symbol at whose address you can locate a heap.
+//!
+//! ``` text
+//! $ cargo new --bin app && cd $_
+//!
+//! $ # add this crate as a dependency
+//! $ edit Cargo.toml && cat $_
+//! [dependencies.riscv-rt]
+//! version = "0.1.0"
+//!
+//! $ # tell Xargo which standard crates to build
+//! $ edit Xargo.toml && cat $_
+//! [dependencies.core]
+//! stage = 0
+//!
+//! [dependencies.compiler_builtins]
+//! features = ["mem"]
+//! stage = 1
+//!
+//! $ # memory layout of the device
+//! $ edit memory.x && cat $_
+//! MEMORY
+//! {
+//!   /* NOTE K = KiBi = 1024 bytes */
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 128K
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 8K
+//! }
+//!
+//! $ edit src/main.rs && cat $_
+//! ```
+//!
+//! ``` ignore,no_run
+//! #![no_std]
+//!
+//! extern crate riscv_rt;
+//!
+//! fn main() {
+//!     // do something here
+//! }
+//! ```
+//!
+//! ``` text
+//! $ cargo install xargo
+//!
+//! $ xargo rustc --target riscv32-unknown-none -- \
+//!    -C link-arg=-Tlink.x -C linker=riscv32-unknown-elf-ld -Z linker-flavor=ld
+//!
+//! $ riscv32-unknown-elf-objdump -Cd $(find target -name app) | head
+//!
+//! Disassembly of section .text:
+//!
+//! 20400000 <_start>:
+//! 20400000:	800011b7    lui	gp,0x80001
+//! 20400004:	80018193    addi	gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
+//! 20400008:	80004137    lui	sp,0x80004
+//! ```
+//!
+//! # Symbol interfaces
+//!
+//! This crate makes heavy use of symbols, linker sections and linker scripts to
+//! provide most of its functionality. Below are described the main symbol
+//! interfaces.
+//!
+//! ## `memory.x`
+//!
+//! This file supplies the information about the device to the linker.
+//!
+//! ### `MEMORY`
+//!
+//! The main information that this file must provide is the memory layout of
+//! the device in the form of the `MEMORY` command. The command is documented
+//! [here][2], but at a minimum you'll want to create two memory regions: one
+//! for Flash memory and another for RAM.
+//!
+//! [2]: https://sourceware.org/binutils/docs/ld/MEMORY.html
+//!
+//! The program instructions (the `.text` section) will be stored in the memory
+//! region named FLASH, and the program `static` variables (the sections `.bss`
+//! and `.data`) will be allocated in the memory region named RAM.
+//!
+//! ### `_stack_start`
+//!
+//! This symbol provides the address at which the call stack will be allocated.
+//! The call stack grows downwards so this address is usually set to the highest
+//! valid RAM address plus one (this *is* an invalid address but the processor
+//! will decrement the stack pointer *before* using its value as an address).
+//!
+//! If omitted this symbol value will default to `ORIGIN(RAM) + LENGTH(RAM)`.
+//!
+//! #### Example
+//!
+//! Allocating the call stack on a different RAM region.
+//!
+//! ```
+//! MEMORY
+//! {
+//!   /* call stack will go here */
+//!   CCRAM : ORIGIN = 0x10000000, LENGTH = 8K
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+//!   /* static variables will go here */
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 40K
+//! }
+//!
+//! _stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
+//! ```
+//!
+//! ### `_sheap`
+//!
+//! This symbol is located in RAM right after the `.bss` and `.data` sections.
+//! You can use the address of this symbol as the start address of a heap
+//! region. This symbol is 4 byte aligned so that address will be a multiple of
+//! 4.
+//!
+//! #### Example
+//!
+//! ```
+//! extern crate some_allocator;
+//!
+//! // Size of the heap in bytes
+//! const SIZE: usize = 1024;
+//!
+//! extern "C" {
+//!     static mut _sheap: u8;
+//! }
+//!
+//! fn main() {
+//!     unsafe {
+//!         let start_address = &mut _sheap as *mut u8;
+//!         some_allocator::initialize(start_address, SIZE);
+//!     }
+//! }
+//! ```
+
+// NOTE: Adapted from cortex-m/src/lib.rs
+#![no_std]
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![feature(asm)]
+#![feature(compiler_builtins_lib)]
+#![feature(const_fn)]
+#![feature(global_asm)]
+#![feature(lang_items)]
+#![feature(linkage)]
+#![feature(naked_functions)]
+#![feature(used)]
+
+extern crate compiler_builtins;
+extern crate riscv;
+extern crate r0;
+
+mod lang_items;
+
+use riscv::{asm, csr};
+pub use riscv::csr::{Trap, Interrupt, Exception};
+
+extern "C" {
+    // NOTE `rustc` forces this signature on us. See `src/lang_items.rs`
+    fn main(argc: isize, argv: *const *const u8) -> isize;
+
+    // Boundaries of the .bss section
+    static mut _ebss: u32;
+    static mut _sbss: u32;
+
+    // Boundaries of the .data section
+    static mut _edata: u32;
+    static mut _sdata: u32;
+
+    // Initial values of the .data section (stored in Flash)
+    static _sidata: u32;
+
+    // Address of _start_trap
+    static _start_trap: u32;
+}
+
+
+/// Entry point of all programs (_start).
+///
+/// It initializes DWARF call frame information, the stack pointer, the
+/// frame pointer (needed for closures to work in start_rust) and the global
+/// pointer. Then it calls _start_rust.
+// FIXME: .option push, .option norelax and .option pop directives aren't
+// supported by the llvm backend yet.
+global_asm!(r#"
+.section .init
+.globl _start
+_start:
+  .cfi_startproc
+  .cfi_undefined ra
+
+  // .option push
+  // .option norelax
+  lui gp, %hi(__global_pointer$)
+  addi gp, gp, %lo(__global_pointer$)
+  // .option pop
+
+  lui sp, %hi(_stack_start)
+  addi sp, sp, %lo(_stack_start)
+
+  add s0, sp, zero
+
+  jal zero, _start_rust
+
+  .cfi_endproc
+"#);
+
+
+/// Rust entry point (_start_rust)
+///
+/// Zeros bss section, initializes data section and calls main. This function
+/// never returns.
+#[naked]
+#[link_section = ".init.rust"]
+#[export_name = "_start_rust"]
+pub extern "C" fn start_rust() -> ! {
+    unsafe {
+        r0::zero_bss(&mut _sbss, &mut _ebss);
+        r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+    }
+
+    // TODO: Enable FPU when available
+
+    // Set mtvec to _start_trap
+    unsafe {
+        // csr::mtvec.write(|w| w.bits(_start_trap));
+        asm!("csrrw zero, 0x305, $0"
+             :
+             : "r"(&_start_trap)
+             :
+             : "volatile");
+    }
+
+    // Neither `argc` or `argv` make sense in bare metal context so we
+    // just stub them
+    unsafe {
+        main(0, ::core::ptr::null());
+    }
+
+    // If `main` returns, then we go into "reactive" mode and simply attend
+    // interrupts as they occur.
+    loop {
+        asm::wfi();
+    }
+}
+
+
+/// Trap entry point (_start_trap)
+///
+/// Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
+/// restores caller saved registers and then returns.
+global_asm!(r#"
+  .section .trap
+  .align 4
+  .global _start_trap
+
+_start_trap:
+  addi sp, sp, -16*4
+
+  sw ra, 1*4(sp)
+  sw t0, 2*4(sp)
+  sw t1, 3*4(sp)
+  sw t2, 4*4(sp)
+  sw t3, 5*4(sp)
+  sw t4, 6*4(sp)
+  sw t5, 7*4(sp)
+  sw t6, 8*4(sp)
+  sw a0, 9*4(sp)
+  sw a1, 10*4(sp)
+  sw a2, 11*4(sp)
+  sw a3, 12*4(sp)
+  sw a4, 13*4(sp)
+  sw a5, 14*4(sp)
+  sw a6, 15*4(sp)
+  sw a7, 16*4(sp)
+
+  jal ra, _start_trap_rust
+
+  lw ra, 1*4(sp)
+  lw t0, 2*4(sp)
+  lw t1, 3*4(sp)
+  lw t2, 4*4(sp)
+  lw t3, 5*4(sp)
+  lw t4, 6*4(sp)
+  lw t5, 7*4(sp)
+  lw t6, 8*4(sp)
+  lw a0, 9*4(sp)
+  lw a1, 10*4(sp)
+  lw a2, 11*4(sp)
+  lw a3, 12*4(sp)
+  lw a4, 13*4(sp)
+  lw a5, 14*4(sp)
+  lw a6, 15*4(sp)
+  lw a7, 16*4(sp)
+
+  addi sp, sp, 16*4
+  mret
+"#);
+
+
+/// Trap entry point rust (_start_trap_rust)
+///
+/// mcause is read to determine the cause of the trap. XLEN-1 bit indicates
+/// if it's an interrupt or an exception. The result is converted to an element
+/// of the Interrupt or Exception enum and passed to handle_interrupt or
+/// handle_exception.
+#[link_section = ".trap.rust"]
+#[export_name = "_start_trap_rust"]
+pub extern "C" fn start_trap_rust() {
+    // dispatch trap to handler
+    trap_handler(csr::mcause.read().cause());
+    // mstatus, remain in M-mode after mret
+    csr::mstatus.set(|w| w.mpp(csr::MPP::Machine));
+}
+
+
+/// Default Trap Handler
+#[used]
+#[no_mangle]
+#[linkage = "weak"]
+fn trap_handler(_: Trap) {}

From a7f61b8a1c7301cfd54f95769376fbd287c4785c Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 18 Nov 2017 09:48:52 +0100
Subject: [PATCH 002/234] Allow compiling on x86_64 for publishing.

---
 riscv-rt/Cargo.toml | 2 +-
 riscv-rt/src/lib.rs | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index ac543add..3e1882f8 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,4 +10,4 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.1"
-riscv = "0.1.0"
+riscv = "0.1.1"
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index f0d60bb2..be49dbef 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -202,8 +202,7 @@ extern "C" {
 /// It initializes DWARF call frame information, the stack pointer, the
 /// frame pointer (needed for closures to work in start_rust) and the global
 /// pointer. Then it calls _start_rust.
-// FIXME: .option push, .option norelax and .option pop directives aren't
-// supported by the llvm backend yet.
+#[cfg(target_arch = "riscv")]
 global_asm!(r#"
 .section .init
 .globl _start
@@ -244,6 +243,7 @@ pub extern "C" fn start_rust() -> ! {
     // TODO: Enable FPU when available
 
     // Set mtvec to _start_trap
+    #[cfg(target_arch = "riscv")]
     unsafe {
         // csr::mtvec.write(|w| w.bits(_start_trap));
         asm!("csrrw zero, 0x305, $0"
@@ -271,6 +271,7 @@ pub extern "C" fn start_rust() -> ! {
 ///
 /// Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
 /// restores caller saved registers and then returns.
+#[cfg(target_arch = "riscv")]
 global_asm!(r#"
   .section .trap
   .align 4

From 1f4dc285e7a8410f701e6437ef9c60bf18724f9e Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 18 Nov 2017 09:49:36 +0100
Subject: [PATCH 003/234] Bump version to 0.1.1

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 3e1882f8..4fa3546d 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.1.0"
+version = "0.1.1"
 repository = "https://github.com/dvc94ch/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]

From 984abfd6e8ac60bc3da7681ed17009346f6fce20 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 18 Nov 2017 14:11:52 +0100
Subject: [PATCH 004/234] Bump version to 0.1.2

---
 riscv-rt/Cargo.toml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 4fa3546d..05f9649c 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.1.1"
+version = "0.1.2"
 repository = "https://github.com/dvc94ch/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]
@@ -9,5 +9,5 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 
 [dependencies]
-r0 = "0.2.1"
-riscv = "0.1.1"
+r0 = "^0.2.1"
+riscv = "^0.1.1"

From 801cb5a16bf0bfa96c0ce8f8c8e56ebd53386332 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 18 Nov 2017 14:25:39 +0100
Subject: [PATCH 005/234] Bump version to 0.1.3

---
 riscv-rt/Cargo.toml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 05f9649c..c5aa5817 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.1.2"
+version = "0.1.3"
 repository = "https://github.com/dvc94ch/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]
@@ -10,4 +10,4 @@ license = "ISC"
 
 [dependencies]
 r0 = "^0.2.1"
-riscv = "^0.1.1"
+riscv = "^0.1.3"

From f210ac26b1719c8ebb406611cd40cc756c1b9811 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Mon, 20 Nov 2017 14:32:45 +0100
Subject: [PATCH 006/234] Use git version.

---
 riscv-rt/Cargo.toml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index c5aa5817..80e6c534 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,4 +10,6 @@ license = "ISC"
 
 [dependencies]
 r0 = "^0.2.1"
-riscv = "^0.1.3"
+
+[dependencies.riscv]
+git = "https://github.com/dvc94ch/riscv"

From d0e2bab6098839ebc41e1004ab9dd7ea6c86fb59 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Tue, 21 Nov 2017 10:56:45 +0100
Subject: [PATCH 007/234] Fix stack calculation.

---
 riscv-rt/src/lib.rs | 64 ++++++++++++++++++++++-----------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index be49dbef..07869181 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -280,41 +280,41 @@ global_asm!(r#"
 _start_trap:
   addi sp, sp, -16*4
 
-  sw ra, 1*4(sp)
-  sw t0, 2*4(sp)
-  sw t1, 3*4(sp)
-  sw t2, 4*4(sp)
-  sw t3, 5*4(sp)
-  sw t4, 6*4(sp)
-  sw t5, 7*4(sp)
-  sw t6, 8*4(sp)
-  sw a0, 9*4(sp)
-  sw a1, 10*4(sp)
-  sw a2, 11*4(sp)
-  sw a3, 12*4(sp)
-  sw a4, 13*4(sp)
-  sw a5, 14*4(sp)
-  sw a6, 15*4(sp)
-  sw a7, 16*4(sp)
+  sw ra, 0*4(sp)
+  sw t0, 1*4(sp)
+  sw t1, 2*4(sp)
+  sw t2, 3*4(sp)
+  sw t3, 4*4(sp)
+  sw t4, 5*4(sp)
+  sw t5, 6*4(sp)
+  sw t6, 7*4(sp)
+  sw a0, 8*4(sp)
+  sw a1, 9*4(sp)
+  sw a2, 10*4(sp)
+  sw a3, 11*4(sp)
+  sw a4, 12*4(sp)
+  sw a5, 13*4(sp)
+  sw a6, 14*4(sp)
+  sw a7, 15*4(sp)
 
   jal ra, _start_trap_rust
 
-  lw ra, 1*4(sp)
-  lw t0, 2*4(sp)
-  lw t1, 3*4(sp)
-  lw t2, 4*4(sp)
-  lw t3, 5*4(sp)
-  lw t4, 6*4(sp)
-  lw t5, 7*4(sp)
-  lw t6, 8*4(sp)
-  lw a0, 9*4(sp)
-  lw a1, 10*4(sp)
-  lw a2, 11*4(sp)
-  lw a3, 12*4(sp)
-  lw a4, 13*4(sp)
-  lw a5, 14*4(sp)
-  lw a6, 15*4(sp)
-  lw a7, 16*4(sp)
+  lw ra, 0*4(sp)
+  lw t0, 1*4(sp)
+  lw t1, 2*4(sp)
+  lw t2, 3*4(sp)
+  lw t3, 4*4(sp)
+  lw t4, 5*4(sp)
+  lw t5, 6*4(sp)
+  lw t6, 7*4(sp)
+  lw a0, 8*4(sp)
+  lw a1, 9*4(sp)
+  lw a2, 10*4(sp)
+  lw a3, 11*4(sp)
+  lw a4, 12*4(sp)
+  lw a5, 13*4(sp)
+  lw a6, 14*4(sp)
+  lw a7, 15*4(sp)
 
   addi sp, sp, 16*4
   mret

From 218d27bbd32b171118c2ba22ce9c83741adbdf6b Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Fri, 23 Feb 2018 11:28:31 +0100
Subject: [PATCH 008/234] Add termination trait to lang-items.

---
 riscv-rt/Cargo.toml        |  4 +---
 riscv-rt/src/lang_items.rs | 19 ++++++++++++++++---
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 80e6c534..0c6e5444 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,6 +10,4 @@ license = "ISC"
 
 [dependencies]
 r0 = "^0.2.1"
-
-[dependencies.riscv]
-git = "https://github.com/dvc94ch/riscv"
+riscv = { path = "../riscv" }
diff --git a/riscv-rt/src/lang_items.rs b/riscv-rt/src/lang_items.rs
index 20e0f3fe..eb8093ac 100644
--- a/riscv-rt/src/lang_items.rs
+++ b/riscv-rt/src/lang_items.rs
@@ -3,7 +3,6 @@
 use riscv::asm;
 
 /// Default panic handler
-#[linkage = "weak"]
 #[lang = "panic_fmt"]
 unsafe extern "C" fn panic_fmt(
     _: ::core::fmt::Arguments, // fmt
@@ -34,12 +33,26 @@ unsafe extern "C" fn panic_fmt(
 // has to call `rustc_main`. That's covered by the `reset_handler` function in
 // root of this crate.
 #[lang = "start"]
-extern "C" fn start(
+extern "C" fn lang_start<T>(
     main: fn(),
     _argc: isize,
     _argv: *const *const u8,
-) -> isize {
+) -> isize
+    where
+    T: Termination,
+{
     main();
 
     0
 }
+
+#[lang = "termination"]
+pub trait Termination {
+    fn report(self) -> i32;
+}
+
+impl Termination for () {
+    fn report(self) -> i32 {
+        0
+    }
+}

From 3dd9eee3460e614ee1dc98d95fe44bc2127e99fe Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Tue, 27 Mar 2018 20:15:49 +0200
Subject: [PATCH 009/234] Update to new riscv api.

---
 riscv-rt/src/lib.rs | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 07869181..9a82f988 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -174,8 +174,8 @@ extern crate r0;
 
 mod lang_items;
 
-use riscv::{asm, csr};
-pub use riscv::csr::{Trap, Interrupt, Exception};
+use riscv::asm;
+use riscv::register::{mcause, mstatus, mtvec};
 
 extern "C" {
     // NOTE `rustc` forces this signature on us. See `src/lang_items.rs`
@@ -245,12 +245,7 @@ pub extern "C" fn start_rust() -> ! {
     // Set mtvec to _start_trap
     #[cfg(target_arch = "riscv")]
     unsafe {
-        // csr::mtvec.write(|w| w.bits(_start_trap));
-        asm!("csrrw zero, 0x305, $0"
-             :
-             : "r"(&_start_trap)
-             :
-             : "volatile");
+        mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
     }
 
     // Neither `argc` or `argv` make sense in bare metal context so we
@@ -331,9 +326,11 @@ _start_trap:
 #[export_name = "_start_trap_rust"]
 pub extern "C" fn start_trap_rust() {
     // dispatch trap to handler
-    trap_handler(csr::mcause.read().cause());
+    trap_handler(mcause::read().cause());
     // mstatus, remain in M-mode after mret
-    csr::mstatus.set(|w| w.mpp(csr::MPP::Machine));
+    unsafe {
+        mstatus::set_mpp(mstatus::MPP::Machine);
+    }
 }
 
 
@@ -341,4 +338,4 @@ pub extern "C" fn start_trap_rust() {
 #[used]
 #[no_mangle]
 #[linkage = "weak"]
-fn trap_handler(_: Trap) {}
+fn trap_handler(_: mcause::Trap) {}

From c7b2bbbe4df1fd3b65729f8fec4cc321a9ec0d12 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Wed, 28 Mar 2018 17:52:49 +0200
Subject: [PATCH 010/234] Revert mtvec.

---
 riscv-rt/src/lib.rs | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 9a82f988..a91bf657 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -175,7 +175,7 @@ extern crate r0;
 mod lang_items;
 
 use riscv::asm;
-use riscv::register::{mcause, mstatus, mtvec};
+use riscv::register::{mcause, mstatus};
 
 extern "C" {
     // NOTE `rustc` forces this signature on us. See `src/lang_items.rs`
@@ -245,7 +245,12 @@ pub extern "C" fn start_rust() -> ! {
     // Set mtvec to _start_trap
     #[cfg(target_arch = "riscv")]
     unsafe {
-        mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
+        //mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
+        asm!("csrrw zero, 0x305, $0"
+             :
+             : "r"(&_start_trap)
+             :
+             : "volatile");
     }
 
     // Neither `argc` or `argv` make sense in bare metal context so we

From 03dec09e183dc3e0dfd15903083ac53f908b4a25 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 31 Mar 2018 11:48:29 +0200
Subject: [PATCH 011/234] Show heap/stack size.

---
 riscv-rt/link.x | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 6fb76b98..5af49bf1 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -25,15 +25,15 @@ SECTIONS
     . = ALIGN(4);
   } > FLASH
 
-  .bss : ALIGN(4)
+  PROVIDE(_sbss = ORIGIN(RAM));
+  .bss _sbss : ALIGN(4)
   {
-    _sbss = .;
     *(.bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
   } > RAM
 
-  .data : ALIGN(4)
+  .data _ebss : ALIGN(4)
   {
     _sidata = LOADADDR(.data);
     _sdata = .;
@@ -44,6 +44,25 @@ SECTIONS
     _edata = .;
   } > RAM AT > FLASH /* LLD fails on AT > FLASH */
 
+  PROVIDE(_heap_size = 0);
+
+  /* fictitious region that represents the memory available for the heap */
+  .heap _edata (INFO) : ALIGN(4)
+  {
+    _sheap = .;
+    . += _heap_size;
+    . = ALIGN(4);
+    _eheap = .;
+  }
+
+  /* fictitious region that represents the memory available for the stack */
+  .stack _eheap (INFO) : ALIGN(4)
+  {
+    _estack = .;
+    . = _stack_start;
+    _sstack = .;
+  }
+
   /* fake output .got section */
   /* Dynamic relocations are unsupported. This section is only used to detect
      relocatable code in the input files and raise an error if relocatable code
@@ -55,8 +74,6 @@ SECTIONS
     _egot = .;
   } > RAM AT > FLASH /* LLD fails on AT > FLASH */
 
-  /* The heap starts right after the .bss + .data section ends */
-  _sheap = _edata;
 
   /* Due to an unfortunate combination of legacy concerns,
      toolchain drawbacks, and insufficient attention to detail,

From 030c12f3600d2630b96670ad72c04dfb6aa8809e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Emil=20Gardstr=C3=B6m?= <emil.gardstrom@gmail.com>
Date: Tue, 24 Apr 2018 22:23:53 +0200
Subject: [PATCH 012/234] Fix for newest breakage, closes #3

---
 riscv-rt/Cargo.toml |  4 ++++
 riscv-rt/build.rs   | 10 ++++++++++
 riscv-rt/src/lib.rs |  3 ++-
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 0c6e5444..6a13a681 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,3 +11,7 @@ license = "ISC"
 [dependencies]
 r0 = "^0.2.1"
 riscv = { path = "../riscv" }
+
+[build-dependencies]
+rustc_version = "0.2.1"
+chrono = "0.4.0"
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 4cd56c63..4b615413 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,10 +1,20 @@
+extern crate chrono;
+extern crate rustc_version;
+
 // NOTE: Adapted from cortex-m/build.rs
 use std::env;
 use std::fs::File;
 use std::io::Write;
 use std::path::PathBuf;
 
+use chrono::NaiveDate;
+
 fn main() {
+    let meta = rustc_version::version_meta().unwrap();
+	// newest nightlies don't need 'extern crate compiler_builtins'
+    if meta.commit_date.unwrap().parse::<NaiveDate>().unwrap() < NaiveDate::from_ymd(2018, 04, 07) {
+        println!("cargo:rustc-cfg=needs_cb")
+    }
     // Put the linker script somewhere the linker can find it
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     File::create(out.join("link.x"))
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index a91bf657..92610b36 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -160,7 +160,7 @@
 #![deny(missing_docs)]
 #![deny(warnings)]
 #![feature(asm)]
-#![feature(compiler_builtins_lib)]
+#![cfg_attr(needs_cb, feature(compiler_builtins_lib))]
 #![feature(const_fn)]
 #![feature(global_asm)]
 #![feature(lang_items)]
@@ -168,6 +168,7 @@
 #![feature(naked_functions)]
 #![feature(used)]
 
+#[cfg(needs_cb)]
 extern crate compiler_builtins;
 extern crate riscv;
 extern crate r0;

From 944d65e9420142a0199fffbdc4d5b7c3225f60ed Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Tue, 24 Jul 2018 16:03:16 +0200
Subject: [PATCH 013/234] Revert "Fix for newest breakage, closes #3"

This reverts commit 030c12f3600d2630b96670ad72c04dfb6aa8809e.
---
 riscv-rt/Cargo.toml |  4 ----
 riscv-rt/build.rs   | 10 ----------
 riscv-rt/src/lib.rs |  3 +--
 3 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 6a13a681..0c6e5444 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,7 +11,3 @@ license = "ISC"
 [dependencies]
 r0 = "^0.2.1"
 riscv = { path = "../riscv" }
-
-[build-dependencies]
-rustc_version = "0.2.1"
-chrono = "0.4.0"
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 4b615413..4cd56c63 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,20 +1,10 @@
-extern crate chrono;
-extern crate rustc_version;
-
 // NOTE: Adapted from cortex-m/build.rs
 use std::env;
 use std::fs::File;
 use std::io::Write;
 use std::path::PathBuf;
 
-use chrono::NaiveDate;
-
 fn main() {
-    let meta = rustc_version::version_meta().unwrap();
-	// newest nightlies don't need 'extern crate compiler_builtins'
-    if meta.commit_date.unwrap().parse::<NaiveDate>().unwrap() < NaiveDate::from_ymd(2018, 04, 07) {
-        println!("cargo:rustc-cfg=needs_cb")
-    }
     // Put the linker script somewhere the linker can find it
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     File::create(out.join("link.x"))
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 92610b36..a91bf657 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -160,7 +160,7 @@
 #![deny(missing_docs)]
 #![deny(warnings)]
 #![feature(asm)]
-#![cfg_attr(needs_cb, feature(compiler_builtins_lib))]
+#![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
 #![feature(global_asm)]
 #![feature(lang_items)]
@@ -168,7 +168,6 @@
 #![feature(naked_functions)]
 #![feature(used)]
 
-#[cfg(needs_cb)]
 extern crate compiler_builtins;
 extern crate riscv;
 extern crate r0;

From 07bd42efe035dc1e682019cff53c0add2f81b461 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Tue, 24 Jul 2018 17:49:40 +0200
Subject: [PATCH 014/234] Update to latest nightly.

---
 riscv-rt/src/lang_items.rs |  9 ++-------
 riscv-rt/src/lib.rs        | 15 ++++++++++++---
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/riscv-rt/src/lang_items.rs b/riscv-rt/src/lang_items.rs
index eb8093ac..4fbe64d3 100644
--- a/riscv-rt/src/lang_items.rs
+++ b/riscv-rt/src/lang_items.rs
@@ -3,13 +3,8 @@
 use riscv::asm;
 
 /// Default panic handler
-#[lang = "panic_fmt"]
-unsafe extern "C" fn panic_fmt(
-    _: ::core::fmt::Arguments, // fmt
-    _: &'static str, // file
-    _: u32, // line
-    _: u32, // col
-) -> ! {
+#[panic_implementation]
+fn panic_fmt(_info: &core::panic::PanicInfo) -> ! {
     asm::ebreak();
     loop {}
 }
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index a91bf657..ca17f931 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -162,13 +162,14 @@
 #![feature(asm)]
 #![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
+#![feature(extern_prelude)]
 #![feature(global_asm)]
 #![feature(lang_items)]
 #![feature(linkage)]
 #![feature(naked_functions)]
+#![feature(panic_implementation)]
 #![feature(used)]
 
-extern crate compiler_builtins;
 extern crate riscv;
 extern crate r0;
 
@@ -340,7 +341,15 @@ pub extern "C" fn start_trap_rust() {
 
 
 /// Default Trap Handler
-#[used]
 #[no_mangle]
 #[linkage = "weak"]
-fn trap_handler(_: mcause::Trap) {}
+pub fn trap_handler(_: mcause::Trap) {}
+
+// Make sure there is an abort when linking
+#[cfg(target_arch = "riscv")]
+global_asm!(r#"
+.section .init
+.globl abort
+abort:
+  jal zero, _start
+"#);

From 4a01db823abb88d7a488ca381ff033d153642822 Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Sat, 4 Aug 2018 21:57:15 +1000
Subject: [PATCH 015/234] fix target_arch conditionals to match "riscv32" and
 "riscv64"

In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.

Include "riscv64" optimistically for future-proofing.
---
 riscv-rt/src/lib.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index ca17f931..31c54c04 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -203,7 +203,7 @@ extern "C" {
 /// It initializes DWARF call frame information, the stack pointer, the
 /// frame pointer (needed for closures to work in start_rust) and the global
 /// pointer. Then it calls _start_rust.
-#[cfg(target_arch = "riscv")]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 global_asm!(r#"
 .section .init
 .globl _start
@@ -244,7 +244,7 @@ pub extern "C" fn start_rust() -> ! {
     // TODO: Enable FPU when available
 
     // Set mtvec to _start_trap
-    #[cfg(target_arch = "riscv")]
+    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
     unsafe {
         //mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
         asm!("csrrw zero, 0x305, $0"
@@ -272,7 +272,7 @@ pub extern "C" fn start_rust() -> ! {
 ///
 /// Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
 /// restores caller saved registers and then returns.
-#[cfg(target_arch = "riscv")]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 global_asm!(r#"
   .section .trap
   .align 4
@@ -346,7 +346,7 @@ pub extern "C" fn start_trap_rust() {
 pub fn trap_handler(_: mcause::Trap) {}
 
 // Make sure there is an abort when linking
-#[cfg(target_arch = "riscv")]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 global_asm!(r#"
 .section .init
 .globl abort

From 081756847bf9b361d22ae1a817ab9c925ca3c546 Mon Sep 17 00:00:00 2001
From: Brad Campbell <bradjc5@gmail.com>
Date: Tue, 7 Aug 2018 17:22:32 -0400
Subject: [PATCH 016/234] lib: make main have no args

I'm not sure when this changed, but without this patch the app does not
seem to run, and with it the blinky_delay test app works as expected.

This is also how it looks in cortex-m-rt:
https://github.com/rust-embedded/cortex-m-rt/blob/6c269f195c9a705162fd912beb952b430cc28336/src/lib.rs#L468
---
 riscv-rt/src/lib.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 31c54c04..2d51f936 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -180,7 +180,7 @@ use riscv::register::{mcause, mstatus};
 
 extern "C" {
     // NOTE `rustc` forces this signature on us. See `src/lang_items.rs`
-    fn main(argc: isize, argv: *const *const u8) -> isize;
+    fn main() -> isize;
 
     // Boundaries of the .bss section
     static mut _ebss: u32;
@@ -257,7 +257,7 @@ pub extern "C" fn start_rust() -> ! {
     // Neither `argc` or `argv` make sense in bare metal context so we
     // just stub them
     unsafe {
-        main(0, ::core::ptr::null());
+        main();
     }
 
     // If `main` returns, then we go into "reactive" mode and simply attend

From e69a28327019f57e07e4662bd9c789b42060d66f Mon Sep 17 00:00:00 2001
From: Dan Callaghan <dcallagh@redhat.com>
Date: Fri, 10 Aug 2018 10:50:23 +1000
Subject: [PATCH 017/234] don't declare _start_rust as a "naked" function

The #[naked] attribute means Rust won't emit instructions to push and
pop a new stack frame. But the assembly routine which calls _start_rust
also doesn't push a new stack frame, so there is no valid stack for this
function.

We probably need a stack frame though, since it's implemented in Rust
and we can't easily ensure that Rust won't try to allocate any local
variables. See #5.
---
 riscv-rt/src/lib.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 2d51f936..1c870b53 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -166,7 +166,6 @@
 #![feature(global_asm)]
 #![feature(lang_items)]
 #![feature(linkage)]
-#![feature(naked_functions)]
 #![feature(panic_implementation)]
 #![feature(used)]
 
@@ -232,7 +231,6 @@ _start:
 ///
 /// Zeros bss section, initializes data section and calls main. This function
 /// never returns.
-#[naked]
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
 pub extern "C" fn start_rust() -> ! {

From 3270dd813f0625831e049bae24df71ef213190fe Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Fri, 10 Aug 2018 18:19:47 +1000
Subject: [PATCH 018/234] use #[no_main] and the entry! macro to specify the
 main function

Matches cortex-m-rt. See:

https://github.com/rust-embedded/cortex-m-rt/pull/69
https://github.com/rust-embedded/cortex-m-rt/pull/78
---
 riscv-rt/src/lib.rs | 47 +++++++++++++++++++++++++++++++++------------
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 1c870b53..cabb2cb5 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -55,10 +55,15 @@
 //!
 //! ``` ignore,no_run
 //! #![no_std]
+//! #![no_main]
 //!
+//! #[macro_use(entry)]
 //! extern crate riscv_rt;
 //!
-//! fn main() {
+//! // use `main` as the entry point of this application
+//! entry!(main);
+//!
+//! fn main() -> ! {
 //!     // do something here
 //! }
 //! ```
@@ -174,13 +179,9 @@ extern crate r0;
 
 mod lang_items;
 
-use riscv::asm;
 use riscv::register::{mcause, mstatus};
 
 extern "C" {
-    // NOTE `rustc` forces this signature on us. See `src/lang_items.rs`
-    fn main() -> isize;
-
     // Boundaries of the .bss section
     static mut _ebss: u32;
     static mut _sbss: u32;
@@ -234,6 +235,11 @@ _start:
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
 pub extern "C" fn start_rust() -> ! {
+    extern "C" {
+        // This symbol will be provided by the user via the `entry!` macro
+        fn main() -> !;
+    }
+
     unsafe {
         r0::zero_bss(&mut _sbss, &mut _ebss);
         r0::init_data(&mut _sdata, &mut _edata, &_sidata);
@@ -252,17 +258,34 @@ pub extern "C" fn start_rust() -> ! {
              : "volatile");
     }
 
-    // Neither `argc` or `argv` make sense in bare metal context so we
-    // just stub them
     unsafe {
         main();
     }
+}
 
-    // If `main` returns, then we go into "reactive" mode and simply attend
-    // interrupts as they occur.
-    loop {
-        asm::wfi();
-    }
+
+/// Macro to define the entry point of the program
+///
+/// **NOTE** This macro must be invoked once and must be invoked from an accessible module, ideally
+/// from the root of the crate.
+///
+/// Usage: `entry!(path::to::entry::point)`
+///
+/// The specified function will be called by the reset handler *after* RAM has been initialized.
+///
+/// The signature of the specified function must be `fn() -> !` (never ending function).
+#[macro_export]
+macro_rules! entry {
+    ($path:expr) => {
+        #[inline(never)]
+        #[export_name = "main"]
+        pub extern "C" fn __impl_main() -> ! {
+            // validate the signature of the program entry point
+            let f: fn() -> ! = $path;
+
+            f()
+        }
+    };
 }
 
 

From 130686e45bda915a349b6c76cbd2d7400af3cfc1 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sat, 11 Aug 2018 17:58:32 +0200
Subject: [PATCH 019/234] A unified contributing experience.

---
 riscv-rt/.github/CODEOWNERS |  1 +
 riscv-rt/.github/bors.toml  |  4 +++
 riscv-rt/.travis.yml        | 50 +++++++++++++++++++++++++++++++++++++
 riscv-rt/CODE_OF_CONDUCT.md | 37 +++++++++++++++++++++++++++
 riscv-rt/ci/install.sh      |  9 +++++++
 riscv-rt/ci/script.sh       | 11 ++++++++
 6 files changed, 112 insertions(+)
 create mode 100644 riscv-rt/.github/CODEOWNERS
 create mode 100644 riscv-rt/.github/bors.toml
 create mode 100644 riscv-rt/.travis.yml
 create mode 100644 riscv-rt/CODE_OF_CONDUCT.md
 create mode 100644 riscv-rt/ci/install.sh
 create mode 100644 riscv-rt/ci/script.sh

diff --git a/riscv-rt/.github/CODEOWNERS b/riscv-rt/.github/CODEOWNERS
new file mode 100644
index 00000000..87f6c03f
--- /dev/null
+++ b/riscv-rt/.github/CODEOWNERS
@@ -0,0 +1 @@
+* @rust-embedded/riscv
\ No newline at end of file
diff --git a/riscv-rt/.github/bors.toml b/riscv-rt/.github/bors.toml
new file mode 100644
index 00000000..ca42be0a
--- /dev/null
+++ b/riscv-rt/.github/bors.toml
@@ -0,0 +1,4 @@
+block_labels = ["needs-decision"]
+delete_merged_branches = true
+required_approvals = 1
+status = ["continuous-integration/travis-ci/push"]
diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
new file mode 100644
index 00000000..a3c9cf27
--- /dev/null
+++ b/riscv-rt/.travis.yml
@@ -0,0 +1,50 @@
+language: rust
+
+matrix:
+  include:
+    #- env: TARGET=x86_64-unknown-linux-gnu
+    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    #- env: TARGET=riscv32imac-unknown-none-elf
+    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    #- env: TARGET=x86_64-unknown-linux-gnu
+    #  rust: beta
+    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    #- env: TARGET=riscv32imac-unknown-none-elf
+    #  rust: beta
+    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    - env: TARGET=x86_64-unknown-linux-gnu
+      rust: nightly
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    - env: TARGET=riscv32imac-unknown-none-elf
+      rust: nightly
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+before_install: set -e
+
+install:
+  - bash ci/install.sh
+
+script:
+  - bash ci/script.sh
+
+after_script: set +e
+
+cache: cargo
+before_cache:
+  # Travis can't cache files that are not readable by "others"
+  - chmod -R a+r $HOME/.cargo
+
+branches:
+  only:
+    - master
+    - staging
+    - trying
+
+notifications:
+  email:
+    on_success: never
diff --git a/riscv-rt/CODE_OF_CONDUCT.md b/riscv-rt/CODE_OF_CONDUCT.md
new file mode 100644
index 00000000..a22c4f68
--- /dev/null
+++ b/riscv-rt/CODE_OF_CONDUCT.md
@@ -0,0 +1,37 @@
+# The Rust Code of Conduct
+
+## Conduct
+
+**Contact**: [RISCV team](https://github.com/rust-embedded/wg#the-riscv-team)
+
+* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic.
+* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all.
+* Please be kind and courteous. There's no need to be mean or rude.
+* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer.
+* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works.
+* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups.
+* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISCV team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
+* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome.
+
+## Moderation
+
+These are the policies for upholding our community's standards of conduct.
+
+1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.)
+2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed.
+3. Moderators will first respond to such remarks with a warning.
+4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off.
+5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded.
+6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology.
+7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed.
+8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others.
+
+In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely.
+
+And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust.
+
+The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org).
+
+*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).*
+
+[team]: https://github.com/rust-embedded/wg#the-riscv-team
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
new file mode 100644
index 00000000..3c419211
--- /dev/null
+++ b/riscv-rt/ci/install.sh
@@ -0,0 +1,9 @@
+set -euxo pipefail
+
+main() {
+    if [ $TARGET != x86_64-unknown-linux-gnu ]; then
+        rustup target add $TARGET
+    fi
+}
+
+main
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
new file mode 100644
index 00000000..eb1a3139
--- /dev/null
+++ b/riscv-rt/ci/script.sh
@@ -0,0 +1,11 @@
+set -euxo pipefail
+
+main() {
+    cargo check --target $TARGET
+
+    if [ $TRAVIS_RUST_VERSION = nightly ]; then
+        cargo check --target $TARGET --features inline-asm
+    fi
+}
+
+main

From 29f304be0495d8706f8107219e1ce9bd6227347e Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sun, 12 Aug 2018 09:23:03 +0200
Subject: [PATCH 020/234] Bump version, update deps and url.

---
 riscv-rt/Cargo.toml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 0c6e5444..d49f0543 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 name = "riscv-rt"
-version = "0.1.3"
-repository = "https://github.com/dvc94ch/riscv-rt"
+version = "0.2.0"
+repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISCV CPU's"
@@ -9,5 +9,5 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 
 [dependencies]
-r0 = "^0.2.1"
-riscv = { path = "../riscv" }
+r0 = "0.2.2"
+riscv = "0.3.0"

From 5d0ab8ff87a3a03638fdd18453f74dd97dd70720 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sun, 12 Aug 2018 09:26:27 +0200
Subject: [PATCH 021/234] Update README.

---
 riscv-rt/README.md | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index 1adfd84c..d98b9822 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -1,9 +1,18 @@
+[![crates.io](https://img.shields.io/crates/d/riscv-rt.svg)](https://crates.io/crates/riscv-rt)
+[![crates.io](https://img.shields.io/crates/v/riscv-rt.svg)](https://crates.io/crates/riscv-rt)
+[![Build Status](https://travis-ci.org/rust-embedded/riscv-rt.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv-rt)
+
 # `riscv-rt`
 
 > Minimal runtime / startup for RISCV CPU's.
 
-# License
-Copyright 2017 David Craven
+This project is developed and maintained by the [RISCV team][team].
+
+## [Documentation](https://docs.rs/crate/riscv-rt)
+
+## License
+
+Copyright 2018 [RISCV team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -16,3 +25,12 @@ INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
 THIS SOFTWARE.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [RISCV team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: CODE_OF_CONDUCT.md
+[team]: https://github.com/rust-embedded/wg#the-riscv-team

From aa092421a3ac335c5fca6529b8a082f89602e9e2 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sun, 12 Aug 2018 09:27:58 +0200
Subject: [PATCH 022/234] Add inline-asm feature.

---
 riscv-rt/Cargo.toml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index d49f0543..7af9e563 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,3 +11,6 @@ license = "ISC"
 [dependencies]
 r0 = "0.2.2"
 riscv = "0.3.0"
+
+[features]
+inline-asm = []
\ No newline at end of file

From a6c53d65feb3f53b88d9d39df215b8a4a4337f35 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Sun, 12 Aug 2018 09:42:28 +0200
Subject: [PATCH 023/234] Bump version.

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 7af9e563..bb6a35cd 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.2.0"
+version = "0.3.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]

From 353894662c446f04c5799a5be6edb257abc27b47 Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Sat, 23 Jun 2018 17:41:49 +1000
Subject: [PATCH 024/234] mark .init and .trap sections as executable

This is needed for lld, otherwise it will complain about section flag
mismatch:

    ld.lld: error: incompatible section flags for .text
    >>> target/riscv32imac-unknown-none/debug/deps/libriscv_rt-7850ee1a6233fbe9.rlib(riscv_rt-7850ee1a6233fbe9.4tmuw4s4crjeqbm5.rcgu.o):(.trap): 0x4
    >>> output section .text: 0x6
---
 riscv-rt/src/lib.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index cabb2cb5..822d9ca0 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -205,7 +205,7 @@ extern "C" {
 /// pointer. Then it calls _start_rust.
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 global_asm!(r#"
-.section .init
+.section .init, "ax"
 .globl _start
 _start:
   .cfi_startproc
@@ -295,7 +295,7 @@ macro_rules! entry {
 /// restores caller saved registers and then returns.
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 global_asm!(r#"
-  .section .trap
+  .section .trap, "ax"
   .align 4
   .global _start_trap
 

From 24290f1fd5da59bb59f3a599107df49b2c2d7aa2 Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Sun, 24 Jun 2018 14:53:48 +1000
Subject: [PATCH 025/234] remove hackery for .debug_gdb_scripts section

This is no longer necessary now that we can configure the target to
exclude the .debug_gdb_scripts section.
See: https://github.com/rust-lang/rust/pull/53139
---
 riscv-rt/link.x | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 5af49bf1..6458683f 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -73,22 +73,6 @@ SECTIONS
     KEEP(*(.got .got.*));
     _egot = .;
   } > RAM AT > FLASH /* LLD fails on AT > FLASH */
-
-
-  /* Due to an unfortunate combination of legacy concerns,
-     toolchain drawbacks, and insufficient attention to detail,
-     rustc has no choice but to mark .debug_gdb_scripts as allocatable.
-     We really do not want to upload it to our target, so we
-     remove the allocatable bit. Unfortunately, it appears
-     that the only way to do this in a linker script is
-     the extremely obscure "INFO" output section type specifier. */
-  /* a rustc hack will force the program to read the first byte of this section,
-     so we'll set the (fake) start address of this section to something we're
-     sure can be read at runtime: the start of the .text section */
-  /* LLD fails to parse _stext (INFO) */
-  .debug_gdb_scripts _stext (INFO) : {
-    KEEP(*(.debug_gdb_scripts))
-  }
 }
 
 /* Do not exceed this mark in the error messages below                | */

From 9b5c0cd41be6b98d5421bbf94ec799d159775beb Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Mon, 13 Aug 2018 22:38:29 +1000
Subject: [PATCH 026/234] align VMA not LMA

This aligns the VMA (virtual adddress at runtime):

    .rodata ALIGN(4) :
    {
        ...

whereas this aligns the LMA (load address):

    .rodata : ALIGN(4)
    {
        ...

If we ensure the VMA is aligned the linker will keep the corresponding
LMA in sync (and it will be aligned too).

Previously, by forcing the LMA to be aligned but leaving the VMA
unspecified, the linker would split .text and .rodata into two
separate loads because their addresses fell out of sync.
---
 riscv-rt/link.x | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 6458683f..6a666da0 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -7,7 +7,7 @@ SECTIONS
 {
   PROVIDE(_stext = ORIGIN(FLASH));
 
-  .text _stext : ALIGN(4)
+  .text ALIGN(_stext,4) :
   {
     /* Put reset handler first in .text section so it ends up as the entry */
     /* point of the program. */
@@ -19,21 +19,20 @@ SECTIONS
     *(.text .text.*);
   } > FLASH
 
-  .rodata : ALIGN(4)
+  .rodata ALIGN(4) :
   {
     *(.rodata .rodata.*);
-    . = ALIGN(4);
   } > FLASH
 
   PROVIDE(_sbss = ORIGIN(RAM));
-  .bss _sbss : ALIGN(4)
+  .bss ALIGN(_sbss,4) :
   {
     *(.bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
   } > RAM
 
-  .data _ebss : ALIGN(4)
+  .data _ebss :
   {
     _sidata = LOADADDR(.data);
     _sdata = .;

From 19254fa9b32ae372366eb71aa3c1efeaa181c84b Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Wed, 15 Aug 2018 14:38:35 +1000
Subject: [PATCH 027/234] discard .eh_frame sections

The .cfi_* assembler directives cause call frame information to be
emitted in a special .eh_frame section. But this is not needed in the
final binary, because we are not doing panic unwinding.

GNU ld already discards this section with its (default) --gc-sections
behaviour. Lld doesn't do that by default though, instead it complains:

    rust-lld: error: no memory region specified for section '.eh_frame'

So let's explicitly discard the .eh_frame section.
---
 riscv-rt/link.x | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 6a666da0..0e2bd985 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -72,6 +72,12 @@ SECTIONS
     KEEP(*(.got .got.*));
     _egot = .;
   } > RAM AT > FLASH /* LLD fails on AT > FLASH */
+
+  /* Discard .eh_frame, we are not doing unwind on panic so it is not needed */
+  /DISCARD/ :
+  {
+    *(.eh_frame);
+  }
 }
 
 /* Do not exceed this mark in the error messages below                | */

From 89506703632b973819f361edb6e91aa210211110 Mon Sep 17 00:00:00 2001
From: Dan Callaghan <djc@djc.id.au>
Date: Wed, 15 Aug 2018 16:57:26 +1000
Subject: [PATCH 028/234] make the linker script compatible with lld

To work around a bug in lld, we need to avoid starting the .bss section
from a fixed address (previously, the _sbss symbol). Otherwise lld
incorrectly tries to extend the FLASH output region up to the start of
the RAM output region, which is too large.

To work around another bug in lld, we need to avoid starting sections
marked with (INFO) from a specific starting address. Its parser does not
accept both a start address and the (INFO) attribute.

Specifying these start addresses is redundant anyway, the linker will
lay them out in sequential order for us.
---
 riscv-rt/link.x | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 0e2bd985..5f249659 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -24,15 +24,15 @@ SECTIONS
     *(.rodata .rodata.*);
   } > FLASH
 
-  PROVIDE(_sbss = ORIGIN(RAM));
-  .bss ALIGN(_sbss,4) :
+  .bss :
   {
+    _sbss = .;
     *(.bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
   } > RAM
 
-  .data _ebss :
+  .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata))
   {
     _sidata = LOADADDR(.data);
     _sdata = .;
@@ -41,37 +41,35 @@ SECTIONS
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;
-  } > RAM AT > FLASH /* LLD fails on AT > FLASH */
+  } > RAM
 
   PROVIDE(_heap_size = 0);
 
   /* fictitious region that represents the memory available for the heap */
-  .heap _edata (INFO) : ALIGN(4)
+  .heap (INFO) :
   {
     _sheap = .;
     . += _heap_size;
     . = ALIGN(4);
     _eheap = .;
-  }
+  } > RAM
 
   /* fictitious region that represents the memory available for the stack */
-  .stack _eheap (INFO) : ALIGN(4)
+  .stack (INFO) :
   {
     _estack = .;
     . = _stack_start;
     _sstack = .;
-  }
+  } > RAM
 
   /* fake output .got section */
   /* Dynamic relocations are unsupported. This section is only used to detect
      relocatable code in the input files and raise an error if relocatable code
      is found */
-  .got :
+  .got (INFO) :
   {
-    _sgot = .;
     KEEP(*(.got .got.*));
-    _egot = .;
-  } > RAM AT > FLASH /* LLD fails on AT > FLASH */
+  }
 
   /* Discard .eh_frame, we are not doing unwind on panic so it is not needed */
   /DISCARD/ :
@@ -81,7 +79,7 @@ SECTIONS
 }
 
 /* Do not exceed this mark in the error messages below                | */
-ASSERT(_sgot == _egot, "
+ASSERT(SIZEOF(.got) == 0, "
 .got section detected in the input files. Dynamic relocations are not
 supported. If you are linking to C code compiled using the `gcc` crate
 then modify your build script to compile the C code _without_ the

From 9c06d6ceda7f0c3f575d3854d1354cb69128d413 Mon Sep 17 00:00:00 2001
From: Jonathan Behrens <fintelia@gmail.com>
Date: Tue, 20 Nov 2018 13:28:19 -0500
Subject: [PATCH 029/234] Update for newer rustc versions

---
 riscv-rt/src/lang_items.rs | 4 ++--
 riscv-rt/src/lib.rs        | 3 ---
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/src/lang_items.rs b/riscv-rt/src/lang_items.rs
index 4fbe64d3..25cb6877 100644
--- a/riscv-rt/src/lang_items.rs
+++ b/riscv-rt/src/lang_items.rs
@@ -3,8 +3,8 @@
 use riscv::asm;
 
 /// Default panic handler
-#[panic_implementation]
-fn panic_fmt(_info: &core::panic::PanicInfo) -> ! {
+#[panic_handler]
+fn panic(_info: &core::panic::PanicInfo) -> ! {
     asm::ebreak();
     loop {}
 }
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 822d9ca0..7faaaa64 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -167,12 +167,9 @@
 #![feature(asm)]
 #![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
-#![feature(extern_prelude)]
 #![feature(global_asm)]
 #![feature(lang_items)]
 #![feature(linkage)]
-#![feature(panic_implementation)]
-#![feature(used)]
 
 extern crate riscv;
 extern crate r0;

From ef135749bd496ab93ad11034ba7655f37f5109a7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 17:11:06 +0300
Subject: [PATCH 030/234] Use riscv::mtvec::write() to set trap handler

---
 riscv-rt/src/lib.rs | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 7faaaa64..f16b27d3 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -176,7 +176,7 @@ extern crate r0;
 
 mod lang_items;
 
-use riscv::register::{mcause, mstatus};
+use riscv::register::{mcause, mstatus, mtvec};
 
 extern "C" {
     // Boundaries of the .bss section
@@ -244,18 +244,10 @@ pub extern "C" fn start_rust() -> ! {
 
     // TODO: Enable FPU when available
 
-    // Set mtvec to _start_trap
-    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
     unsafe {
-        //mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
-        asm!("csrrw zero, 0x305, $0"
-             :
-             : "r"(&_start_trap)
-             :
-             : "volatile");
-    }
+        // Set mtvec to _start_trap
+        mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
 
-    unsafe {
         main();
     }
 }

From 52a8809fa103122baa18913a6b76d6077992d60c Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 17:15:31 +0300
Subject: [PATCH 031/234] Remove lang_items

---
 riscv-rt/src/lang_items.rs | 53 --------------------------------------
 riscv-rt/src/lib.rs        |  3 ---
 2 files changed, 56 deletions(-)
 delete mode 100644 riscv-rt/src/lang_items.rs

diff --git a/riscv-rt/src/lang_items.rs b/riscv-rt/src/lang_items.rs
deleted file mode 100644
index 25cb6877..00000000
--- a/riscv-rt/src/lang_items.rs
+++ /dev/null
@@ -1,53 +0,0 @@
-// NOTE: Adapted from cortex-m/src/lang_items.rs
-
-use riscv::asm;
-
-/// Default panic handler
-#[panic_handler]
-fn panic(_info: &core::panic::PanicInfo) -> ! {
-    asm::ebreak();
-    loop {}
-}
-
-/// Lang item required to make the normal `main` work in applications
-// This is how the `start` lang item works:
-// When `rustc` compiles a binary crate, it creates a `main` function that looks
-// like this:
-//
-// ```
-// #[export_name = "main"]
-// pub extern "C" fn rustc_main(argc: isize, argv: *const *const u8) -> isize {
-//     start(main)
-// }
-// ```
-//
-// Where `start` is this function and `main` is the binary crate's `main`
-// function.
-//
-// The final piece is that the entry point of our program, the reset handler,
-// has to call `rustc_main`. That's covered by the `reset_handler` function in
-// root of this crate.
-#[lang = "start"]
-extern "C" fn lang_start<T>(
-    main: fn(),
-    _argc: isize,
-    _argv: *const *const u8,
-) -> isize
-    where
-    T: Termination,
-{
-    main();
-
-    0
-}
-
-#[lang = "termination"]
-pub trait Termination {
-    fn report(self) -> i32;
-}
-
-impl Termination for () {
-    fn report(self) -> i32 {
-        0
-    }
-}
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index f16b27d3..4e13db37 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -168,14 +168,11 @@
 #![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
 #![feature(global_asm)]
-#![feature(lang_items)]
 #![feature(linkage)]
 
 extern crate riscv;
 extern crate r0;
 
-mod lang_items;
-
 use riscv::register::{mcause, mstatus, mtvec};
 
 extern "C" {

From 5c4dde2845d944c3a9e36737f0c9cabd380a093b Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 17:39:02 +0300
Subject: [PATCH 032/234] Get rid of inline assembly

---
 riscv-rt/asm.S                              |  89 ++++++++++++++++++
 riscv-rt/assemble.sh                        |  14 +++
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 0 -> 1514 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 0 -> 1514 bytes
 riscv-rt/build.rs                           |  21 ++++-
 riscv-rt/check-blobs.sh                     |  21 +++++
 riscv-rt/src/lib.rs                         |  95 --------------------
 7 files changed, 141 insertions(+), 99 deletions(-)
 create mode 100644 riscv-rt/asm.S
 create mode 100755 riscv-rt/assemble.sh
 create mode 100644 riscv-rt/bin/riscv32imac-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32imc-unknown-none-elf.a
 create mode 100755 riscv-rt/check-blobs.sh

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
new file mode 100644
index 00000000..a1fda993
--- /dev/null
+++ b/riscv-rt/asm.S
@@ -0,0 +1,89 @@
+/*
+    Entry point of all programs (_start).
+
+    It initializes DWARF call frame information, the stack pointer, the
+    frame pointer (needed for closures to work in start_rust) and the global
+    pointer. Then it calls _start_rust.
+*/
+
+.section .init, "ax"
+.global _start
+
+_start:
+    .cfi_startproc
+    .cfi_undefined ra
+
+    // .option push
+    // .option norelax
+    lui gp, %hi(__global_pointer$)
+    addi gp, gp, %lo(__global_pointer$)
+    // .option pop
+
+    lui sp, %hi(_stack_start)
+    addi sp, sp, %lo(_stack_start)
+
+    add s0, sp, zero
+
+    jal zero, _start_rust
+
+    .cfi_endproc
+
+
+/*
+    Trap entry point (_start_trap)
+
+    Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
+    restores caller saved registers and then returns.
+*/
+.section .trap, "ax"
+.align 4
+.global _start_trap
+
+_start_trap:
+    addi sp, sp, -16*4
+
+    sw ra, 0*4(sp)
+    sw t0, 1*4(sp)
+    sw t1, 2*4(sp)
+    sw t2, 3*4(sp)
+    sw t3, 4*4(sp)
+    sw t4, 5*4(sp)
+    sw t5, 6*4(sp)
+    sw t6, 7*4(sp)
+    sw a0, 8*4(sp)
+    sw a1, 9*4(sp)
+    sw a2, 10*4(sp)
+    sw a3, 11*4(sp)
+    sw a4, 12*4(sp)
+    sw a5, 13*4(sp)
+    sw a6, 14*4(sp)
+    sw a7, 15*4(sp)
+
+    jal ra, _start_trap_rust
+
+    lw ra, 0*4(sp)
+    lw t0, 1*4(sp)
+    lw t1, 2*4(sp)
+    lw t2, 3*4(sp)
+    lw t3, 4*4(sp)
+    lw t4, 5*4(sp)
+    lw t5, 6*4(sp)
+    lw t6, 7*4(sp)
+    lw a0, 8*4(sp)
+    lw a1, 9*4(sp)
+    lw a2, 10*4(sp)
+    lw a3, 11*4(sp)
+    lw a4, 12*4(sp)
+    lw a5, 13*4(sp)
+    lw a6, 14*4(sp)
+    lw a7, 15*4(sp)
+
+    addi sp, sp, 16*4
+    mret
+
+
+/* Make sure there is an abort when linking */
+.section .init
+.globl abort
+abort:
+    jal zero, _start
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
new file mode 100755
index 00000000..c3e9795d
--- /dev/null
+++ b/riscv-rt/assemble.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+set -euxo pipefail
+
+crate=riscv-rt
+
+# remove existing blobs because otherwise this will append object files to the old blobs
+rm -f bin/*.a
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a
+
+rm bin/$crate.o
diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..d8f2b7d7bde111b9e0715ab4e3003c364effd23f
GIT binary patch
literal 1514
zcma)5U279T6uq0oT4O5-6_G^hrba4$tZ5TkE47pq>q|+k*pIi(CPouXle)W>T13&G
zP=A20K1yGFEg~W!B0)qX=!@@``fTx@otb765PRXyJ#*&HnXfyEamy~2C&Cx?c1!uX
z0{dHC&kU=Ce3*!W>^0@4<65>$BABjit&mlyGedU8DXw0yU8646``0QXnT#htl$Jox
zhaX>^nbtIo7ZIk>Z))|3F7Y1F&v?UUsF!-^6%)^%Xf(>PkLRXC8r8Rd?AEuR?`qV?
znaaoRb!{Dc9edON)_%A8e*MFvk7qv_jp5HDUoL;0_?B%>fB&_8^3T)BjqJeG=2SM<
z$Q5RHW&`sZ^8*W;3)#iSVqs}#DPcLJr^Nn_ia^@>4bmQJTD&)K5c`X;pO9nw3Bk5g
z;;I8}(}LdRx2Pb6I%bIe@x7GL9s&qbS4Y2_`h84<_52ywe@jc8=X6^>(Gd5KNG`&&
zuXK#(xUV#zPsU72C)2!Btrx7Sxl*sx+>)L2N~n0Zy`Jp*PJ3<n>df>8WwG%ZG1R8C
zw2U}?T=Kw*?`9l3ERui~-@`aAd0@rkeWM`QaF*yH4|>fxZgGB;LR4Oa&UowqH*87v
zQ}R-Q2PIF2^I+Mv3LITq#IizeY0V|$mgQPx6dZ>PyHvG|O0B}I2fdFbV5w~0wyot7
z*4nSdIT7`#-dg;l)@)UE37Lm459`c>25gWW_xQg&)Jo^N{{Nx$&T}5#Ymyz7;tj2F
z#8ZNY<2lCJ{d(8ApJ!Kw`h|_M`}JP19^MgpxC5nkjWP7p`Cl@|UX&pZmSy+rZSjO8
xbI`**C_TRx)6_)6BuWe=ggopKSlt~%YI4p^0BO*HMcMs%KY86bZ$vaI?=Kl}n;HNB

literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..d8f2b7d7bde111b9e0715ab4e3003c364effd23f
GIT binary patch
literal 1514
zcma)5U279T6uq0oT4O5-6_G^hrba4$tZ5TkE47pq>q|+k*pIi(CPouXle)W>T13&G
zP=A20K1yGFEg~W!B0)qX=!@@``fTx@otb765PRXyJ#*&HnXfyEamy~2C&Cx?c1!uX
z0{dHC&kU=Ce3*!W>^0@4<65>$BABjit&mlyGedU8DXw0yU8646``0QXnT#htl$Jox
zhaX>^nbtIo7ZIk>Z))|3F7Y1F&v?UUsF!-^6%)^%Xf(>PkLRXC8r8Rd?AEuR?`qV?
znaaoRb!{Dc9edON)_%A8e*MFvk7qv_jp5HDUoL;0_?B%>fB&_8^3T)BjqJeG=2SM<
z$Q5RHW&`sZ^8*W;3)#iSVqs}#DPcLJr^Nn_ia^@>4bmQJTD&)K5c`X;pO9nw3Bk5g
z;;I8}(}LdRx2Pb6I%bIe@x7GL9s&qbS4Y2_`h84<_52ywe@jc8=X6^>(Gd5KNG`&&
zuXK#(xUV#zPsU72C)2!Btrx7Sxl*sx+>)L2N~n0Zy`Jp*PJ3<n>df>8WwG%ZG1R8C
zw2U}?T=Kw*?`9l3ERui~-@`aAd0@rkeWM`QaF*yH4|>fxZgGB;LR4Oa&UowqH*87v
zQ}R-Q2PIF2^I+Mv3LITq#IizeY0V|$mgQPx6dZ>PyHvG|O0B}I2fdFbV5w~0wyot7
z*4nSdIT7`#-dg;l)@)UE37Lm459`c>25gWW_xQg&)Jo^N{{Nx$&T}5#Ymyz7;tj2F
z#8ZNY<2lCJ{d(8ApJ!Kw`h|_M`}JP19^MgpxC5nkjWP7p`Cl@|UX&pZmSy+rZSjO8
xbI`**C_TRx)6_)6BuWe=ggopKSlt~%YI4p^0BO*HMcMs%KY86bZ$vaI?=Kl}n;HNB

literal 0
HcmV?d00001

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 4cd56c63..be724270 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,17 +1,30 @@
 // NOTE: Adapted from cortex-m/build.rs
 use std::env;
-use std::fs::File;
+use std::fs;
 use std::io::Write;
 use std::path::PathBuf;
 
 fn main() {
+    let target = env::var("TARGET").unwrap();
+    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+    let name = env::var("CARGO_PKG_NAME").unwrap();
+
+    if target.starts_with("riscv") {
+        fs::copy(
+            format!("bin/{}.a", target),
+            out_dir.join(format!("lib{}.a", name)),
+        ).unwrap();
+
+        println!("cargo:rustc-link-lib=static={}", name);
+        println!("cargo:rustc-link-search={}", out_dir.display());
+    }
+
     // Put the linker script somewhere the linker can find it
-    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
-    File::create(out.join("link.x"))
+    fs::File::create(out_dir.join("link.x"))
         .unwrap()
         .write_all(include_bytes!("link.x"))
         .unwrap();
-    println!("cargo:rustc-link-search={}", out.display());
+    println!("cargo:rustc-link-search={}", out_dir.display());
 
     println!("cargo:rerun-if-changed=build.rs");
     println!("cargo:rerun-if-changed=link.x");
diff --git a/riscv-rt/check-blobs.sh b/riscv-rt/check-blobs.sh
new file mode 100755
index 00000000..36d885e6
--- /dev/null
+++ b/riscv-rt/check-blobs.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+# Checks that the blobs are up to date with the committed assembly files
+
+set -euxo pipefail
+
+for lib in $(ls bin/*.a); do
+    filename=$(basename $lib)
+    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
+done
+
+./assemble.sh
+
+for lib in $(ls bin/*.a); do
+    filename=$(basename $lib)
+    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
+done
+
+for cksum in $(ls bin/*.after); do
+    diff -u $cksum ${cksum%.after}.before
+done
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 4e13db37..21e7169f 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -164,10 +164,8 @@
 #![no_std]
 #![deny(missing_docs)]
 #![deny(warnings)]
-#![feature(asm)]
 #![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
-#![feature(global_asm)]
 #![feature(linkage)]
 
 extern crate riscv;
@@ -192,36 +190,6 @@ extern "C" {
 }
 
 
-/// Entry point of all programs (_start).
-///
-/// It initializes DWARF call frame information, the stack pointer, the
-/// frame pointer (needed for closures to work in start_rust) and the global
-/// pointer. Then it calls _start_rust.
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-global_asm!(r#"
-.section .init, "ax"
-.globl _start
-_start:
-  .cfi_startproc
-  .cfi_undefined ra
-
-  // .option push
-  // .option norelax
-  lui gp, %hi(__global_pointer$)
-  addi gp, gp, %lo(__global_pointer$)
-  // .option pop
-
-  lui sp, %hi(_stack_start)
-  addi sp, sp, %lo(_stack_start)
-
-  add s0, sp, zero
-
-  jal zero, _start_rust
-
-  .cfi_endproc
-"#);
-
-
 /// Rust entry point (_start_rust)
 ///
 /// Zeros bss section, initializes data section and calls main. This function
@@ -275,60 +243,6 @@ macro_rules! entry {
 }
 
 
-/// Trap entry point (_start_trap)
-///
-/// Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
-/// restores caller saved registers and then returns.
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-global_asm!(r#"
-  .section .trap, "ax"
-  .align 4
-  .global _start_trap
-
-_start_trap:
-  addi sp, sp, -16*4
-
-  sw ra, 0*4(sp)
-  sw t0, 1*4(sp)
-  sw t1, 2*4(sp)
-  sw t2, 3*4(sp)
-  sw t3, 4*4(sp)
-  sw t4, 5*4(sp)
-  sw t5, 6*4(sp)
-  sw t6, 7*4(sp)
-  sw a0, 8*4(sp)
-  sw a1, 9*4(sp)
-  sw a2, 10*4(sp)
-  sw a3, 11*4(sp)
-  sw a4, 12*4(sp)
-  sw a5, 13*4(sp)
-  sw a6, 14*4(sp)
-  sw a7, 15*4(sp)
-
-  jal ra, _start_trap_rust
-
-  lw ra, 0*4(sp)
-  lw t0, 1*4(sp)
-  lw t1, 2*4(sp)
-  lw t2, 3*4(sp)
-  lw t3, 4*4(sp)
-  lw t4, 5*4(sp)
-  lw t5, 6*4(sp)
-  lw t6, 7*4(sp)
-  lw a0, 8*4(sp)
-  lw a1, 9*4(sp)
-  lw a2, 10*4(sp)
-  lw a3, 11*4(sp)
-  lw a4, 12*4(sp)
-  lw a5, 13*4(sp)
-  lw a6, 14*4(sp)
-  lw a7, 15*4(sp)
-
-  addi sp, sp, 16*4
-  mret
-"#);
-
-
 /// Trap entry point rust (_start_trap_rust)
 ///
 /// mcause is read to determine the cause of the trap. XLEN-1 bit indicates
@@ -351,12 +265,3 @@ pub extern "C" fn start_trap_rust() {
 #[no_mangle]
 #[linkage = "weak"]
 pub fn trap_handler(_: mcause::Trap) {}
-
-// Make sure there is an abort when linking
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-global_asm!(r#"
-.section .init
-.globl abort
-abort:
-  jal zero, _start
-"#);

From 7740a5c87d8258efc08e329508686dc861eb41dd Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:10:36 +0300
Subject: [PATCH 033/234] Do not use #[linkage = "weak"]

---
 riscv-rt/link.x     |  2 ++
 riscv-rt/src/lib.rs | 17 ++++++++++-------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 5f249659..48a17005 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -3,6 +3,8 @@ INCLUDE memory.x
 
 PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
 
+PROVIDE(trap_handler = default_trap_handler);
+
 SECTIONS
 {
   PROVIDE(_stext = ORIGIN(FLASH));
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 21e7169f..7860a668 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -166,12 +166,11 @@
 #![deny(warnings)]
 #![feature(compiler_builtins_lib)]
 #![feature(const_fn)]
-#![feature(linkage)]
 
 extern crate riscv;
 extern crate r0;
 
-use riscv::register::{mcause, mstatus, mtvec};
+use riscv::register::{mstatus, mtvec};
 
 extern "C" {
     // Boundaries of the .bss section
@@ -252,10 +251,15 @@ macro_rules! entry {
 #[link_section = ".trap.rust"]
 #[export_name = "_start_trap_rust"]
 pub extern "C" fn start_trap_rust() {
-    // dispatch trap to handler
-    trap_handler(mcause::read().cause());
-    // mstatus, remain in M-mode after mret
+    extern "C" {
+        fn trap_handler();
+    }
+
     unsafe {
+        // dispatch trap to handler
+        trap_handler();
+
+        // mstatus, remain in M-mode after mret
         mstatus::set_mpp(mstatus::MPP::Machine);
     }
 }
@@ -263,5 +267,4 @@ pub extern "C" fn start_trap_rust() {
 
 /// Default Trap Handler
 #[no_mangle]
-#[linkage = "weak"]
-pub fn trap_handler(_: mcause::Trap) {}
+pub fn default_trap_handler() {}

From 0bc07597eea301d367f6392a60e8626353b25ce7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:12:13 +0300
Subject: [PATCH 034/234] Use newer riscv crate

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index bb6a35cd..439b52f2 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.2"
-riscv = "0.3.0"
+riscv = "0.4.0"
 
 [features]
 inline-asm = []
\ No newline at end of file

From 573c41a1b2dfdc1004225f50f73d227d4db50d75 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:19:06 +0300
Subject: [PATCH 035/234] Do not use unstable features

---
 riscv-rt/src/lib.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 7860a668..ffc6842b 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -164,8 +164,6 @@
 #![no_std]
 #![deny(missing_docs)]
 #![deny(warnings)]
-#![feature(compiler_builtins_lib)]
-#![feature(const_fn)]
 
 extern crate riscv;
 extern crate r0;

From 96d46bf3ec47a8da749eb768ed1a65a000758f92 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:30:51 +0300
Subject: [PATCH 036/234] Ignore temporary bin/* files

---
 riscv-rt/.gitignore | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv-rt/.gitignore b/riscv-rt/.gitignore
index 1e7caa9e..e38997ad 100644
--- a/riscv-rt/.gitignore
+++ b/riscv-rt/.gitignore
@@ -1,2 +1,5 @@
 Cargo.lock
 target/
+bin/*.after
+bin/*.before
+bin/*.o

From eae775c3278329df37447744ee53a13df2c4ca8f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:38:19 +0300
Subject: [PATCH 037/234] Use const-fn and inline-asm if available

---
 riscv-rt/Cargo.toml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 439b52f2..3601991f 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -13,4 +13,5 @@ r0 = "0.2.2"
 riscv = "0.4.0"
 
 [features]
-inline-asm = []
\ No newline at end of file
+const-fn = ["riscv/const-fn"]
+inline-asm = ["riscv/inline-asm"]

From d56bb294745db4df1e513dad6ac942f5888e5330 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:38:54 +0300
Subject: [PATCH 038/234] Test with const-fn on nightly

---
 riscv-rt/ci/script.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index eb1a3139..dde62739 100644
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -4,7 +4,7 @@ main() {
     cargo check --target $TARGET
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
-        cargo check --target $TARGET --features inline-asm
+        cargo check --target $TARGET --features 'const-fn inline-asm'
     fi
 }
 

From 483906c2e66aacb8e45aed0ad83865a796cbc540 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:40:07 +0300
Subject: [PATCH 039/234] Check binary blobs during CI

---
 riscv-rt/.travis.yml   | 1 +
 riscv-rt/ci/install.sh | 3 +++
 riscv-rt/ci/script.sh  | 4 ++++
 3 files changed, 8 insertions(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index a3c9cf27..d4791052 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -28,6 +28,7 @@ before_install: set -e
 
 install:
   - bash ci/install.sh
+  - export PATH="$PATH:$PWD/gcc/bin"
 
 script:
   - bash ci/script.sh
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
index 3c419211..fa989702 100644
--- a/riscv-rt/ci/install.sh
+++ b/riscv-rt/ci/install.sh
@@ -4,6 +4,9 @@ main() {
     if [ $TARGET != x86_64-unknown-linux-gnu ]; then
         rustup target add $TARGET
     fi
+
+    mkdir gcc
+    curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
 }
 
 main
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index dde62739..9aa0d7a4 100644
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -6,6 +6,10 @@ main() {
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
         cargo check --target $TARGET --features 'const-fn inline-asm'
     fi
+
+    if [ $TARGET = x86_64-unknown-linux-gnu ]; then
+        ./check-blobs.sh
+    fi
 }
 
 main

From 5737ea356629dea55295d728007c5acbffd74de8 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 18:42:01 +0300
Subject: [PATCH 040/234] Check build on stable

---
 riscv-rt/.travis.yml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index d4791052..01ba0e88 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -24,6 +24,14 @@ matrix:
       rust: nightly
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
+    - env: TARGET=x86_64-unknown-linux-gnu
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    - env: TARGET=riscv32imac-unknown-none-elf
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
 before_install: set -e
 
 install:

From ac66a5a74e1fa37ba7c05d6d132e7cbd709241a7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 26 Jan 2019 20:35:06 +0300
Subject: [PATCH 041/234] Fix RISC-V name

---
 riscv-rt/Cargo.toml | 2 +-
 riscv-rt/src/lib.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 3601991f..a5ebd67e 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -4,7 +4,7 @@ version = "0.3.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]
-description = "Minimal runtime / startup for RISCV CPU's"
+description = "Minimal runtime / startup for RISC-V CPU's"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index ffc6842b..7c7348df 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -1,4 +1,4 @@
-//! Minimal startup / runtime for RISCV CPU's
+//! Minimal startup / runtime for RISC-V CPU's
 //!
 //! # Features
 //!

From 2f90dbee14a5fe0fc141d994623bbc2a68193ee6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 27 Jan 2019 14:06:51 +0300
Subject: [PATCH 042/234] Update heap docs

---
 riscv-rt/src/lib.rs | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 7c7348df..fb4ee8eb 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -133,29 +133,32 @@
 //! _stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
 //! ```
 //!
+//! ### `_heap_size`
+//!
+//! This symbol provides the size of a heap region. The default value is 0. You can set `_heap_size`
+//! to a non-zero value if you are planning to use heap allocations.
+//!
 //! ### `_sheap`
 //!
 //! This symbol is located in RAM right after the `.bss` and `.data` sections.
 //! You can use the address of this symbol as the start address of a heap
-//! region. This symbol is 4 byte aligned so that address will be a multiple of
-//! 4.
+//! region. This symbol is 4 byte aligned so that address will be a multiple of 4.
 //!
 //! #### Example
 //!
 //! ```
 //! extern crate some_allocator;
 //!
-//! // Size of the heap in bytes
-//! const SIZE: usize = 1024;
-//!
 //! extern "C" {
-//!     static mut _sheap: u8;
+//!     static _sheap: u8;
+//!     static _heap_size: u8;
 //! }
 //!
 //! fn main() {
 //!     unsafe {
-//!         let start_address = &mut _sheap as *mut u8;
-//!         some_allocator::initialize(start_address, SIZE);
+//!         let heap_bottom = &_sheap as *const u8 as usize;
+//!         let heap_size = &_heap_size as *const u8 as usize;
+//!         some_allocator::initialize(heap_bottom, heap_size);
 //!     }
 //! }
 //! ```

From 0e141d8476f585b8c9e8d35ff1e427a3280bf75f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 27 Jan 2019 14:08:27 +0300
Subject: [PATCH 043/234] Update example in docs

---
 riscv-rt/src/lib.rs | 70 +++++++++++++++++++++++++++++++--------------
 1 file changed, 48 insertions(+), 22 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index fb4ee8eb..32e89496 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -29,25 +29,17 @@
 //!
 //! $ # add this crate as a dependency
 //! $ edit Cargo.toml && cat $_
-//! [dependencies.riscv-rt]
-//! version = "0.1.0"
-//!
-//! $ # tell Xargo which standard crates to build
-//! $ edit Xargo.toml && cat $_
-//! [dependencies.core]
-//! stage = 0
-//!
-//! [dependencies.compiler_builtins]
-//! features = ["mem"]
-//! stage = 1
+//! [dependencies]
+//! riscv-rt = "0.3.0"
+//! panic-halt = "0.2.0"
 //!
 //! $ # memory layout of the device
 //! $ edit memory.x && cat $_
 //! MEMORY
 //! {
 //!   /* NOTE K = KiBi = 1024 bytes */
-//!   FLASH : ORIGIN = 0x08000000, LENGTH = 128K
-//!   RAM : ORIGIN = 0x20000000, LENGTH = 8K
+//!   FLASH : ORIGIN = 0x20000000, LENGTH = 16M
+//!   RAM : ORIGIN = 0x80000000, LENGTH = 16K
 //! }
 //!
 //! $ edit src/main.rs && cat $_
@@ -57,31 +49,65 @@
 //! #![no_std]
 //! #![no_main]
 //!
-//! #[macro_use(entry)]
-//! extern crate riscv_rt;
+//! extern crate panic_halt;
+//!
+//! use riscv_rt::entry;
 //!
 //! // use `main` as the entry point of this application
 //! entry!(main);
 //!
 //! fn main() -> ! {
 //!     // do something here
+//!     loop { }
 //! }
 //! ```
 //!
 //! ``` text
-//! $ cargo install xargo
+//! $ mkdir .cargo && edit .cargo/config && cat $_
+//! [target.riscv32imac-unknown-none-elf]
+//! rustflags = [
+//!   "-C", "link-arg=-Tlink.x"
+//! ]
+//!
+//! [build]
+//! target = "riscv32imac-unknown-none-elf"
+//! $ edit build.rs && cat $_
+//! ```
+//!
+//! ``` ignore,no_run
+//! use std::env;
+//! use std::fs::File;
+//! use std::io::Write;
+//! use std::path::Path;
+//!
+//! /// Put the linker script somewhere the linker can find it.
+//! fn main() {
+//!     let out_dir = env::var("OUT_DIR").expect("No out dir");
+//!     let dest_path = Path::new(&out_dir);
+//!     let mut f = File::create(&dest_path.join("memory.x"))
+//!         .expect("Could not create file");
+//!
+//!     f.write_all(include_bytes!("memory.x"))
+//!         .expect("Could not write file");
 //!
-//! $ xargo rustc --target riscv32-unknown-none -- \
-//!    -C link-arg=-Tlink.x -C linker=riscv32-unknown-elf-ld -Z linker-flavor=ld
+//!     println!("cargo:rustc-link-search={}", dest_path.display());
+//!
+//!     println!("cargo:rerun-if-changed=memory.x");
+//!     println!("cargo:rerun-if-changed=build.rs");
+//! }
+//! ```
+//!
+//! ``` text
+//! $ cargo build
 //!
 //! $ riscv32-unknown-elf-objdump -Cd $(find target -name app) | head
 //!
 //! Disassembly of section .text:
 //!
-//! 20400000 <_start>:
-//! 20400000:	800011b7    lui	gp,0x80001
-//! 20400004:	80018193    addi	gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
-//! 20400008:	80004137    lui	sp,0x80004
+//! 20000000 <_start>:
+//! 20000000:	800011b7          	lui	gp,0x80001
+//! 20000004:	80018193          	addi	gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
+//! 20000008:	80004137          	lui	sp,0x80004
 //! ```
 //!
 //! # Symbol interfaces

From 11d3c8cb94e5da69fba89b15ca76a4b7b607629e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 27 Jan 2019 18:41:06 +0300
Subject: [PATCH 044/234] Remove obsolete things from documentation

---
 riscv-rt/src/lib.rs | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 32e89496..33f99fa3 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -8,16 +8,6 @@
 //!
 //! - Before main initialization of the FPU (for targets that have a FPU).
 //!
-//! - A `panic_fmt` implementation that just calls abort that you can opt into
-//!   through the "abort-on-panic" Cargo feature. If you don't use this feature
-//!   you'll have to provide the `panic_fmt` lang item yourself. Documentation
-//!   [here][1]
-//!
-//! [1]: https://doc.rust-lang.org/unstable-book/language-features/lang-items.html
-//!
-//! - A minimal `start` lang item to support the standard `fn main()`
-//!   interface. (The processor goes to sleep after returning from `main`)
-//!
 //! - A linker script that encodes the memory layout of a generic RISC-V
 //!   microcontroller. This linker script is missing some information that must
 //!   be supplied through a `memory.x` file (see example below).

From d0b35943da92c907cfc2dbc4e60ceaa9fa83d60f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 27 Jan 2019 18:48:42 +0300
Subject: [PATCH 045/234] Mention entry! macro

---
 riscv-rt/src/lib.rs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 33f99fa3..2f3eaaec 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -8,6 +8,8 @@
 //!
 //! - Before main initialization of the FPU (for targets that have a FPU).
 //!
+//! - An `entry!` macro to declare the entry point of the program.
+//!
 //! - A linker script that encodes the memory layout of a generic RISC-V
 //!   microcontroller. This linker script is missing some information that must
 //!   be supplied through a `memory.x` file (see example below).

From c5e0ec1857e03f31b04ca626187fda0303f442bd Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 27 Jan 2019 18:53:08 +0300
Subject: [PATCH 046/234] Bump version

---
 riscv-rt/Cargo.toml | 2 +-
 riscv-rt/src/lib.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index a5ebd67e..7d3265e4 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.3.0"
+version = "0.4.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "no-std"]
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 2f3eaaec..6a2df0b1 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -22,7 +22,7 @@
 //! $ # add this crate as a dependency
 //! $ edit Cargo.toml && cat $_
 //! [dependencies]
-//! riscv-rt = "0.3.0"
+//! riscv-rt = "0.4.0"
 //! panic-halt = "0.2.0"
 //!
 //! $ # memory layout of the device

From f9147fd94b41eb35a1bdb0784af1e29feaf46d0a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 6 Feb 2019 19:09:29 +0300
Subject: [PATCH 047/234] Remove the unused 'const-fn' feature

---
 riscv-rt/Cargo.toml   | 1 -
 riscv-rt/ci/script.sh | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 7d3265e4..629aaa89 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -13,5 +13,4 @@ r0 = "0.2.2"
 riscv = "0.4.0"
 
 [features]
-const-fn = ["riscv/const-fn"]
 inline-asm = ["riscv/inline-asm"]
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index 9aa0d7a4..e2497ee9 100644
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -4,7 +4,7 @@ main() {
     cargo check --target $TARGET
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
-        cargo check --target $TARGET --features 'const-fn inline-asm'
+        cargo check --target $TARGET --features 'inline-asm'
     fi
 
     if [ $TARGET = x86_64-unknown-linux-gnu ]; then

From 93c9d0ad31972d399bb39429af5a0b6a5c866550 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 6 Feb 2019 22:26:39 +0300
Subject: [PATCH 048/234] Add team e-mail to authors

---
 riscv-rt/Cargo.toml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 629aaa89..c9a895f8 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -2,7 +2,10 @@
 name = "riscv-rt"
 version = "0.4.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
-authors = ["David Craven <david@craven.ch>"]
+authors = [
+    "The RISC-V Team <risc-v@teams.rust-embedded.org>",
+    "David Craven <david@craven.ch>",
+]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
 keywords = ["riscv", "runtime", "startup"]

From e4217a736c6fb7c6d2b49f771477a4b199a66351 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 7 Feb 2019 19:54:18 +0300
Subject: [PATCH 049/234] Leave just team e-mail in authors

---
 riscv-rt/Cargo.toml | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index c9a895f8..23422854 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -2,10 +2,7 @@
 name = "riscv-rt"
 version = "0.4.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
-authors = [
-    "The RISC-V Team <risc-v@teams.rust-embedded.org>",
-    "David Craven <david@craven.ch>",
-]
+authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
 keywords = ["riscv", "runtime", "startup"]

From 0d671a419b24413e1aafa09fae17167c1c72a561 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 14 Feb 2019 17:43:59 +0300
Subject: [PATCH 050/234] Fix _start_trap address calculation

---
 riscv-rt/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 6a2df0b1..c430f412 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -229,7 +229,7 @@ pub extern "C" fn start_rust() -> ! {
 
     unsafe {
         // Set mtvec to _start_trap
-        mtvec::write(_start_trap as usize, mtvec::TrapMode::Direct);
+        mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);
 
         main();
     }

From b4486cbb8cd881ed6536116551f0d59a4e44aa5c Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 22 Feb 2019 11:59:39 +0300
Subject: [PATCH 051/234] Fix _start_trap alignment

---
 riscv-rt/asm.S                              |   1 -
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1514 -> 1482 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1514 -> 1482 bytes
 riscv-rt/link.x                             |   1 +
 4 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index a1fda993..2de48d09 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -36,7 +36,6 @@ _start:
     restores caller saved registers and then returns.
 */
 .section .trap, "ax"
-.align 4
 .global _start_trap
 
 _start_trap:
diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index d8f2b7d7bde111b9e0715ab4e3003c364effd23f..24971b2de844ebda8af79bd142e8e8914fbf5ec3 100644
GIT binary patch
delta 145
zcmaFGeTsX+0wzPFiHkHCB_^KMpUlCi!uWr(E~EP5C`Lv`hRM-P-x-xQ$1_JWGRjQe
z&7!U8!+-#cP^LMMW&vUcD1QnQ0|U=wepY41Ig^c9)fpE|js}t^CO3o0)vW3gM}R5<
Kp{hX?%p?E|>>4ou

delta 178
zcmX@b{fc|S0wxoaiHkHCEhe7U=VN3LW?+EhiN91B<tNKCs<QzFfnc#4BO@c<WOt_T
zydbVN5c2`C!Df5rXhueZ$+KCsH4}gWFdzVBm;-4RAa;QAS1>U!NKAguqRhBqvM{SU
d<AKT6K=RJyWH8yysxI*as3H)m8bmQd*#N_>8_)m%

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index d8f2b7d7bde111b9e0715ab4e3003c364effd23f..24971b2de844ebda8af79bd142e8e8914fbf5ec3 100644
GIT binary patch
delta 145
zcmaFGeTsX+0wzPFiHkHCB_^KMpUlCi!uWr(E~EP5C`Lv`hRM-P-x-xQ$1_JWGRjQe
z&7!U8!+-#cP^LMMW&vUcD1QnQ0|U=wepY41Ig^c9)fpE|js}t^CO3o0)vW3gM}R5<
Kp{hX?%p?E|>>4ou

delta 178
zcmX@b{fc|S0wxoaiHkHCEhe7U=VN3LW?+EhiN91B<tNKCs<QzFfnc#4BO@c<WOt_T
zydbVN5c2`C!Df5rXhueZ$+KCsH4}gWFdzVBm;-4RAa;QAS1>U!NKAguqRhBqvM{SU
d<AKT6K=RJyWH8yysxI*as3H)m8bmQd*#N_>8_)m%

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 48a17005..c172f746 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -15,6 +15,7 @@ SECTIONS
     /* point of the program. */
     KEEP(*(.init));
     KEEP(*(.init.rust));
+    . = ALIGN(4);
     KEEP(*(.trap));
     KEEP(*(.trap.rust));
 

From f88d31d88ff9ed2be49755f08fefa8fbd5a6d707 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 4 Mar 2019 19:03:46 +0300
Subject: [PATCH 052/234] Use position-independent loads in asm.S

---
 riscv-rt/asm.S | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 2de48d09..876bb499 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -15,12 +15,10 @@ _start:
 
     // .option push
     // .option norelax
-    lui gp, %hi(__global_pointer$)
-    addi gp, gp, %lo(__global_pointer$)
+    la gp, __global_pointer$
     // .option pop
 
-    lui sp, %hi(_stack_start)
-    addi sp, sp, %lo(_stack_start)
+    la sp, _stack_start
 
     add s0, sp, zero
 

From 28e5e7beb5f5b6b124b2baa0143d6a83452d7ecb Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 4 Mar 2019 19:14:36 +0300
Subject: [PATCH 053/234] Disable relaxation for gp load

---
 riscv-rt/asm.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 876bb499..4402d777 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -13,10 +13,10 @@ _start:
     .cfi_startproc
     .cfi_undefined ra
 
-    // .option push
-    // .option norelax
+    .option push
+    .option norelax
     la gp, __global_pointer$
-    // .option pop
+    .option pop
 
     la sp, _stack_start
 

From 6ef721887322a2dabfeffc47d66506eec2455cc1 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 4 Mar 2019 19:16:14 +0300
Subject: [PATCH 054/234] Generate binaries for riscv64 targets

---
 riscv-rt/assemble.sh | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index c3e9795d..f3e9c1e2 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -9,6 +9,10 @@ rm -f bin/*.a
 
 riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a
+ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
 
 rm bin/$crate.o

From 656af9deaf4e1940cce54b32b272d2314ec566e4 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 17:51:11 +0300
Subject: [PATCH 055/234] Regenerate binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1482 -> 1502 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1482 -> 1502 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 0 -> 2130 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 0 -> 2130 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 riscv-rt/bin/riscv64gc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64imac-unknown-none-elf.a

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 24971b2de844ebda8af79bd142e8e8914fbf5ec3..22f6970b9df794a680f13467f276e4843ea511af 100644
GIT binary patch
delta 327
zcmX@beUE#>0!HJB3pK5Dm>C!t85kH$fS7?ngMpWUhhaKUU~(fPgE){DW@KdetmN=<
z6O%Dxpo1|BBSZcN`+xZ#{{Nl$%ZCZ5&W&+`v=Ue|h+u)UKn!LEw#f$>MY%cPqAZg?
zGL|wbO-^S@P7>#V2!r%UK$U<fabAcxh;0mE0v!cZ!wKPl*f4Q9AX|_RA`WteAU6_Q
zV6zLe5hJ78<Z>2eRu7<K6DH4RQD%&qe3(U@amD1<U{aV>opH-#YgTpMD?qIZKre%g
d;GUe%D$V$1ayP5G#0{X%K!~wm5)@n@008w_EsFpE

delta 328
zcmcb|eTsX+0!G7$3pEWSm>C!t85kH$fS7?ngMpWUhhaNVU~(fPgE^2EW@KbAW?^K=
z|8W0b{)hShCbKa5Ob%k4AT0sb03ul6ED(d4fo-xZQz@gw<jG9QMp9e|Nn<Dzq+S{-
z4r0T^Ie=^_?#TkoVn)*35Vbr=(jq{%AV>fRK$Z(~f|(3TAU5CT2xcQjMw!XoEXu4h
zObiSalQ**{GX_k)&Z5pZW%7R@IcKsut2*O?$^NYBnkPV7fxZJ-12P8W3;`$`7$9(P
UV)A@eb%`TD^8(>wknjR=0S}cX$^ZZW

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 24971b2de844ebda8af79bd142e8e8914fbf5ec3..22f6970b9df794a680f13467f276e4843ea511af 100644
GIT binary patch
delta 327
zcmX@beUE#>0!HJB3pK5Dm>C!t85kH$fS7?ngMpWUhhaKUU~(fPgE){DW@KdetmN=<
z6O%Dxpo1|BBSZcN`+xZ#{{Nl$%ZCZ5&W&+`v=Ue|h+u)UKn!LEw#f$>MY%cPqAZg?
zGL|wbO-^S@P7>#V2!r%UK$U<fabAcxh;0mE0v!cZ!wKPl*f4Q9AX|_RA`WteAU6_Q
zV6zLe5hJ78<Z>2eRu7<K6DH4RQD%&qe3(U@amD1<U{aV>opH-#YgTpMD?qIZKre%g
d;GUe%D$V$1ayP5G#0{X%K!~wm5)@n@008w_EsFpE

delta 328
zcmcb|eTsX+0!G7$3pEWSm>C!t85kH$fS7?ngMpWUhhaNVU~(fPgE^2EW@KbAW?^K=
z|8W0b{)hShCbKa5Ob%k4AT0sb03ul6ED(d4fo-xZQz@gw<jG9QMp9e|Nn<Dzq+S{-
z4r0T^Ie=^_?#TkoVn)*35Vbr=(jq{%AV>fRK$Z(~f|(3TAU5CT2xcQjMw!XoEXu4h
zObiSalQ**{GX_k)&Z5pZW%7R@IcKsut2*O?$^NYBnkPV7fxZJ-12P8W3;`$`7$9(P
UV)A@eb%`TD^8(>wknjR=0S}cX$^ZZW

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..1bc727c5404548e652ccfca5562fa324fcb590e8
GIT binary patch
literal 2130
zcmbtV-D?v;5T8q8)!0Zyv0|kpu_}n3Z4)YyT8|W~4<V(+e!N{TF*U(7sds15B8vVA
z^+ErPk|!UFh!hc#AR;0@`(|vP{g~O0WP7=&=)ms$_BS&-yE`{YY}B&z#j)_Y=uR0_
zmK>{dG@2Zi4hvxb2;!*7VLGm5yTFy{+SW2yxhgVXmz?~{S=-gCJYT0QBgrJ&eke5}
zTo%F)E@vhJnubZZXs`{fm1F^mA!!FN7&IUP-S7mRA3xNf7xh8hXFG0us|6C;l#vK&
zP;FfLQEmMEp1RewarpVs7yU2o&6QWHukXJ({Z_9JzZ-df;ltR+^rwl>U(xH4v6haH
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z7fO$q%qSWKb4lq%&@C6JWrgUz>Z?gi{t?Ar@(G0_DEFj&_9`~Xd;O^%BnNQpXNXVo
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zDsTStXz<IwE*?bYq5M=MZ~iOD(VpJAJVTB|{H*f@&N5ySX#{@xH%0!d!jbY*tc;iE
x^2<#jUuZ&E7Z;{pqv4IGUiQ`=DR?R_bd45@c;Aou*e||^E`>71Rde>n{{p_2pfLad

literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..1bc727c5404548e652ccfca5562fa324fcb590e8
GIT binary patch
literal 2130
zcmbtV-D?v;5T8q8)!0Zyv0|kpu_}n3Z4)YyT8|W~4<V(+e!N{TF*U(7sds15B8vVA
z^+ErPk|!UFh!hc#AR;0@`(|vP{g~O0WP7=&=)ms$_BS&-yE`{YY}B&z#j)_Y=uR0_
zmK>{dG@2Zi4hvxb2;!*7VLGm5yTFy{+SW2yxhgVXmz?~{S=-gCJYT0QBgrJ&eke5}
zTo%F)E@vhJnubZZXs`{fm1F^mA!!FN7&IUP-S7mRA3xNf7xh8hXFG0us|6C;l#vK&
zP;FfLQEmMEp1RewarpVs7yU2o&6QWHukXJ({Z_9JzZ-df;ltR+^rwl>U(xH4v6haH
z*T&P?dNwz?H5r&$n~BfXX47-^x!nBLe9UqnI>^s)h%3-mr$M`?X?>BvZaO#d$As-~
zRnYgw^!x$eErP5t?WQ1zM^a4uEj#mZ#aF^0bV=CMf7)kH)3XJF(9ZUwxyR?6l(DB3
z+C)b>@FzO(LyT`f|HTgeS;mK;?H%;YU=&RAM!A}^%I0#lRB;RT0Q>y&H+S}eecRdD
z7fO$q%qSWKb4lq%&@C6JWrgUz>Z?gi{t?Ar@(G0_DEFj&_9`~Xd;O^%BnNQpXNXVo
zJ&51efmiDl6+S7{yA=NcfsdnBt0MVR9)HlCyGyQ>L+#pJ7bS8FcU;h~TdoCq&T&Au
z3uQ|$RZ7S*$bOVKEELT}+gd6pNBJ+<htbpn>K$l9gC-vdc(@p@DV}~(RWa0sf_cBS
z2zn=~`M<_fU;OU;CtIl)^5#E-EPbN}v$m#&xafwU=x>Ak<o8M6A;~BXzx<2L3Xl<6
zDsTStXz<IwE*?bYq5M=MZ~iOD(VpJAJVTB|{H*f@&N5ySX#{@xH%0!d!jbY*tc;iE
x^2<#jUuZ&E7Z;{pqv4IGUiQ`=DR?R_bd45@c;Aou*e||^E`>71Rde>n{{p_2pfLad

literal 0
HcmV?d00001


From d5e487fcf7a9176d048f016ad887f8d78c8c3a4d Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 18:04:40 +0300
Subject: [PATCH 056/234] Update CI build matrix

---
 riscv-rt/.travis.yml | 39 ++++++++++++---------------------------
 1 file changed, 12 insertions(+), 27 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 01ba0e88..e61c80a5 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -1,36 +1,21 @@
 language: rust
 
-matrix:
-  include:
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    #- env: TARGET=x86_64-unknown-linux-gnu
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+rust:
+- nightly
+- stable
 
-    #- env: TARGET=riscv32imac-unknown-none-elf
-    #  rust: beta
-    #  if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+env:
+- TARGET=x86_64-unknown-linux-gnu
+- TARGET=riscv32imac-unknown-none-elf
+- TARGET=riscv64imac-unknown-none-elf
 
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: nightly
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-    - env: TARGET=x86_64-unknown-linux-gnu
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+matrix:
+  exclude:
+    - rust: stable
+      env: TARGET=riscv64imac-unknown-none-elf
 
-    - env: TARGET=riscv32imac-unknown-none-elf
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
 before_install: set -e
 

From 465690eaa5a972482088c9f93a89f93fe3c18c0a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 18:06:53 +0300
Subject: [PATCH 057/234] Regenerate binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1502 -> 1490 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1502 -> 1490 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2130 -> 2114 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2130 -> 2114 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 22f6970b9df794a680f13467f276e4843ea511af..e301d87339624d8fd01ee4ddee127467fd276a01 100644
GIT binary patch
delta 142
zcmcb|eTjR*0wyDaiHkHC6(*im<}qerWXS(;|6l%x`Tr)fF#1dmVw}JzG5Im$dLTKO
zX*sV50|SE~ACLe7iOufJ&WwyQle<}z8Eq!7XHjPin0y^b&YAolOscc0Gp?BI4<t`a
ZE(ek?CeLS8mpH@3zz_&A0ZcMN*#JeuB=7(L

delta 154
zcmcb_eUE#>0w!aliHkHCbtaxx7W=H^@NpB9F=L>EF$*I@{s;Si`5*rOo%qX#iGg9V
z8{-5<rODSB*8|CRrsceH3=9l{d_V#Slr~#4J2Nt>O|EBAX7rf6m_?m2YVv6yxnlBX
lFe%Nd&bVc=GmyM8IU7iRnLL?QUE&7N+(3v4V3HBa1_0^XDSQ9`

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 22f6970b9df794a680f13467f276e4843ea511af..e301d87339624d8fd01ee4ddee127467fd276a01 100644
GIT binary patch
delta 142
zcmcb|eTjR*0wyDaiHkHC6(*im<}qerWXS(;|6l%x`Tr)fF#1dmVw}JzG5Im$dLTKO
zX*sV50|SE~ACLe7iOufJ&WwyQle<}z8Eq!7XHjPin0y^b&YAolOscc0Gp?BI4<t`a
ZE(ek?CeLS8mpH@3zz_&A0ZcMN*#JeuB=7(L

delta 154
zcmcb_eUE#>0w!aliHkHCbtaxx7W=H^@NpB9F=L>EF$*I@{s;Si`5*rOo%qX#iGg9V
z8{-5<rODSB*8|CRrsceH3=9l{d_V#Slr~#4J2Nt>O|EBAX7rf6m_?m2YVv6yxnlBX
lFe%Nd&bVc=GmyM8IU7iRnLL?QUE&7N+(3v4V3HBa1_0^XDSQ9`

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index 1bc727c5404548e652ccfca5562fa324fcb590e8..b35b6b2d7719562a0df42e884858d475be8d867b 100644
GIT binary patch
delta 139
zcmca4a7bXn0wxoaiHi&vBPL!}=P_nsWXS(;|6l%x`Tr&hF#1eRVm!epF}aaZc(NVS
z7a+@+`MabD0|W>HDLyD0L`iIRW_i!ZC^OlZ&7ASU<ZL#3#+b>gf#ib8uYu%>$=dAp
Zj5{W01IZhcR|Cn8$*+MV!(?p^bpUsFC%FIs

delta 148
zcmX>ka7kdo0wyzqiHi&vGbUbE7yGQ_@NpB9F=L>EF$*I@{s;Si`5*rOoy^AQ!^Qvx
zlY<yfFe*(hWE7sP$MglrQfB_nD+iHd5CqbElkHi=H`}p1VPsUBtjuQ4_+fH1n>}ON
n<k>)S!{pmQa>rz8c6-JXlcRy;i^;Qr<c!I;fuz7>X%2M&TO%vh

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index 1bc727c5404548e652ccfca5562fa324fcb590e8..b35b6b2d7719562a0df42e884858d475be8d867b 100644
GIT binary patch
delta 139
zcmca4a7bXn0wxoaiHi&vBPL!}=P_nsWXS(;|6l%x`Tr&hF#1eRVm!epF}aaZc(NVS
z7a+@+`MabD0|W>HDLyD0L`iIRW_i!ZC^OlZ&7ASU<ZL#3#+b>gf#ib8uYu%>$=dAp
Zj5{W01IZhcR|Cn8$*+MV!(?p^bpUsFC%FIs

delta 148
zcmX>ka7kdo0wyzqiHi&vGbUbE7yGQ_@NpB9F=L>EF$*I@{s;Si`5*rOoy^AQ!^Qvx
zlY<yfFe*(hWE7sP$MglrQfB_nD+iHd5CqbElkHi=H`}p1VPsUBtjuQ4_+fH1n>}ON
n<k>)S!{pmQa>rz8c6-JXlcRy;i^;Qr<c!I;fuz7>X%2M&TO%vh


From b7dac856be7bd8375917ec3deb0d8a364f0837e7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 18:12:42 +0300
Subject: [PATCH 058/234] Update 'riscv' dependency

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 23422854..28536baa 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.2"
-riscv = "0.4.0"
+riscv = "0.5.0"
 
 [features]
 inline-asm = ["riscv/inline-asm"]

From 06e15287c2e5426b1f81cca5c8f920e0cc14ff86 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 15:54:42 +0300
Subject: [PATCH 059/234] Copy cortex-m-rt-macros

---
 riscv-rt/macros/Cargo.toml |  28 ++
 riscv-rt/macros/src/lib.rs | 807 +++++++++++++++++++++++++++++++++++++
 2 files changed, 835 insertions(+)
 create mode 100644 riscv-rt/macros/Cargo.toml
 create mode 100644 riscv-rt/macros/src/lib.rs

diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
new file mode 100644
index 00000000..ba6db64f
--- /dev/null
+++ b/riscv-rt/macros/Cargo.toml
@@ -0,0 +1,28 @@
+[package]
+authors = ["Jorge Aparicio <jorge@japaric.io>"]
+categories = ["embedded", "no-std"]
+description = "Attributes re-exported in `cortex-m-rt`"
+documentation = "https://docs.rs/cortex-m-rt"
+keywords = ["arm", "cortex-m", "runtime", "startup"]
+license = "MIT OR Apache-2.0"
+name = "cortex-m-rt-macros"
+repository = "https://github.com/japaric/cortex-m-rt"
+version = "0.1.5"
+
+[lib]
+proc-macro = true
+
+[dependencies]
+quote = "0.6.8"
+proc-macro2 = "0.4.20"
+
+[dependencies.syn]
+features = ["extra-traits", "full"]
+version = "0.15.13"
+
+[dependencies.rand]
+version = "0.5.5"
+default-features = false
+
+[dev-dependencies]
+cortex-m-rt = { path = "..", version = "0.6.0" }
diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
new file mode 100644
index 00000000..7528586e
--- /dev/null
+++ b/riscv-rt/macros/src/lib.rs
@@ -0,0 +1,807 @@
+#![deny(warnings)]
+
+extern crate proc_macro;
+extern crate rand;
+#[macro_use]
+extern crate quote;
+extern crate core;
+extern crate proc_macro2;
+#[macro_use]
+extern crate syn;
+
+use proc_macro2::Span;
+use rand::Rng;
+use rand::SeedableRng;
+use std::collections::HashSet;
+use std::sync::atomic::{AtomicUsize, Ordering};
+use std::time::{SystemTime, UNIX_EPOCH};
+use syn::{
+    parse, spanned::Spanned, AttrStyle, Attribute, FnArg, Ident, Item, ItemFn, ItemStatic,
+    PathArguments, ReturnType, Stmt, Type, Visibility,
+};
+
+static CALL_COUNT: AtomicUsize = AtomicUsize::new(0);
+
+use proc_macro::TokenStream;
+
+/// Attribute to declare the entry point of the program
+///
+/// **IMPORTANT**: This attribute must appear exactly *once* in the dependency graph. Also, if you
+/// are using Rust 1.30 the attribute must be used on a reachable item (i.e. there must be no
+/// private modules between the item and the root of the crate); if the item is in the root of the
+/// crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31 and newer releases.
+///
+/// The specified function will be called by the reset handler *after* RAM has been initialized. In
+/// the case of the `thumbv7em-none-eabihf` target the FPU will also be enabled before the function
+/// is called.
+///
+/// The type of the specified function must be `[unsafe] fn() -> !` (never ending function)
+///
+/// # Properties
+///
+/// The entry point will be called by the reset handler. The program can't reference to the entry
+/// point, much less invoke it.
+///
+/// `static mut` variables declared within the entry point are safe to access. The compiler can't
+/// prove this is safe so the attribute will help by making a transformation to the source code: for
+/// this reason a variable like `static mut FOO: u32` will become `let FOO: &'static mut u32;`. Note
+/// that `&'static mut` references have move semantics.
+///
+/// # Examples
+///
+/// - Simple entry point
+///
+/// ``` no_run
+/// # #![no_main]
+/// # use cortex_m_rt_macros::entry;
+/// #[entry]
+/// fn main() -> ! {
+///     loop {
+///         /* .. */
+///     }
+/// }
+/// ```
+///
+/// - `static mut` variables local to the entry point are safe to modify.
+///
+/// ``` no_run
+/// # #![no_main]
+/// # use cortex_m_rt_macros::entry;
+/// #[entry]
+/// fn main() -> ! {
+///     static mut FOO: u32 = 0;
+///
+///     let foo: &'static mut u32 = FOO;
+///     assert_eq!(*foo, 0);
+///     *foo = 1;
+///     assert_eq!(*foo, 1);
+///
+///     loop {
+///         /* .. */
+///     }
+/// }
+/// ```
+#[proc_macro_attribute]
+pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
+    let f = parse_macro_input!(input as ItemFn);
+
+    // check the function signature
+    let valid_signature = f.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.abi.is_none()
+        && f.decl.inputs.is_empty()
+        && f.decl.generics.params.is_empty()
+        && f.decl.generics.where_clause.is_none()
+        && f.decl.variadic.is_none()
+        && match f.decl.output {
+            ReturnType::Default => false,
+            ReturnType::Type(_, ref ty) => match **ty {
+                Type::Never(_) => true,
+                _ => false,
+            },
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            f.span(),
+            "`#[entry]` function must have signature `[unsafe] fn() -> !`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let unsafety = f.unsafety;
+    let hash = random_ident();
+    let (statics, stmts) = match extract_static_muts(f.block.stmts) {
+        Err(e) => return e.to_compile_error().into(),
+        Ok(x) => x,
+    };
+
+    let vars = statics
+        .into_iter()
+        .map(|var| {
+            let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
+            let ident = var.ident;
+            let ty = var.ty;
+            let expr = var.expr;
+
+            quote!(
+                #[allow(non_snake_case)]
+                #(#cfgs)*
+                let #ident: &'static mut #ty = unsafe {
+                    #(#attrs)*
+                    #(#cfgs)*
+                    static mut #ident: #ty = #expr;
+
+                    &mut #ident
+                };
+            )
+        })
+        .collect::<Vec<_>>();
+
+    quote!(
+        #[export_name = "main"]
+        #(#attrs)*
+        pub #unsafety fn #hash() -> ! {
+            #(#vars)*
+
+            #(#stmts)*
+        }
+    )
+    .into()
+}
+
+/// Attribute to declare an exception handler
+///
+/// **IMPORTANT**: If you are using Rust 1.30 this attribute must be used on reachable items (i.e.
+/// there must be no private modules between the item and the root of the crate); if the item is in
+/// the root of the crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31
+/// and newer releases.
+///
+/// # Syntax
+///
+/// ```
+/// # use cortex_m_rt_macros::exception;
+/// #[exception]
+/// fn SysTick() {
+///     // ..
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// where the name of the function must be one of:
+///
+/// - `DefaultHandler`
+/// - `NonMaskableInt`
+/// - `HardFault`
+/// - `MemoryManagement` (a)
+/// - `BusFault` (a)
+/// - `UsageFault` (a)
+/// - `SecureFault` (b)
+/// - `SVCall`
+/// - `DebugMonitor` (a)
+/// - `PendSV`
+/// - `SysTick`
+///
+/// (a) Not available on Cortex-M0 variants (`thumbv6m-none-eabi`)
+///
+/// (b) Only available on ARMv8-M
+///
+/// # Usage
+///
+/// `#[exception] fn HardFault(..` sets the hard fault handler. The handler must have signature
+/// `[unsafe] fn(&ExceptionFrame) -> !`. This handler is not allowed to return as that can cause
+/// undefined behavior.
+///
+/// `#[exception] fn DefaultHandler(..` sets the *default* handler. All exceptions which have not
+/// been assigned a handler will be serviced by this handler. This handler must have signature
+/// `[unsafe] fn(irqn: i16) [-> !]`. `irqn` is the IRQ number (See CMSIS); `irqn` will be a negative
+/// number when the handler is servicing a core exception; `irqn` will be a positive number when the
+/// handler is servicing a device specific exception (interrupt).
+///
+/// `#[exception] fn Name(..` overrides the default handler for the exception with the given `Name`.
+/// These handlers must have signature `[unsafe] fn() [-> !]`. When overriding these other exception
+/// it's possible to add state to them by declaring `static mut` variables at the beginning of the
+/// body of the function. These variables will be safe to access from the function body.
+///
+/// # Properties
+///
+/// Exception handlers can only be called by the hardware. Other parts of the program can't refer to
+/// the exception handlers, much less invoke them as if they were functions.
+///
+/// `static mut` variables declared within an exception handler are safe to access and can be used
+/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
+/// the attribute will help by making a transformation to the source code: for this reason a
+/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
+///
+/// # Examples
+///
+/// - Setting the `HardFault` handler
+///
+/// ```
+/// # extern crate cortex_m_rt;
+/// # extern crate cortex_m_rt_macros;
+/// # use cortex_m_rt_macros::exception;
+/// #[exception]
+/// fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
+///     // prints the exception frame as a panic message
+///     panic!("{:#?}", ef);
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// - Setting the default handler
+///
+/// ```
+/// # use cortex_m_rt_macros::exception;
+/// #[exception]
+/// fn DefaultHandler(irqn: i16) {
+///     println!("IRQn = {}", irqn);
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// - Overriding the `SysTick` handler
+///
+/// ```
+/// extern crate cortex_m_rt as rt;
+///
+/// use rt::exception;
+///
+/// #[exception]
+/// fn SysTick() {
+///     static mut COUNT: i32 = 0;
+///
+///     // `COUNT` is safe to access and has type `&mut i32`
+///     *COUNT += 1;
+///
+///     println!("{}", COUNT);
+/// }
+///
+/// # fn main() {}
+/// ```
+#[proc_macro_attribute]
+pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
+    let f = parse_macro_input!(input as ItemFn);
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    let fspan = f.span();
+    let ident = f.ident;
+
+    enum Exception {
+        DefaultHandler,
+        HardFault,
+        Other,
+    }
+
+    let ident_s = ident.to_string();
+    let exn = match &*ident_s {
+        "DefaultHandler" => Exception::DefaultHandler,
+        "HardFault" => Exception::HardFault,
+        // NOTE that at this point we don't check if the exception is available on the target (e.g.
+        // MemoryManagement is not available on Cortex-M0)
+        "NonMaskableInt" | "MemoryManagement" | "BusFault" | "UsageFault" | "SecureFault"
+        | "SVCall" | "DebugMonitor" | "PendSV" | "SysTick" => Exception::Other,
+        _ => {
+            return parse::Error::new(ident.span(), "This is not a valid exception name")
+                .to_compile_error()
+                .into();
+        }
+    };
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let block = f.block;
+    let stmts = block.stmts;
+    let unsafety = f.unsafety;
+
+    let hash = random_ident();
+    match exn {
+        Exception::DefaultHandler => {
+            let valid_signature = f.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.abi.is_none()
+                && f.decl.inputs.len() == 1
+                && f.decl.generics.params.is_empty()
+                && f.decl.generics.where_clause.is_none()
+                && f.decl.variadic.is_none()
+                && match f.decl.output {
+                    ReturnType::Default => true,
+                    ReturnType::Type(_, ref ty) => match **ty {
+                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                        Type::Never(..) => true,
+                        _ => false,
+                    },
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    "`DefaultHandler` must have signature `[unsafe] fn(i16) [-> !]`",
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            let arg = match f.decl.inputs[0] {
+                FnArg::Captured(ref arg) => arg,
+                _ => unreachable!(),
+            };
+
+            quote!(
+                #[export_name = #ident_s]
+                #(#attrs)*
+                pub #unsafety extern "C" fn #hash() {
+                    extern crate core;
+
+                    const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
+
+                    let #arg = unsafe { core::ptr::read(SCB_ICSR) as u8 as i16 - 16 };
+
+                    #(#stmts)*
+                }
+            )
+            .into()
+        }
+        Exception::HardFault => {
+            let valid_signature = f.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.abi.is_none()
+                && f.decl.inputs.len() == 1
+                && match f.decl.inputs[0] {
+                    FnArg::Captured(ref arg) => match arg.ty {
+                        Type::Reference(ref r) => r.lifetime.is_none() && r.mutability.is_none(),
+                        _ => false,
+                    },
+                    _ => false,
+                }
+                && f.decl.generics.params.is_empty()
+                && f.decl.generics.where_clause.is_none()
+                && f.decl.variadic.is_none()
+                && match f.decl.output {
+                    ReturnType::Default => false,
+                    ReturnType::Type(_, ref ty) => match **ty {
+                        Type::Never(_) => true,
+                        _ => false,
+                    },
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    "`HardFault` handler must have signature `[unsafe] fn(&ExceptionFrame) -> !`",
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            let arg = match f.decl.inputs[0] {
+                FnArg::Captured(ref arg) => arg,
+                _ => unreachable!(),
+            };
+
+            let pat = &arg.pat;
+
+            quote!(
+                #[export_name = "HardFault"]
+                #[link_section = ".HardFault.user"]
+                #(#attrs)*
+                pub #unsafety extern "C" fn #hash(#arg) -> ! {
+                    extern crate cortex_m_rt;
+
+                    // further type check of the input argument
+                    let #pat: &cortex_m_rt::ExceptionFrame = #pat;
+                    #(#stmts)*
+                }
+            )
+            .into()
+        }
+        Exception::Other => {
+            let valid_signature = f.constness.is_none()
+                && f.vis == Visibility::Inherited
+                && f.abi.is_none()
+                && f.decl.inputs.is_empty()
+                && f.decl.generics.params.is_empty()
+                && f.decl.generics.where_clause.is_none()
+                && f.decl.variadic.is_none()
+                && match f.decl.output {
+                    ReturnType::Default => true,
+                    ReturnType::Type(_, ref ty) => match **ty {
+                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                        Type::Never(..) => true,
+                        _ => false,
+                    },
+                };
+
+            if !valid_signature {
+                return parse::Error::new(
+                    fspan,
+                    "`#[exception]` handlers other than `DefaultHandler` and `HardFault` must have \
+                     signature `[unsafe] fn() [-> !]`",
+                )
+                .to_compile_error()
+                .into();
+            }
+
+            let (statics, stmts) = match extract_static_muts(stmts) {
+                Err(e) => return e.to_compile_error().into(),
+                Ok(x) => x,
+            };
+
+            let vars = statics
+                .into_iter()
+                .map(|var| {
+                    let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
+                    let ident = var.ident;
+                    let ty = var.ty;
+                    let expr = var.expr;
+
+                    quote!(
+                        #[allow(non_snake_case)]
+                        #(#cfgs)*
+                        let #ident: &mut #ty = unsafe {
+                            #(#attrs)*
+                            #(#cfgs)*
+                            static mut #ident: #ty = #expr;
+
+                            &mut #ident
+                        };
+                    )
+                })
+                .collect::<Vec<_>>();
+
+            quote!(
+                #[export_name = #ident_s]
+                #(#attrs)*
+                pub #unsafety extern "C" fn #hash() {
+                    extern crate cortex_m_rt;
+
+                    // check that this exception actually exists
+                    cortex_m_rt::Exception::#ident;
+
+                    #(#vars)*
+
+                    #(#stmts)*
+                }
+            )
+            .into()
+        }
+    }
+}
+
+/// Attribute to declare an interrupt (AKA device-specific exception) handler
+///
+/// **IMPORTANT**: If you are using Rust 1.30 this attribute must be used on reachable items (i.e.
+/// there must be no private modules between the item and the root of the crate); if the item is in
+/// the root of the crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31
+/// and newer releases.
+///
+/// **NOTE**: This attribute is exposed by `cortex-m-rt` only when the `device` feature is enabled.
+/// However, that export is not meant to be used directly -- using it will result in a compilation
+/// error. You should instead use the device crate (usually generated using `svd2rust`) re-export of
+/// that attribute. You need to use the re-export to have the compiler check that the interrupt
+/// exists on the target device.
+///
+/// # Syntax
+///
+/// ``` ignore
+/// extern crate device;
+///
+/// // the attribute comes from the device crate not from cortex-m-rt
+/// use device::interrupt;
+///
+/// #[interrupt]
+/// fn USART1() {
+///     // ..
+/// }
+/// ```
+///
+/// where the name of the function must be one of the device interrupts.
+///
+/// # Usage
+///
+/// `#[interrupt] fn Name(..` overrides the default handler for the interrupt with the given `Name`.
+/// These handlers must have signature `[unsafe] fn() [-> !]`. It's possible to add state to these
+/// handlers by declaring `static mut` variables at the beginning of the body of the function. These
+/// variables will be safe to access from the function body.
+///
+/// If the interrupt handler has not been overridden it will be dispatched by the default exception
+/// handler (`DefaultHandler`).
+///
+/// # Properties
+///
+/// Interrupts handlers can only be called by the hardware. Other parts of the program can't refer
+/// to the interrupt handlers, much less invoke them as if they were functions.
+///
+/// `static mut` variables declared within an interrupt handler are safe to access and can be used
+/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
+/// the attribute will help by making a transformation to the source code: for this reason a
+/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
+///
+/// # Examples
+///
+/// - Using state within an interrupt handler
+///
+/// ``` ignore
+/// extern crate device;
+///
+/// use device::interrupt;
+///
+/// #[interrupt]
+/// fn TIM2() {
+///     static mut COUNT: i32 = 0;
+///
+///     // `COUNT` is safe to access and has type `&mut i32`
+///     *COUNT += 1;
+///
+///     println!("{}", COUNT);
+/// }
+/// ```
+#[proc_macro_attribute]
+pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
+    let f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function");
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    let fspan = f.span();
+    let ident = f.ident;
+    let ident_s = ident.to_string();
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let block = f.block;
+    let stmts = block.stmts;
+    let unsafety = f.unsafety;
+
+    let valid_signature = f.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.abi.is_none()
+        && f.decl.inputs.is_empty()
+        && f.decl.generics.params.is_empty()
+        && f.decl.generics.where_clause.is_none()
+        && f.decl.variadic.is_none()
+        && match f.decl.output {
+            ReturnType::Default => true,
+            ReturnType::Type(_, ref ty) => match **ty {
+                Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                Type::Never(..) => true,
+                _ => false,
+            },
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            fspan,
+            "`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    let (statics, stmts) = match extract_static_muts(stmts) {
+        Err(e) => return e.to_compile_error().into(),
+        Ok(x) => x,
+    };
+
+    let vars = statics
+        .into_iter()
+        .map(|var| {
+            let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
+            let ident = var.ident;
+            let ty = var.ty;
+            let expr = var.expr;
+
+            quote!(
+                #[allow(non_snake_case)]
+                #(#cfgs)*
+                let #ident: &mut #ty = unsafe {
+                    #(#attrs)*
+                    #(#cfgs)*
+                    static mut #ident: #ty = #expr;
+
+                    &mut #ident
+                };
+            )
+        })
+        .collect::<Vec<_>>();
+
+    let hash = random_ident();
+    quote!(
+        #[export_name = #ident_s]
+        #(#attrs)*
+        pub #unsafety extern "C" fn #hash() {
+            interrupt::#ident;
+
+            #(#vars)*
+
+            #(#stmts)*
+        }
+    )
+    .into()
+}
+
+/// Attribute to mark which function will be called at the beginning of the reset handler.
+///
+/// **IMPORTANT**: This attribute can appear at most *once* in the dependency graph. Also, if you
+/// are using Rust 1.30 the attribute must be used on a reachable item (i.e. there must be no
+/// private modules between the item and the root of the crate); if the item is in the root of the
+/// crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31 and newer
+/// releases.
+///
+/// The function must have the signature of `unsafe fn()`.
+///
+/// The function passed will be called before static variables are initialized. Any access of static
+/// variables will result in undefined behavior.
+///
+/// # Examples
+///
+/// ```
+/// # use cortex_m_rt_macros::pre_init;
+/// #[pre_init]
+/// unsafe fn before_main() {
+///     // do something here
+/// }
+///
+/// # fn main() {}
+/// ```
+#[proc_macro_attribute]
+pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
+    let f = parse_macro_input!(input as ItemFn);
+
+    // check the function signature
+    let valid_signature = f.constness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.unsafety.is_some()
+        && f.abi.is_none()
+        && f.decl.inputs.is_empty()
+        && f.decl.generics.params.is_empty()
+        && f.decl.generics.where_clause.is_none()
+        && f.decl.variadic.is_none()
+        && match f.decl.output {
+            ReturnType::Default => true,
+            ReturnType::Type(_, ref ty) => match **ty {
+                Type::Tuple(ref tuple) => tuple.elems.is_empty(),
+                _ => false,
+            },
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            f.span(),
+            "`#[pre_init]` function must have signature `unsafe fn()`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let ident = f.ident;
+    let block = f.block;
+
+    quote!(
+        #[export_name = "__pre_init"]
+        #(#attrs)*
+        pub unsafe fn #ident() #block
+    )
+    .into()
+}
+
+// Creates a random identifier
+fn random_ident() -> Ident {
+    let secs = SystemTime::now()
+        .duration_since(UNIX_EPOCH)
+        .unwrap()
+        .as_secs();
+
+    let count: u64 = CALL_COUNT.fetch_add(1, Ordering::SeqCst) as u64;
+    let mut seed: [u8; 16] = [0; 16];
+
+    for (i, v) in seed.iter_mut().take(8).enumerate() {
+        *v = ((secs >> (i * 8)) & 0xFF) as u8
+    }
+
+    for (i, v) in seed.iter_mut().skip(8).enumerate() {
+        *v = ((count >> (i * 8)) & 0xFF) as u8
+    }
+
+    let mut rng = rand::rngs::SmallRng::from_seed(seed);
+    Ident::new(
+        &(0..16)
+            .map(|i| {
+                if i == 0 || rng.gen() {
+                    ('a' as u8 + rng.gen::<u8>() % 25) as char
+                } else {
+                    ('0' as u8 + rng.gen::<u8>() % 10) as char
+                }
+            })
+            .collect::<String>(),
+        Span::call_site(),
+    )
+}
+
+/// Extracts `static mut` vars from the beginning of the given statements
+fn extract_static_muts(stmts: Vec<Stmt>) -> Result<(Vec<ItemStatic>, Vec<Stmt>), parse::Error> {
+    let mut istmts = stmts.into_iter();
+
+    let mut seen = HashSet::new();
+    let mut statics = vec![];
+    let mut stmts = vec![];
+    while let Some(stmt) = istmts.next() {
+        match stmt {
+            Stmt::Item(Item::Static(var)) => {
+                if var.mutability.is_some() {
+                    if seen.contains(&var.ident) {
+                        return Err(parse::Error::new(
+                            var.ident.span(),
+                            format!("the name `{}` is defined multiple times", var.ident),
+                        ));
+                    }
+
+                    seen.insert(var.ident.clone());
+                    statics.push(var);
+                } else {
+                    stmts.push(Stmt::Item(Item::Static(var)));
+                }
+            }
+            _ => {
+                stmts.push(stmt);
+                break;
+            }
+        }
+    }
+
+    stmts.extend(istmts);
+
+    Ok((statics, stmts))
+}
+
+fn extract_cfgs(attrs: Vec<Attribute>) -> (Vec<Attribute>, Vec<Attribute>) {
+    let mut cfgs = vec![];
+    let mut not_cfgs = vec![];
+
+    for attr in attrs {
+        if eq(&attr, "cfg") {
+            cfgs.push(attr);
+        } else {
+            not_cfgs.push(attr);
+        }
+    }
+
+    (cfgs, not_cfgs)
+}
+
+/// Returns `true` if `attr.path` matches `name`
+fn eq(attr: &Attribute, name: &str) -> bool {
+    attr.style == AttrStyle::Outer && attr.path.segments.len() == 1 && {
+        let pair = attr.path.segments.first().unwrap();
+        let segment = pair.value();
+        segment.arguments == PathArguments::None && segment.ident.to_string() == name
+    }
+}

From 85efa3b0809c723fad14f30a6523dec05e508ae5 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 16:02:52 +0300
Subject: [PATCH 060/234] [macros] Fix Cargo.toml

---
 riscv-rt/macros/Cargo.toml | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index ba6db64f..84762ff3 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -1,12 +1,15 @@
 [package]
-authors = ["Jorge Aparicio <jorge@japaric.io>"]
+authors = [
+    "The RISC-V Team <risc-v@teams.rust-embedded.org>",
+    "Jorge Aparicio <jorge@japaric.io>",
+]
 categories = ["embedded", "no-std"]
-description = "Attributes re-exported in `cortex-m-rt`"
-documentation = "https://docs.rs/cortex-m-rt"
-keywords = ["arm", "cortex-m", "runtime", "startup"]
+description = "Attributes re-exported in `riscv-rt`"
+documentation = "https://docs.rs/riscv-rt"
+keywords = ["riscv", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
-name = "cortex-m-rt-macros"
-repository = "https://github.com/japaric/cortex-m-rt"
+name = "riscv-rt-macros"
+repository = "https://github.com/rust-embedded/riscv-rt"
 version = "0.1.5"
 
 [lib]
@@ -25,4 +28,4 @@ version = "0.5.5"
 default-features = false
 
 [dev-dependencies]
-cortex-m-rt = { path = "..", version = "0.6.0" }
+riscv-rt = { path = "..", version = "0.4.0" }

From 1ad79f8fb76efef8b9efb162414e961d89c170e1 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 16:03:43 +0300
Subject: [PATCH 061/234] [macros] Replace cortex-m with riscv

---
 riscv-rt/macros/src/lib.rs | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 7528586e..d345a4b1 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -53,7 +53,7 @@ use proc_macro::TokenStream;
 ///
 /// ``` no_run
 /// # #![no_main]
-/// # use cortex_m_rt_macros::entry;
+/// # use riscv_rt_macros::entry;
 /// #[entry]
 /// fn main() -> ! {
 ///     loop {
@@ -66,7 +66,7 @@ use proc_macro::TokenStream;
 ///
 /// ``` no_run
 /// # #![no_main]
-/// # use cortex_m_rt_macros::entry;
+/// # use riscv_rt_macros::entry;
 /// #[entry]
 /// fn main() -> ! {
 ///     static mut FOO: u32 = 0;
@@ -169,7 +169,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 /// # Syntax
 ///
 /// ```
-/// # use cortex_m_rt_macros::exception;
+/// # use riscv_rt_macros::exception;
 /// #[exception]
 /// fn SysTick() {
 ///     // ..
@@ -228,11 +228,11 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 /// - Setting the `HardFault` handler
 ///
 /// ```
-/// # extern crate cortex_m_rt;
-/// # extern crate cortex_m_rt_macros;
-/// # use cortex_m_rt_macros::exception;
+/// # extern crate riscv_rt;
+/// # extern crate riscv_rt_macros;
+/// # use riscv_rt_macros::exception;
 /// #[exception]
-/// fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
+/// fn HardFault(ef: &riscv_rt::ExceptionFrame) -> ! {
 ///     // prints the exception frame as a panic message
 ///     panic!("{:#?}", ef);
 /// }
@@ -243,7 +243,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 /// - Setting the default handler
 ///
 /// ```
-/// # use cortex_m_rt_macros::exception;
+/// # use riscv_rt_macros::exception;
 /// #[exception]
 /// fn DefaultHandler(irqn: i16) {
 ///     println!("IRQn = {}", irqn);
@@ -255,7 +255,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 /// - Overriding the `SysTick` handler
 ///
 /// ```
-/// extern crate cortex_m_rt as rt;
+/// extern crate riscv_rt as rt;
 ///
 /// use rt::exception;
 ///
@@ -403,10 +403,10 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
                 #[link_section = ".HardFault.user"]
                 #(#attrs)*
                 pub #unsafety extern "C" fn #hash(#arg) -> ! {
-                    extern crate cortex_m_rt;
+                    extern crate riscv_rt;
 
                     // further type check of the input argument
-                    let #pat: &cortex_m_rt::ExceptionFrame = #pat;
+                    let #pat: &riscv_rt::ExceptionFrame = #pat;
                     #(#stmts)*
                 }
             )
@@ -470,10 +470,10 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
                 #[export_name = #ident_s]
                 #(#attrs)*
                 pub #unsafety extern "C" fn #hash() {
-                    extern crate cortex_m_rt;
+                    extern crate riscv_rt;
 
                     // check that this exception actually exists
-                    cortex_m_rt::Exception::#ident;
+                    riscv_rt::Exception::#ident;
 
                     #(#vars)*
 
@@ -492,7 +492,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
 /// the root of the crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31
 /// and newer releases.
 ///
-/// **NOTE**: This attribute is exposed by `cortex-m-rt` only when the `device` feature is enabled.
+/// **NOTE**: This attribute is exposed by `riscv-rt` only when the `device` feature is enabled.
 /// However, that export is not meant to be used directly -- using it will result in a compilation
 /// error. You should instead use the device crate (usually generated using `svd2rust`) re-export of
 /// that attribute. You need to use the re-export to have the compiler check that the interrupt
@@ -503,7 +503,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
 /// ``` ignore
 /// extern crate device;
 ///
-/// // the attribute comes from the device crate not from cortex-m-rt
+/// // the attribute comes from the device crate not from riscv-rt
 /// use device::interrupt;
 ///
 /// #[interrupt]
@@ -656,7 +656,7 @@ pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
 /// # Examples
 ///
 /// ```
-/// # use cortex_m_rt_macros::pre_init;
+/// # use riscv_rt_macros::pre_init;
 /// #[pre_init]
 /// unsafe fn before_main() {
 ///     // do something here

From f981ee60ef1b400576a87db73b60febb6746188a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 16:08:12 +0300
Subject: [PATCH 062/234] Use proc-macro `entry`

---
 riscv-rt/Cargo.toml |  1 +
 riscv-rt/src/lib.rs | 38 ++++++++------------------------------
 2 files changed, 9 insertions(+), 30 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 28536baa..084e9e85 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,6 +11,7 @@ license = "ISC"
 [dependencies]
 r0 = "0.2.2"
 riscv = "0.5.0"
+riscv-rt-macros = { path = "macros", version = "0.1.5" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index c430f412..88db9d1a 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -8,7 +8,7 @@
 //!
 //! - Before main initialization of the FPU (for targets that have a FPU).
 //!
-//! - An `entry!` macro to declare the entry point of the program.
+//! - `#[entry]` to declare the entry point of the program
 //!
 //! - A linker script that encodes the memory layout of a generic RISC-V
 //!   microcontroller. This linker script is missing some information that must
@@ -46,8 +46,8 @@
 //! use riscv_rt::entry;
 //!
 //! // use `main` as the entry point of this application
-//! entry!(main);
-//!
+//! // `main` is not allowed to return
+//! #[entry]
 //! fn main() -> ! {
 //!     // do something here
 //!     loop { }
@@ -187,8 +187,11 @@
 #![deny(warnings)]
 
 extern crate riscv;
+extern crate riscv_rt_macros as macros;
 extern crate r0;
 
+pub use macros::entry;
+
 use riscv::register::{mstatus, mtvec};
 
 extern "C" {
@@ -215,8 +218,8 @@ extern "C" {
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
 pub extern "C" fn start_rust() -> ! {
-    extern "C" {
-        // This symbol will be provided by the user via the `entry!` macro
+    extern "Rust" {
+        // This symbol will be provided by the user via `#[entry]`
         fn main() -> !;
     }
 
@@ -236,31 +239,6 @@ pub extern "C" fn start_rust() -> ! {
 }
 
 
-/// Macro to define the entry point of the program
-///
-/// **NOTE** This macro must be invoked once and must be invoked from an accessible module, ideally
-/// from the root of the crate.
-///
-/// Usage: `entry!(path::to::entry::point)`
-///
-/// The specified function will be called by the reset handler *after* RAM has been initialized.
-///
-/// The signature of the specified function must be `fn() -> !` (never ending function).
-#[macro_export]
-macro_rules! entry {
-    ($path:expr) => {
-        #[inline(never)]
-        #[export_name = "main"]
-        pub extern "C" fn __impl_main() -> ! {
-            // validate the signature of the program entry point
-            let f: fn() -> ! = $path;
-
-            f()
-        }
-    };
-}
-
-
 /// Trap entry point rust (_start_trap_rust)
 ///
 /// mcause is read to determine the cause of the trap. XLEN-1 bit indicates

From f11f0523906e0d166b3e23acc5dcc29df7dd0fe9 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 17:23:30 +0300
Subject: [PATCH 063/234] Add 'pre_init' attribute

---
 riscv-rt/link.x     |  5 +++++
 riscv-rt/src/lib.rs | 36 +++++++++++++++++++++++++-----------
 2 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index c172f746..3cccb3ca 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -5,6 +5,11 @@ PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
 
 PROVIDE(trap_handler = default_trap_handler);
 
+/* # Pre-initialization function */
+/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
+   then the function this points to will be called before the RAM is initialized. */
+PROVIDE(__pre_init = default_pre_init);
+
 SECTIONS
 {
   PROVIDE(_stext = ORIGIN(FLASH));
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 88db9d1a..1dc606af 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -9,6 +9,7 @@
 //! - Before main initialization of the FPU (for targets that have a FPU).
 //!
 //! - `#[entry]` to declare the entry point of the program
+//! - `#[pre_init]` to run code *before* `static` variables are initialized
 //!
 //! - A linker script that encodes the memory layout of a generic RISC-V
 //!   microcontroller. This linker script is missing some information that must
@@ -180,6 +181,14 @@
 //!     }
 //! }
 //! ```
+//!
+//! ## `pre_init!`
+//!
+//! A user-defined function can be run at the start of the reset handler, before RAM is
+//! initialized. The macro `pre_init!` can be called to set the function to be run. The function is
+//! intended to perform actions that cannot wait the time it takes for RAM to be initialized, such
+//! as disabling a watchdog. As the function is called before RAM is initialized, any access of
+//! static variables will result in undefined behavior.
 
 // NOTE: Adapted from cortex-m/src/lib.rs
 #![no_std]
@@ -190,7 +199,7 @@ extern crate riscv;
 extern crate riscv_rt_macros as macros;
 extern crate r0;
 
-pub use macros::entry;
+pub use macros::{entry, pre_init};
 
 use riscv::register::{mstatus, mtvec};
 
@@ -217,25 +226,26 @@ extern "C" {
 /// never returns.
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
-pub extern "C" fn start_rust() -> ! {
+pub unsafe extern "C" fn start_rust() -> ! {
     extern "Rust" {
         // This symbol will be provided by the user via `#[entry]`
         fn main() -> !;
-    }
 
-    unsafe {
-        r0::zero_bss(&mut _sbss, &mut _ebss);
-        r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+        // This symbol will be provided by the user via `#[pre_init]`
+        fn __pre_init();
     }
 
+    __pre_init();
+
+    r0::zero_bss(&mut _sbss, &mut _ebss);
+    r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+
     // TODO: Enable FPU when available
 
-    unsafe {
-        // Set mtvec to _start_trap
-        mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);
+    // Set mtvec to _start_trap
+    mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);
 
-        main();
-    }
+    main();
 }
 
 
@@ -265,3 +275,7 @@ pub extern "C" fn start_trap_rust() {
 /// Default Trap Handler
 #[no_mangle]
 pub fn default_trap_handler() {}
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "Rust" fn default_pre_init() {}

From 253aa88fff9561126ac4f2504493f0e50af76bcd Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 17:24:26 +0300
Subject: [PATCH 064/234] [macros] Remove 'static mut' hack

---
 riscv-rt/macros/src/lib.rs | 234 +------------------------------------
 1 file changed, 4 insertions(+), 230 deletions(-)

diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index d345a4b1..605f7c04 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -12,12 +12,10 @@ extern crate syn;
 use proc_macro2::Span;
 use rand::Rng;
 use rand::SeedableRng;
-use std::collections::HashSet;
 use std::sync::atomic::{AtomicUsize, Ordering};
 use std::time::{SystemTime, UNIX_EPOCH};
 use syn::{
-    parse, spanned::Spanned, AttrStyle, Attribute, FnArg, Ident, Item, ItemFn, ItemStatic,
-    PathArguments, ReturnType, Stmt, Type, Visibility,
+    parse, spanned::Spanned, FnArg, Ident, ItemFn, ReturnType, Type, Visibility,
 };
 
 static CALL_COUNT: AtomicUsize = AtomicUsize::new(0);
@@ -42,11 +40,6 @@ use proc_macro::TokenStream;
 /// The entry point will be called by the reset handler. The program can't reference to the entry
 /// point, much less invoke it.
 ///
-/// `static mut` variables declared within the entry point are safe to access. The compiler can't
-/// prove this is safe so the attribute will help by making a transformation to the source code: for
-/// this reason a variable like `static mut FOO: u32` will become `let FOO: &'static mut u32;`. Note
-/// that `&'static mut` references have move semantics.
-///
 /// # Examples
 ///
 /// - Simple entry point
@@ -61,26 +54,6 @@ use proc_macro::TokenStream;
 ///     }
 /// }
 /// ```
-///
-/// - `static mut` variables local to the entry point are safe to modify.
-///
-/// ``` no_run
-/// # #![no_main]
-/// # use riscv_rt_macros::entry;
-/// #[entry]
-/// fn main() -> ! {
-///     static mut FOO: u32 = 0;
-///
-///     let foo: &'static mut u32 = FOO;
-///     assert_eq!(*foo, 0);
-///     *foo = 1;
-///     assert_eq!(*foo, 1);
-///
-///     loop {
-///         /* .. */
-///     }
-/// }
-/// ```
 #[proc_macro_attribute]
 pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
@@ -120,39 +93,12 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let attrs = f.attrs;
     let unsafety = f.unsafety;
     let hash = random_ident();
-    let (statics, stmts) = match extract_static_muts(f.block.stmts) {
-        Err(e) => return e.to_compile_error().into(),
-        Ok(x) => x,
-    };
-
-    let vars = statics
-        .into_iter()
-        .map(|var| {
-            let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
-            let ident = var.ident;
-            let ty = var.ty;
-            let expr = var.expr;
-
-            quote!(
-                #[allow(non_snake_case)]
-                #(#cfgs)*
-                let #ident: &'static mut #ty = unsafe {
-                    #(#attrs)*
-                    #(#cfgs)*
-                    static mut #ident: #ty = #expr;
-
-                    &mut #ident
-                };
-            )
-        })
-        .collect::<Vec<_>>();
+    let stmts = f.block.stmts;
 
     quote!(
         #[export_name = "main"]
         #(#attrs)*
         pub #unsafety fn #hash() -> ! {
-            #(#vars)*
-
             #(#stmts)*
         }
     )
@@ -209,20 +155,13 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 /// handler is servicing a device specific exception (interrupt).
 ///
 /// `#[exception] fn Name(..` overrides the default handler for the exception with the given `Name`.
-/// These handlers must have signature `[unsafe] fn() [-> !]`. When overriding these other exception
-/// it's possible to add state to them by declaring `static mut` variables at the beginning of the
-/// body of the function. These variables will be safe to access from the function body.
+/// These handlers must have signature `[unsafe] fn() [-> !]`.
 ///
 /// # Properties
 ///
 /// Exception handlers can only be called by the hardware. Other parts of the program can't refer to
 /// the exception handlers, much less invoke them as if they were functions.
 ///
-/// `static mut` variables declared within an exception handler are safe to access and can be used
-/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
-/// the attribute will help by making a transformation to the source code: for this reason a
-/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
-///
 /// # Examples
 ///
 /// - Setting the `HardFault` handler
@@ -251,26 +190,6 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 ///
 /// # fn main() {}
 /// ```
-///
-/// - Overriding the `SysTick` handler
-///
-/// ```
-/// extern crate riscv_rt as rt;
-///
-/// use rt::exception;
-///
-/// #[exception]
-/// fn SysTick() {
-///     static mut COUNT: i32 = 0;
-///
-///     // `COUNT` is safe to access and has type `&mut i32`
-///     *COUNT += 1;
-///
-///     println!("{}", COUNT);
-/// }
-///
-/// # fn main() {}
-/// ```
 #[proc_macro_attribute]
 pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
@@ -439,33 +358,6 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
                 .into();
             }
 
-            let (statics, stmts) = match extract_static_muts(stmts) {
-                Err(e) => return e.to_compile_error().into(),
-                Ok(x) => x,
-            };
-
-            let vars = statics
-                .into_iter()
-                .map(|var| {
-                    let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
-                    let ident = var.ident;
-                    let ty = var.ty;
-                    let expr = var.expr;
-
-                    quote!(
-                        #[allow(non_snake_case)]
-                        #(#cfgs)*
-                        let #ident: &mut #ty = unsafe {
-                            #(#attrs)*
-                            #(#cfgs)*
-                            static mut #ident: #ty = #expr;
-
-                            &mut #ident
-                        };
-                    )
-                })
-                .collect::<Vec<_>>();
-
             quote!(
                 #[export_name = #ident_s]
                 #(#attrs)*
@@ -475,8 +367,6 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
                     // check that this exception actually exists
                     riscv_rt::Exception::#ident;
 
-                    #(#vars)*
-
                     #(#stmts)*
                 }
             )
@@ -517,9 +407,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
 /// # Usage
 ///
 /// `#[interrupt] fn Name(..` overrides the default handler for the interrupt with the given `Name`.
-/// These handlers must have signature `[unsafe] fn() [-> !]`. It's possible to add state to these
-/// handlers by declaring `static mut` variables at the beginning of the body of the function. These
-/// variables will be safe to access from the function body.
+/// These handlers must have signature `[unsafe] fn() [-> !]`.
 ///
 /// If the interrupt handler has not been overridden it will be dispatched by the default exception
 /// handler (`DefaultHandler`).
@@ -528,31 +416,6 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
 ///
 /// Interrupts handlers can only be called by the hardware. Other parts of the program can't refer
 /// to the interrupt handlers, much less invoke them as if they were functions.
-///
-/// `static mut` variables declared within an interrupt handler are safe to access and can be used
-/// to preserve state across invocations of the handler. The compiler can't prove this is safe so
-/// the attribute will help by making a transformation to the source code: for this reason a
-/// variable like `static mut FOO: u32` will become `let FOO: &mut u32;`.
-///
-/// # Examples
-///
-/// - Using state within an interrupt handler
-///
-/// ``` ignore
-/// extern crate device;
-///
-/// use device::interrupt;
-///
-/// #[interrupt]
-/// fn TIM2() {
-///     static mut COUNT: i32 = 0;
-///
-///     // `COUNT` is safe to access and has type `&mut i32`
-///     *COUNT += 1;
-///
-///     println!("{}", COUNT);
-/// }
-/// ```
 #[proc_macro_attribute]
 pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
     let f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function");
@@ -598,33 +461,6 @@ pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
         .into();
     }
 
-    let (statics, stmts) = match extract_static_muts(stmts) {
-        Err(e) => return e.to_compile_error().into(),
-        Ok(x) => x,
-    };
-
-    let vars = statics
-        .into_iter()
-        .map(|var| {
-            let (ref cfgs, ref attrs) = extract_cfgs(var.attrs);
-            let ident = var.ident;
-            let ty = var.ty;
-            let expr = var.expr;
-
-            quote!(
-                #[allow(non_snake_case)]
-                #(#cfgs)*
-                let #ident: &mut #ty = unsafe {
-                    #(#attrs)*
-                    #(#cfgs)*
-                    static mut #ident: #ty = #expr;
-
-                    &mut #ident
-                };
-            )
-        })
-        .collect::<Vec<_>>();
-
     let hash = random_ident();
     quote!(
         #[export_name = #ident_s]
@@ -632,8 +468,6 @@ pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
         pub #unsafety extern "C" fn #hash() {
             interrupt::#ident;
 
-            #(#vars)*
-
             #(#stmts)*
         }
     )
@@ -745,63 +579,3 @@ fn random_ident() -> Ident {
         Span::call_site(),
     )
 }
-
-/// Extracts `static mut` vars from the beginning of the given statements
-fn extract_static_muts(stmts: Vec<Stmt>) -> Result<(Vec<ItemStatic>, Vec<Stmt>), parse::Error> {
-    let mut istmts = stmts.into_iter();
-
-    let mut seen = HashSet::new();
-    let mut statics = vec![];
-    let mut stmts = vec![];
-    while let Some(stmt) = istmts.next() {
-        match stmt {
-            Stmt::Item(Item::Static(var)) => {
-                if var.mutability.is_some() {
-                    if seen.contains(&var.ident) {
-                        return Err(parse::Error::new(
-                            var.ident.span(),
-                            format!("the name `{}` is defined multiple times", var.ident),
-                        ));
-                    }
-
-                    seen.insert(var.ident.clone());
-                    statics.push(var);
-                } else {
-                    stmts.push(Stmt::Item(Item::Static(var)));
-                }
-            }
-            _ => {
-                stmts.push(stmt);
-                break;
-            }
-        }
-    }
-
-    stmts.extend(istmts);
-
-    Ok((statics, stmts))
-}
-
-fn extract_cfgs(attrs: Vec<Attribute>) -> (Vec<Attribute>, Vec<Attribute>) {
-    let mut cfgs = vec![];
-    let mut not_cfgs = vec![];
-
-    for attr in attrs {
-        if eq(&attr, "cfg") {
-            cfgs.push(attr);
-        } else {
-            not_cfgs.push(attr);
-        }
-    }
-
-    (cfgs, not_cfgs)
-}
-
-/// Returns `true` if `attr.path` matches `name`
-fn eq(attr: &Attribute, name: &str) -> bool {
-    attr.style == AttrStyle::Outer && attr.path.segments.len() == 1 && {
-        let pair = attr.path.segments.first().unwrap();
-        let segment = pair.value();
-        segment.arguments == PathArguments::None && segment.ident.to_string() == name
-    }
-}

From 64fb6ad3122dbe38d71e6193d7e416a9c1197859 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 5 Mar 2019 21:40:03 +0300
Subject: [PATCH 065/234] [macros] Remove 'exception' and 'interrupt'
 attributes

---
 riscv-rt/macros/src/lib.rs | 371 +------------------------------------
 1 file changed, 1 insertion(+), 370 deletions(-)

diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 605f7c04..0a6bcdbb 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -15,7 +15,7 @@ use rand::SeedableRng;
 use std::sync::atomic::{AtomicUsize, Ordering};
 use std::time::{SystemTime, UNIX_EPOCH};
 use syn::{
-    parse, spanned::Spanned, FnArg, Ident, ItemFn, ReturnType, Type, Visibility,
+    parse, spanned::Spanned, Ident, ItemFn, ReturnType, Type, Visibility,
 };
 
 static CALL_COUNT: AtomicUsize = AtomicUsize::new(0);
@@ -105,375 +105,6 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     .into()
 }
 
-/// Attribute to declare an exception handler
-///
-/// **IMPORTANT**: If you are using Rust 1.30 this attribute must be used on reachable items (i.e.
-/// there must be no private modules between the item and the root of the crate); if the item is in
-/// the root of the crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31
-/// and newer releases.
-///
-/// # Syntax
-///
-/// ```
-/// # use riscv_rt_macros::exception;
-/// #[exception]
-/// fn SysTick() {
-///     // ..
-/// }
-///
-/// # fn main() {}
-/// ```
-///
-/// where the name of the function must be one of:
-///
-/// - `DefaultHandler`
-/// - `NonMaskableInt`
-/// - `HardFault`
-/// - `MemoryManagement` (a)
-/// - `BusFault` (a)
-/// - `UsageFault` (a)
-/// - `SecureFault` (b)
-/// - `SVCall`
-/// - `DebugMonitor` (a)
-/// - `PendSV`
-/// - `SysTick`
-///
-/// (a) Not available on Cortex-M0 variants (`thumbv6m-none-eabi`)
-///
-/// (b) Only available on ARMv8-M
-///
-/// # Usage
-///
-/// `#[exception] fn HardFault(..` sets the hard fault handler. The handler must have signature
-/// `[unsafe] fn(&ExceptionFrame) -> !`. This handler is not allowed to return as that can cause
-/// undefined behavior.
-///
-/// `#[exception] fn DefaultHandler(..` sets the *default* handler. All exceptions which have not
-/// been assigned a handler will be serviced by this handler. This handler must have signature
-/// `[unsafe] fn(irqn: i16) [-> !]`. `irqn` is the IRQ number (See CMSIS); `irqn` will be a negative
-/// number when the handler is servicing a core exception; `irqn` will be a positive number when the
-/// handler is servicing a device specific exception (interrupt).
-///
-/// `#[exception] fn Name(..` overrides the default handler for the exception with the given `Name`.
-/// These handlers must have signature `[unsafe] fn() [-> !]`.
-///
-/// # Properties
-///
-/// Exception handlers can only be called by the hardware. Other parts of the program can't refer to
-/// the exception handlers, much less invoke them as if they were functions.
-///
-/// # Examples
-///
-/// - Setting the `HardFault` handler
-///
-/// ```
-/// # extern crate riscv_rt;
-/// # extern crate riscv_rt_macros;
-/// # use riscv_rt_macros::exception;
-/// #[exception]
-/// fn HardFault(ef: &riscv_rt::ExceptionFrame) -> ! {
-///     // prints the exception frame as a panic message
-///     panic!("{:#?}", ef);
-/// }
-///
-/// # fn main() {}
-/// ```
-///
-/// - Setting the default handler
-///
-/// ```
-/// # use riscv_rt_macros::exception;
-/// #[exception]
-/// fn DefaultHandler(irqn: i16) {
-///     println!("IRQn = {}", irqn);
-/// }
-///
-/// # fn main() {}
-/// ```
-#[proc_macro_attribute]
-pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
-    let f = parse_macro_input!(input as ItemFn);
-
-    if !args.is_empty() {
-        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
-            .to_compile_error()
-            .into();
-    }
-
-    let fspan = f.span();
-    let ident = f.ident;
-
-    enum Exception {
-        DefaultHandler,
-        HardFault,
-        Other,
-    }
-
-    let ident_s = ident.to_string();
-    let exn = match &*ident_s {
-        "DefaultHandler" => Exception::DefaultHandler,
-        "HardFault" => Exception::HardFault,
-        // NOTE that at this point we don't check if the exception is available on the target (e.g.
-        // MemoryManagement is not available on Cortex-M0)
-        "NonMaskableInt" | "MemoryManagement" | "BusFault" | "UsageFault" | "SecureFault"
-        | "SVCall" | "DebugMonitor" | "PendSV" | "SysTick" => Exception::Other,
-        _ => {
-            return parse::Error::new(ident.span(), "This is not a valid exception name")
-                .to_compile_error()
-                .into();
-        }
-    };
-
-    // XXX should we blacklist other attributes?
-    let attrs = f.attrs;
-    let block = f.block;
-    let stmts = block.stmts;
-    let unsafety = f.unsafety;
-
-    let hash = random_ident();
-    match exn {
-        Exception::DefaultHandler => {
-            let valid_signature = f.constness.is_none()
-                && f.vis == Visibility::Inherited
-                && f.abi.is_none()
-                && f.decl.inputs.len() == 1
-                && f.decl.generics.params.is_empty()
-                && f.decl.generics.where_clause.is_none()
-                && f.decl.variadic.is_none()
-                && match f.decl.output {
-                    ReturnType::Default => true,
-                    ReturnType::Type(_, ref ty) => match **ty {
-                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
-                        Type::Never(..) => true,
-                        _ => false,
-                    },
-                };
-
-            if !valid_signature {
-                return parse::Error::new(
-                    fspan,
-                    "`DefaultHandler` must have signature `[unsafe] fn(i16) [-> !]`",
-                )
-                .to_compile_error()
-                .into();
-            }
-
-            let arg = match f.decl.inputs[0] {
-                FnArg::Captured(ref arg) => arg,
-                _ => unreachable!(),
-            };
-
-            quote!(
-                #[export_name = #ident_s]
-                #(#attrs)*
-                pub #unsafety extern "C" fn #hash() {
-                    extern crate core;
-
-                    const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
-
-                    let #arg = unsafe { core::ptr::read(SCB_ICSR) as u8 as i16 - 16 };
-
-                    #(#stmts)*
-                }
-            )
-            .into()
-        }
-        Exception::HardFault => {
-            let valid_signature = f.constness.is_none()
-                && f.vis == Visibility::Inherited
-                && f.abi.is_none()
-                && f.decl.inputs.len() == 1
-                && match f.decl.inputs[0] {
-                    FnArg::Captured(ref arg) => match arg.ty {
-                        Type::Reference(ref r) => r.lifetime.is_none() && r.mutability.is_none(),
-                        _ => false,
-                    },
-                    _ => false,
-                }
-                && f.decl.generics.params.is_empty()
-                && f.decl.generics.where_clause.is_none()
-                && f.decl.variadic.is_none()
-                && match f.decl.output {
-                    ReturnType::Default => false,
-                    ReturnType::Type(_, ref ty) => match **ty {
-                        Type::Never(_) => true,
-                        _ => false,
-                    },
-                };
-
-            if !valid_signature {
-                return parse::Error::new(
-                    fspan,
-                    "`HardFault` handler must have signature `[unsafe] fn(&ExceptionFrame) -> !`",
-                )
-                .to_compile_error()
-                .into();
-            }
-
-            let arg = match f.decl.inputs[0] {
-                FnArg::Captured(ref arg) => arg,
-                _ => unreachable!(),
-            };
-
-            let pat = &arg.pat;
-
-            quote!(
-                #[export_name = "HardFault"]
-                #[link_section = ".HardFault.user"]
-                #(#attrs)*
-                pub #unsafety extern "C" fn #hash(#arg) -> ! {
-                    extern crate riscv_rt;
-
-                    // further type check of the input argument
-                    let #pat: &riscv_rt::ExceptionFrame = #pat;
-                    #(#stmts)*
-                }
-            )
-            .into()
-        }
-        Exception::Other => {
-            let valid_signature = f.constness.is_none()
-                && f.vis == Visibility::Inherited
-                && f.abi.is_none()
-                && f.decl.inputs.is_empty()
-                && f.decl.generics.params.is_empty()
-                && f.decl.generics.where_clause.is_none()
-                && f.decl.variadic.is_none()
-                && match f.decl.output {
-                    ReturnType::Default => true,
-                    ReturnType::Type(_, ref ty) => match **ty {
-                        Type::Tuple(ref tuple) => tuple.elems.is_empty(),
-                        Type::Never(..) => true,
-                        _ => false,
-                    },
-                };
-
-            if !valid_signature {
-                return parse::Error::new(
-                    fspan,
-                    "`#[exception]` handlers other than `DefaultHandler` and `HardFault` must have \
-                     signature `[unsafe] fn() [-> !]`",
-                )
-                .to_compile_error()
-                .into();
-            }
-
-            quote!(
-                #[export_name = #ident_s]
-                #(#attrs)*
-                pub #unsafety extern "C" fn #hash() {
-                    extern crate riscv_rt;
-
-                    // check that this exception actually exists
-                    riscv_rt::Exception::#ident;
-
-                    #(#stmts)*
-                }
-            )
-            .into()
-        }
-    }
-}
-
-/// Attribute to declare an interrupt (AKA device-specific exception) handler
-///
-/// **IMPORTANT**: If you are using Rust 1.30 this attribute must be used on reachable items (i.e.
-/// there must be no private modules between the item and the root of the crate); if the item is in
-/// the root of the crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31
-/// and newer releases.
-///
-/// **NOTE**: This attribute is exposed by `riscv-rt` only when the `device` feature is enabled.
-/// However, that export is not meant to be used directly -- using it will result in a compilation
-/// error. You should instead use the device crate (usually generated using `svd2rust`) re-export of
-/// that attribute. You need to use the re-export to have the compiler check that the interrupt
-/// exists on the target device.
-///
-/// # Syntax
-///
-/// ``` ignore
-/// extern crate device;
-///
-/// // the attribute comes from the device crate not from riscv-rt
-/// use device::interrupt;
-///
-/// #[interrupt]
-/// fn USART1() {
-///     // ..
-/// }
-/// ```
-///
-/// where the name of the function must be one of the device interrupts.
-///
-/// # Usage
-///
-/// `#[interrupt] fn Name(..` overrides the default handler for the interrupt with the given `Name`.
-/// These handlers must have signature `[unsafe] fn() [-> !]`.
-///
-/// If the interrupt handler has not been overridden it will be dispatched by the default exception
-/// handler (`DefaultHandler`).
-///
-/// # Properties
-///
-/// Interrupts handlers can only be called by the hardware. Other parts of the program can't refer
-/// to the interrupt handlers, much less invoke them as if they were functions.
-#[proc_macro_attribute]
-pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
-    let f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function");
-
-    if !args.is_empty() {
-        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
-            .to_compile_error()
-            .into();
-    }
-
-    let fspan = f.span();
-    let ident = f.ident;
-    let ident_s = ident.to_string();
-
-    // XXX should we blacklist other attributes?
-    let attrs = f.attrs;
-    let block = f.block;
-    let stmts = block.stmts;
-    let unsafety = f.unsafety;
-
-    let valid_signature = f.constness.is_none()
-        && f.vis == Visibility::Inherited
-        && f.abi.is_none()
-        && f.decl.inputs.is_empty()
-        && f.decl.generics.params.is_empty()
-        && f.decl.generics.where_clause.is_none()
-        && f.decl.variadic.is_none()
-        && match f.decl.output {
-            ReturnType::Default => true,
-            ReturnType::Type(_, ref ty) => match **ty {
-                Type::Tuple(ref tuple) => tuple.elems.is_empty(),
-                Type::Never(..) => true,
-                _ => false,
-            },
-        };
-
-    if !valid_signature {
-        return parse::Error::new(
-            fspan,
-            "`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`",
-        )
-        .to_compile_error()
-        .into();
-    }
-
-    let hash = random_ident();
-    quote!(
-        #[export_name = #ident_s]
-        #(#attrs)*
-        pub #unsafety extern "C" fn #hash() {
-            interrupt::#ident;
-
-            #(#stmts)*
-        }
-    )
-    .into()
-}
-
 /// Attribute to mark which function will be called at the beginning of the reset handler.
 ///
 /// **IMPORTANT**: This attribute can appear at most *once* in the dependency graph. Also, if you

From d2eff45f5930a8e808530673c3e719956a7bea82 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 7 Mar 2019 15:14:51 +0300
Subject: [PATCH 066/234] Fix documentation

---
 riscv-rt/macros/src/lib.rs | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 0a6bcdbb..91ef9117 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -29,9 +29,8 @@ use proc_macro::TokenStream;
 /// private modules between the item and the root of the crate); if the item is in the root of the
 /// crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31 and newer releases.
 ///
-/// The specified function will be called by the reset handler *after* RAM has been initialized. In
-/// the case of the `thumbv7em-none-eabihf` target the FPU will also be enabled before the function
-/// is called.
+/// The specified function will be called by the reset handler *after* RAM has been initialized.
+/// If present, the FPU will also be enabled before the function is called.
 ///
 /// The type of the specified function must be `[unsafe] fn() -> !` (never ending function)
 ///

From f572fdecd48a82b6b7b14f20b07746e673621394 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 7 Mar 2019 16:04:34 +0300
Subject: [PATCH 067/234] Add MSRV policy

---
 riscv-rt/.travis.yml | 3 +++
 riscv-rt/src/lib.rs  | 7 +++++++
 2 files changed, 10 insertions(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index e61c80a5..52f2755e 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -3,6 +3,7 @@ language: rust
 rust:
 - nightly
 - stable
+- 1.31.0 # MSRV
 
 env:
 - TARGET=x86_64-unknown-linux-gnu
@@ -15,6 +16,8 @@ matrix:
   exclude:
     - rust: stable
       env: TARGET=riscv64imac-unknown-none-elf
+    - rust: 1.31.0 # MSRV
+      env: TARGET=riscv64imac-unknown-none-elf
 
 
 before_install: set -e
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 1dc606af..1de3121b 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -1,5 +1,12 @@
 //! Minimal startup / runtime for RISC-V CPU's
 //!
+//! # Minimum Supported Rust Version (MSRV)
+//!
+//! This crate is guaranteed to compile on stable Rust 1.31 and up. It *might*
+//! compile with older versions but that may change in any new patch release.
+//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
+//! are not supported on stable yet.
+//!
 //! # Features
 //!
 //! This crate provides

From e85c1fb81c01faacf39aa4b2e9ea64e8650c1d90 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 7 Mar 2019 16:05:01 +0300
Subject: [PATCH 068/234] Bump version

---
 riscv-rt/Cargo.toml        | 2 +-
 riscv-rt/macros/Cargo.toml | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 084e9e85..3e642580 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.4.0"
+version = "0.5.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index 84762ff3..fb1e741c 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -28,4 +28,4 @@ version = "0.5.5"
 default-features = false
 
 [dev-dependencies]
-riscv-rt = { path = "..", version = "0.4.0" }
+riscv-rt = { path = "..", version = "0.5.0" }

From 8163823a83bc9eda50057c6b5fb59f342148e2b6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 15 Mar 2019 16:46:19 +0300
Subject: [PATCH 069/234] Produce a compilation error if riscv-rt appears more
 than once in the dependency graph

---
 riscv-rt/src/lib.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 1de3121b..d2274812 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -210,6 +210,10 @@ pub use macros::{entry, pre_init};
 
 use riscv::register::{mstatus, mtvec};
 
+#[export_name = "error: riscv-rt appears more than once in the dependency graph"]
+#[doc(hidden)]
+pub static __ONCE__: () = ();
+
 extern "C" {
     // Boundaries of the .bss section
     static mut _ebss: u32;

From 1c716aacb1cac7df12a5610d84df216bf54626c7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 29 Mar 2019 16:03:23 +0300
Subject: [PATCH 070/234] Update 'riscv' dependency

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 3e642580..ff4c1b4b 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.2"
-riscv = "0.5.0"
+riscv = "0.5.1"
 riscv-rt-macros = { path = "macros", version = "0.1.5" }
 
 [features]

From 373d773767545b0d251f833b6488fa6381e82693 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 29 Mar 2019 16:05:07 +0300
Subject: [PATCH 071/234] Initialize FPU when available

---
 riscv-rt/src/lib.rs | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index d2274812..b8d1e2b8 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -208,7 +208,7 @@ extern crate r0;
 
 pub use macros::{entry, pre_init};
 
-use riscv::register::{mstatus, mtvec};
+use riscv::register::{mstatus, mtvec, misa, fcsr};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -251,7 +251,15 @@ pub unsafe extern "C" fn start_rust() -> ! {
     r0::zero_bss(&mut _sbss, &mut _ebss);
     r0::init_data(&mut _sdata, &mut _edata, &_sidata);
 
-    // TODO: Enable FPU when available
+    // Initialize FPU when available
+    if let Some(isa) = misa::read() {
+        if isa.has_extension('F') || isa.has_extension('D') {
+            fcsr::clear_flags();
+            fcsr::set_rounding_mode(fcsr::RoundingMode::RoundToNearestEven);
+            mstatus::set_fs(mstatus::FS::Dirty);
+            // TODO: fill registers with zeros
+        }
+    }
 
     // Set mtvec to _start_trap
     mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);

From a4ac2f3e330da3a5f41520320ff2406d6c543b88 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 17:27:19 +0300
Subject: [PATCH 072/234] Fix linker script: produce correct program headers

---
 riscv-rt/link.x | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 3cccb3ca..5515ecf7 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -10,6 +10,13 @@ PROVIDE(trap_handler = default_trap_handler);
    then the function this points to will be called before the RAM is initialized. */
 PROVIDE(__pre_init = default_pre_init);
 
+PHDRS
+{
+    flash PT_LOAD;
+    ram_init PT_LOAD;
+    ram PT_NULL;
+}
+
 SECTIONS
 {
   PROVIDE(_stext = ORIGIN(FLASH));
@@ -25,22 +32,14 @@ SECTIONS
     KEEP(*(.trap.rust));
 
     *(.text .text.*);
-  } > FLASH
+  } > FLASH :flash
 
   .rodata ALIGN(4) :
   {
     *(.rodata .rodata.*);
-  } > FLASH
+  } > FLASH :flash
 
-  .bss :
-  {
-    _sbss = .;
-    *(.bss .bss.*);
-    . = ALIGN(4);
-    _ebss = .;
-  } > RAM
-
-  .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata))
+  .data ALIGN(4) :
   {
     _sidata = LOADADDR(.data);
     _sdata = .;
@@ -49,7 +48,15 @@ SECTIONS
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;
-  } > RAM
+  } > RAM AT > FLASH :ram_init
+
+  .bss :
+  {
+    _sbss = .;
+    *(.bss .bss.*);
+    . = ALIGN(4);
+    _ebss = .;
+  } > RAM :ram
 
   PROVIDE(_heap_size = 0);
 
@@ -60,7 +67,7 @@ SECTIONS
     . += _heap_size;
     . = ALIGN(4);
     _eheap = .;
-  } > RAM
+  } > RAM :ram
 
   /* fictitious region that represents the memory available for the stack */
   .stack (INFO) :
@@ -68,7 +75,7 @@ SECTIONS
     _estack = .;
     . = _stack_start;
     _sstack = .;
-  } > RAM
+  } > RAM :ram
 
   /* fake output .got section */
   /* Dynamic relocations are unsupported. This section is only used to detect

From 43b527c99b6cd22cef25eae6d5c3b6be0dfdcc0e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 18:25:21 +0300
Subject: [PATCH 073/234] Fix _stext redefinition

---
 riscv-rt/link.x | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 5515ecf7..a6e5b8fd 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -21,6 +21,11 @@ SECTIONS
 {
   PROVIDE(_stext = ORIGIN(FLASH));
 
+  .text.dummy ORIGIN(FLASH) :
+  {
+    /* This section is intended to make _stext address work */
+  } > FLASH :ram
+
   .text ALIGN(_stext,4) :
   {
     /* Put reset handler first in .text section so it ends up as the entry */

From fdd627df17f8131feaf988ee6930ff1a6d583b28 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 18:47:27 +0300
Subject: [PATCH 074/234] Use region aliases in the linker script

---
 riscv-rt/link.x | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index a6e5b8fd..db08f047 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -1,7 +1,4 @@
-/* NOTE: Adapted from cortex-m/link.x */
-INCLUDE memory.x
-
-PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
+PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
 
 PROVIDE(trap_handler = default_trap_handler);
 
@@ -12,19 +9,19 @@ PROVIDE(__pre_init = default_pre_init);
 
 PHDRS
 {
-    flash PT_LOAD;
-    ram_init PT_LOAD;
-    ram PT_NULL;
+    load PT_LOAD;
+    ram_load PT_LOAD;
+    virtual PT_NULL;
 }
 
 SECTIONS
 {
-  PROVIDE(_stext = ORIGIN(FLASH));
+  PROVIDE(_stext = ORIGIN(REGION_TEXT));
 
-  .text.dummy ORIGIN(FLASH) :
+  .text.dummy ORIGIN(REGION_TEXT) :
   {
     /* This section is intended to make _stext address work */
-  } > FLASH :ram
+  } > REGION_TEXT :virtual
 
   .text ALIGN(_stext,4) :
   {
@@ -37,12 +34,12 @@ SECTIONS
     KEEP(*(.trap.rust));
 
     *(.text .text.*);
-  } > FLASH :flash
+  } > REGION_TEXT :load
 
   .rodata ALIGN(4) :
   {
     *(.rodata .rodata.*);
-  } > FLASH :flash
+  } > REGION_RODATA :load
 
   .data ALIGN(4) :
   {
@@ -53,7 +50,7 @@ SECTIONS
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;
-  } > RAM AT > FLASH :ram_init
+  } > REGION_DATA AT > REGION_RODATA :ram_load
 
   .bss :
   {
@@ -61,7 +58,7 @@ SECTIONS
     *(.bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
-  } > RAM :ram
+  } > REGION_BSS :virtual
 
   PROVIDE(_heap_size = 0);
 
@@ -72,7 +69,7 @@ SECTIONS
     . += _heap_size;
     . = ALIGN(4);
     _eheap = .;
-  } > RAM :ram
+  } > REGION_HEAP :virtual
 
   /* fictitious region that represents the memory available for the stack */
   .stack (INFO) :
@@ -80,7 +77,7 @@ SECTIONS
     _estack = .;
     . = _stack_start;
     _sstack = .;
-  } > RAM :ram
+  } > REGION_STACK :virtual
 
   /* fake output .got section */
   /* Dynamic relocations are unsupported. This section is only used to detect

From ec35554f40e5c8231363dd4783eef6f7e3223650 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 18:51:22 +0300
Subject: [PATCH 075/234] Put provides in one place

---
 riscv-rt/link.x | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index db08f047..2db5c282 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -1,4 +1,6 @@
+PROVIDE(_stext = ORIGIN(REGION_TEXT));
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
+PROVIDE(_heap_size = 0);
 
 PROVIDE(trap_handler = default_trap_handler);
 
@@ -16,8 +18,6 @@ PHDRS
 
 SECTIONS
 {
-  PROVIDE(_stext = ORIGIN(REGION_TEXT));
-
   .text.dummy ORIGIN(REGION_TEXT) :
   {
     /* This section is intended to make _stext address work */
@@ -60,8 +60,6 @@ SECTIONS
     _ebss = .;
   } > REGION_BSS :virtual
 
-  PROVIDE(_heap_size = 0);
-
   /* fictitious region that represents the memory available for the heap */
   .heap (INFO) :
   {

From 9d64f83fa4b02e709c20b75dda814f36e7150d9b Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 18:59:11 +0300
Subject: [PATCH 076/234] Add more asserts

---
 riscv-rt/link.x | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 2db5c282..396e058f 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -93,10 +93,49 @@ SECTIONS
   }
 }
 
-/* Do not exceed this mark in the error messages below                | */
+/* Do not exceed this mark in the error messages above                                    | */
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
+
+ASSERT(_stext % 4 == 0, "
+ERROR(riscv-rt): `_stext` must be 4-byte aligned");
+
+ASSERT(_sdata % 4 == 0 && _edata % 4 == 0, "
+BUG(riscv-rt): .data is not 4-byte aligned");
+
+ASSERT(_sidata % 4 == 0, "
+BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
+
+ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
+BUG(riscv-rt): .bss is not 4-byte aligned");
+
+ASSERT(_sheap % 4 == 0, "
+BUG(riscv-rt): start of .heap is not 4-byte aligned");
+
+ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
+ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
+Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
+
 ASSERT(SIZEOF(.got) == 0, "
 .got section detected in the input files. Dynamic relocations are not
 supported. If you are linking to C code compiled using the `gcc` crate
 then modify your build script to compile the C code _without_ the
 -fPIC flag. See the documentation of the `gcc::Config.fpic` method for
 details.");
+
+/* Do not exceed this mark in the error messages above                                    | */

From b04261e0a9d11cc9a9355830764e9d6944f38dd7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 19:02:29 +0300
Subject: [PATCH 077/234] Allocate stacks for all the harts

---
 riscv-rt/link.x | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 396e058f..4c7b0ddf 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -1,5 +1,7 @@
 PROVIDE(_stext = ORIGIN(REGION_TEXT));
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
+PROVIDE(_max_hart_id = 0);
+PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
 PROVIDE(trap_handler = default_trap_handler);
@@ -131,6 +133,10 @@ ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
 ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
 Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
 
+ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
+ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
+Consider changing `_max_hart_id` or `_hart_stack_size`.");
+
 ASSERT(SIZEOF(.got) == 0, "
 .got section detected in the input files. Dynamic relocations are not
 supported. If you are linking to C code compiled using the `gcc` crate

From c4d4b7a1662ff2e3c6609d3eec885f86b863a108 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 19:16:17 +0300
Subject: [PATCH 078/234] Turn abort() into an infinite loop

---
 riscv-rt/asm.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 4402d777..4a9c3f25 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -83,4 +83,4 @@ _start_trap:
 .section .init
 .globl abort
 abort:
-    jal zero, _start
+    j abort

From b50b9ed7134af4e0736c8e082852177b6008c192 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Apr 2019 19:34:55 +0300
Subject: [PATCH 079/234] Set stack pointer for all the harts

---
 riscv-rt/asm.S | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 4a9c3f25..d85d0b44 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -18,8 +18,23 @@ _start:
     la gp, __global_pointer$
     .option pop
 
+    // Check hart id
+    csrr a2, mhartid
+    lui t0, %hi(_max_hart_id)
+    add t0, t0, %lo(_max_hart_id)
+    bgtu a2, t0, abort
+
+    // Allocate stacks
     la sp, _stack_start
+    lui t0, %hi(_hart_stack_size)
+    add t0, t0, %lo(_hart_stack_size)
+    mul t0, a2, t0
+    sub sp, sp, t0
+
+    // Park non-zero harts
+    bnez a2, abort
 
+    // Set frame pointer
     add s0, sp, zero
 
     jal zero, _start_rust

From c201a96cae0ed48fa2f62a45e0254b649f04a58e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 9 Apr 2019 18:51:58 +0300
Subject: [PATCH 080/234] Revert "Initialize FPU when available"

This reverts commit 373d773767545b0d251f833b6488fa6381e82693.
---
 riscv-rt/src/lib.rs | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index b8d1e2b8..d2274812 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -208,7 +208,7 @@ extern crate r0;
 
 pub use macros::{entry, pre_init};
 
-use riscv::register::{mstatus, mtvec, misa, fcsr};
+use riscv::register::{mstatus, mtvec};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -251,15 +251,7 @@ pub unsafe extern "C" fn start_rust() -> ! {
     r0::zero_bss(&mut _sbss, &mut _ebss);
     r0::init_data(&mut _sdata, &mut _edata, &_sidata);
 
-    // Initialize FPU when available
-    if let Some(isa) = misa::read() {
-        if isa.has_extension('F') || isa.has_extension('D') {
-            fcsr::clear_flags();
-            fcsr::set_rounding_mode(fcsr::RoundingMode::RoundToNearestEven);
-            mstatus::set_fs(mstatus::FS::Dirty);
-            // TODO: fill registers with zeros
-        }
-    }
+    // TODO: Enable FPU when available
 
     // Set mtvec to _start_trap
     mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);

From 73e56ebfabf56b815626f0917d9180ce42270a90 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 28 Apr 2019 20:25:26 +0200
Subject: [PATCH 081/234] Initialize GPR and MSR state

---
 riscv-rt/asm.S | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index d85d0b44..afcffaf1 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -13,6 +13,43 @@ _start:
     .cfi_startproc
     .cfi_undefined ra
 
+    csrw mideleg, 0
+    csrw medeleg, 0
+    csrw mie, 0
+    csrw mip, 0
+
+    li  x1, 0
+    li  x2, 0
+    li  x3, 0
+    li  x4, 0
+    li  x5, 0
+    li  x6, 0
+    li  x7, 0
+    li  x8, 0
+    li  x9, 0
+    li  x10,0
+    li  x11,0
+    li  x12,0
+    li  x13,0
+    li  x14,0
+    li  x15,0
+    li  x16,0
+    li  x17,0
+    li  x18,0
+    li  x19,0
+    li  x20,0
+    li  x21,0
+    li  x22,0
+    li  x23,0
+    li  x24,0
+    li  x25,0
+    li  x26,0
+    li  x27,0
+    li  x28,0
+    li  x29,0
+    li  x30,0
+    li  x31,0
+
     .option push
     .option norelax
     la gp, __global_pointer$

From 1f9677f3c73e2bc496c0ac4bf45d21e497023baa Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 28 Apr 2019 21:02:37 +0200
Subject: [PATCH 082/234] Set frame pointer right after stack allocation

---
 riscv-rt/asm.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index afcffaf1..99bd0bd9 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -68,12 +68,12 @@ _start:
     mul t0, a2, t0
     sub sp, sp, t0
 
-    // Park non-zero harts
-    bnez a2, abort
-
     // Set frame pointer
     add s0, sp, zero
 
+    // Park non-zero harts
+    bnez a2, abort
+
     jal zero, _start_rust
 
     .cfi_endproc

From 03f4eef93d6ef7ba9d6d72e9479edfa77dc51550 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 28 Apr 2019 21:05:04 +0200
Subject: [PATCH 083/234] Set trap handler in assembly

---
 riscv-rt/asm.S      | 4 ++++
 riscv-rt/src/lib.rs | 8 +-------
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 99bd0bd9..aa426e3b 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -71,6 +71,10 @@ _start:
     // Set frame pointer
     add s0, sp, zero
 
+    // Set trap handler
+    la t0, _start_trap
+    csrw mtvec, t0
+
     // Park non-zero harts
     bnez a2, abort
 
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index d2274812..0a1534a6 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -208,7 +208,7 @@ extern crate r0;
 
 pub use macros::{entry, pre_init};
 
-use riscv::register::{mstatus, mtvec};
+use riscv::register::mstatus;
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -225,9 +225,6 @@ extern "C" {
 
     // Initial values of the .data section (stored in Flash)
     static _sidata: u32;
-
-    // Address of _start_trap
-    static _start_trap: u32;
 }
 
 
@@ -253,9 +250,6 @@ pub unsafe extern "C" fn start_rust() -> ! {
 
     // TODO: Enable FPU when available
 
-    // Set mtvec to _start_trap
-    mtvec::write(&_start_trap as *const _ as usize, mtvec::TrapMode::Direct);
-
     main();
 }
 

From 84042d706ad1064db3a68b0c4037a7b8c017b3cf Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 20 May 2019 11:16:42 +0300
Subject: [PATCH 084/234] Do not set mideleg and medeleg (not supported on
 FE310)

---
 riscv-rt/asm.S | 2 --
 1 file changed, 2 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index aa426e3b..9a96381a 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -13,8 +13,6 @@ _start:
     .cfi_startproc
     .cfi_undefined ra
 
-    csrw mideleg, 0
-    csrw medeleg, 0
     csrw mie, 0
     csrw mip, 0
 

From 5c1bbc64e4349ea3fe71e9d74a57122861be062e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 May 2019 22:22:38 +0300
Subject: [PATCH 085/234] Introduce _mp_hook

---
 riscv-rt/Cargo.toml |  2 +-
 riscv-rt/asm.S      |  3 ---
 riscv-rt/link.x     |  9 +++++++++
 riscv-rt/src/lib.rs | 22 +++++++++++++++++++---
 4 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index ff4c1b4b..9ba0610f 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "0.2.2"
-riscv = "0.5.1"
+riscv = "0.5.3"
 riscv-rt-macros = { path = "macros", version = "0.1.5" }
 
 [features]
diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 9a96381a..471c3ade 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -73,9 +73,6 @@ _start:
     la t0, _start_trap
     csrw mtvec, t0
 
-    // Park non-zero harts
-    bnez a2, abort
-
     jal zero, _start_rust
 
     .cfi_endproc
diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 4c7b0ddf..8a90af39 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -11,6 +11,15 @@ PROVIDE(trap_handler = default_trap_handler);
    then the function this points to will be called before the RAM is initialized. */
 PROVIDE(__pre_init = default_pre_init);
 
+/* # Multi-processing hook function
+   fn _mp_hook() -> bool;
+
+   This function is called from all the harts and should return true only for one hart,
+   which will perform memory initialization. For other harts it should return false
+   and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
+*/
+PROVIDE(_mp_hook = default_mp_hook);
+
 PHDRS
 {
     load PT_LOAD;
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 0a1534a6..0f8cbf4c 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -241,12 +241,16 @@ pub unsafe extern "C" fn start_rust() -> ! {
 
         // This symbol will be provided by the user via `#[pre_init]`
         fn __pre_init();
+
+        fn _mp_hook() -> bool;
     }
 
-    __pre_init();
+    if _mp_hook() {
+        __pre_init();
 
-    r0::zero_bss(&mut _sbss, &mut _ebss);
-    r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+        r0::zero_bss(&mut _sbss, &mut _ebss);
+        r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+    }
 
     // TODO: Enable FPU when available
 
@@ -284,3 +288,15 @@ pub fn default_trap_handler() {}
 #[doc(hidden)]
 #[no_mangle]
 pub unsafe extern "Rust" fn default_pre_init() {}
+
+#[doc(hidden)]
+#[no_mangle]
+pub extern "Rust" fn default_mp_hook() -> bool {
+    use riscv::register::mhartid;
+    match mhartid::read() {
+        0 => true,
+        _ => loop {
+            unsafe { riscv::asm::wfi() }
+        },
+    }
+}

From 5d8f8c3ba13aa6ba0b20cb42ebe9d7d872bca7f3 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 May 2019 22:22:58 +0300
Subject: [PATCH 086/234] Regenerate binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1490 -> 1954 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1490 -> 1954 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2114 -> 2794 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2114 -> 2794 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index e301d87339624d8fd01ee4ddee127467fd276a01..4fa389e0ac1a52625e0003f61d67d5242bb0b456 100644
GIT binary patch
literal 1954
zcma)6&rcIU6n@iU)hdcVAz(~F{H<$+M$s5jiWI>LO2UtLaM_kBRiL=L5+z1696T5g
zMh{;78}#5&V~8=v7(<LP#(4H7;=zkXzqhjk+a^X|^5%WtH*ep}&g|RzW0sv8ZH*p?
zm0CPN6%LNESfWWM3`dD544=?$I<95AWMzvO6)|1gnk2FdPHt+y?HWb3-rrU^lt_5x
z4<2q&AT}Jm*^x;LA+U%tLEmYK5xuM+k0-q8U9^TO$vK^j!xJ(o+GLwZ$&_f9?c%sR
zE;?j~NXxY7l%3*)JR!Pdm*|$=;-ow&GBP7h$y1_7_K05D`vA+_mx7!f$!||Wz%wDr
zeR&?LhQ0wi(%R$DK&V-qNj6sqdf?|dcl+YS`KLd`!y}g?&o)1=o!$DvemV7O`t^-B
zd)^vzP45o9Kl-8dW9n1-^Vj*`zh;v6QVs2o+EYDqJ=xxc-cbL&{)T}^1F6Be!R*k&
zP`%|)EWS~n!E_&q>q693hL-bLRKd6Sb2_x`0`d-?#8$v%_Ed9Ip=mO1j`Lvgki($!
z{}#g~r_EQ6R}5I#`v{hVFjbU2q4@2^6kJ%q!W8lH(~FwQKUc=51AGwzglR>Pf=B6K
zK&irhA|;%tri^a~*ZbrAy=C()WxT6|N2tGq6Io@Pj7&U6rg>qkn6<{t$zox`&D)J+
zj$2pFQ8bNN7zy-E?vme1Y7TA1N?|%*(p7$k*;kyBZZkcBh|jZnjoL^zLXCe+eZaMA
zmCm?XK^j1;^L55r=X<DLr;-?JJquj3Qt6Dfejd1Xz0w(L{UUIkuQS#<-)r>-3^2x8
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delta 630
zcmZ8fJxjw-6uqxWW3{a&D5MmTV#P+MYTT@|ASentImGH9_(3I2L2yuiftELPDF~hX
zAr1~s{(&wIj{OD2d){ke^})$I=iZb1?tMvb<}>?z>;%oI9!5bF)^DhO+6bfem2dd#
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zx+LGM<)c^DOB{e5?Z@_UEBx<_5(m*N03W^rCggu4S>NnAl;;!W!UtDANaFf%$RC8-
BNiYBa

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index e301d87339624d8fd01ee4ddee127467fd276a01..4fa389e0ac1a52625e0003f61d67d5242bb0b456 100644
GIT binary patch
literal 1954
zcma)6&rcIU6n@iU)hdcVAz(~F{H<$+M$s5jiWI>LO2UtLaM_kBRiL=L5+z1696T5g
zMh{;78}#5&V~8=v7(<LP#(4H7;=zkXzqhjk+a^X|^5%WtH*ep}&g|RzW0sv8ZH*p?
zm0CPN6%LNESfWWM3`dD544=?$I<95AWMzvO6)|1gnk2FdPHt+y?HWb3-rrU^lt_5x
z4<2q&AT}Jm*^x;LA+U%tLEmYK5xuM+k0-q8U9^TO$vK^j!xJ(o+GLwZ$&_f9?c%sR
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delta 630
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zTYi~$GE952lYSEOvSO82YAK=<PEIj!GJuLT2EL8Oz}lBhtFqc<H?nXe6T7#W!_8^6
zx+LGM<)c^DOB{e5?Z@_UEBx<_5(m*N03W^rCggu4S>NnAl;;!W!UtDANaFf%$RC8-
BNiYBa

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index b35b6b2d7719562a0df42e884858d475be8d867b..b9289a01bc822013c03e0a67c2f2a11f191c935c 100644
GIT binary patch
literal 2794
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z@!JvWda#2tGoe>O8~U-GQYfq~gkT@@LJ#ap5P<F1raikpTSqp6(Qhq=wJG<w@6FV3
zg#L227lwYlayqO9S`q&P(z?=}rO%08=TMi>EQ9MrpW^9Ptv5$^G)!8((RZWs^}g}D
zF!sOd|3y#6TAlg^9r_zMI!Ty+5wE!5kC{?;0qs|6d+|xie>)llD6>_@od0(?kd*%w
zZzh$8^3xib`3I1rcbe<6ffMC$Om8Y)aYY14`8#++46=~&Q>=<tbsa(u*KUqw@5~_Q
z|LPqR19SdKwUcszg&jPxmB_W@W9Fwj&)hpm!Ou+k<Y>*zPv<`=ev;>3)nW;n@oxd+
Co#Sx;

delta 634
zcmaDQdPrbGv|xO3Nn%k+d`VGa0YhR^eo@K993y5!OOuHU4NW3g7{GuLNIHO74h*~u
zJPgx;0+SmV8N`9KFe4*_F$*I@{)hYj@;}V~H@S?lW^x0&%w#*J8b*o9icG?j&oRkN
zUc@B9$N}c*F^e$DO^#;vovg$pBx?vXR)B#GY&bGu3layZ=kx=sU}2D$tjwZO4|HvE
zHpI;gP^TA_7MH--U~eFKDIP2d_7}404B|i@50VJfqYM&2F%Beg7#pOX7l`X&axe*F
zm;jW9845Cp6G;vxj;>w=szwk<^C77R=?4LjI5(IDCiobXpd65dz~uF8OC}ewTL1%`
zfAT8!2aGb4yE)7SA22}_9e}FkntYi<pD|`KGpD`a0%nLH%mS{-!JPU`D;OrXaN6na
zfJ%D6Gy-XmPhq}=X#yn(CQ$5%-hisy01^TMkXyMYhjZz0K-~~Bxtq(JlK~pQfs?s8
F<N@T9R=fZJ

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index b35b6b2d7719562a0df42e884858d475be8d867b..b9289a01bc822013c03e0a67c2f2a11f191c935c 100644
GIT binary patch
literal 2794
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z84H1$1By@%5gfSk8{m**5Q?HGLI_z1A%r+{<B<bg5LC@nliv1B4y2{&`s(YirmCkO
z)4A94t5f^hzRfnboaV+@@3YxLUI~u20YC<yS@pO<==mXdl?L{)<A%OB2jJI(>ikYW
zv>S20v@AV^LiGB4Pd*0OqiyH=%Oy()OcFN%|G>YVVgYWps&N1(f)1>Lb_jlOa`+Ua
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zf{H(q!Y>*;xf%E{fhC>}L37)MZb!nrsKSnBY2<B4;lGIZ7BJ_#BSrsx3O^L_%fHWf
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z@!JvWda#2tGoe>O8~U-GQYfq~gkT@@LJ#ap5P<F1raikpTSqp6(Qhq=wJG<w@6FV3
zg#L227lwYlayqO9S`q&P(z?=}rO%08=TMi>EQ9MrpW^9Ptv5$^G)!8((RZWs^}g}D
zF!sOd|3y#6TAlg^9r_zMI!Ty+5wE!5kC{?;0qs|6d+|xie>)llD6>_@od0(?kd*%w
zZzh$8^3xib`3I1rcbe<6ffMC$Om8Y)aYY14`8#++46=~&Q>=<tbsa(u*KUqw@5~_Q
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Co#Sx;

delta 634
zcmaDQdPrbGv|xO3Nn%k+d`VGa0YhR^eo@K993y5!OOuHU4NW3g7{GuLNIHO74h*~u
zJPgx;0+SmV8N`9KFe4*_F$*I@{)hYj@;}V~H@S?lW^x0&%w#*J8b*o9icG?j&oRkN
zUc@B9$N}c*F^e$DO^#;vovg$pBx?vXR)B#GY&bGu3layZ=kx=sU}2D$tjwZO4|HvE
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zm;jW9845Cp6G;vxj;>w=szwk<^C77R=?4LjI5(IDCiobXpd65dz~uF8OC}ewTL1%`
zfAT8!2aGb4yE)7SA22}_9e}FkntYi<pD|`KGpD`a0%nLH%mS{-!JPU`D;OrXaN6na
zfJ%D6Gy-XmPhq}=X#yn(CQ$5%-hisy01^TMkXyMYhjZz0K-~~Bxtq(JlK~pQfs?s8
F<N@T9R=fZJ


From 6d144111f3ebc0d44bd5c0bb6ababacda1079fc6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:26:46 +0300
Subject: [PATCH 087/234] Update documentation

---
 riscv-rt/link.x     |   4 +-
 riscv-rt/src/lib.rs | 107 +++++++++++++++++++++++++++++++++-----------
 2 files changed, 82 insertions(+), 29 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 8a90af39..65da46ad 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -14,8 +14,8 @@ PROVIDE(__pre_init = default_pre_init);
 /* # Multi-processing hook function
    fn _mp_hook() -> bool;
 
-   This function is called from all the harts and should return true only for one hart,
-   which will perform memory initialization. For other harts it should return false
+   This function is called from all the harts and must return true only for one hart,
+   which will perform memory initialization. For other harts it must return false
    and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
 */
 PROVIDE(_mp_hook = default_mp_hook);
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 0f8cbf4c..70a35015 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -13,14 +13,14 @@
 //!
 //! - Before main initialization of the `.bss` and `.data` sections.
 //!
-//! - Before main initialization of the FPU (for targets that have a FPU).
-//!
 //! - `#[entry]` to declare the entry point of the program
 //! - `#[pre_init]` to run code *before* `static` variables are initialized
 //!
 //! - A linker script that encodes the memory layout of a generic RISC-V
 //!   microcontroller. This linker script is missing some information that must
-//!   be supplied through a `memory.x` file (see example below).
+//!   be supplied through a `memory.x` file (see example below). This file
+//!   must be supplied using rustflags and listed *before* `link.x`. Arbitrary
+//!   filename can be use instead of `memory.x`.
 //!
 //! - A `_sheap` symbol at whose address you can locate a heap.
 //!
@@ -37,11 +37,17 @@
 //! $ edit memory.x && cat $_
 //! MEMORY
 //! {
-//!   /* NOTE K = KiBi = 1024 bytes */
-//!   FLASH : ORIGIN = 0x20000000, LENGTH = 16M
 //!   RAM : ORIGIN = 0x80000000, LENGTH = 16K
+//!   FLASH : ORIGIN = 0x20000000, LENGTH = 16M
 //! }
 //!
+//! REGION_ALIAS("REGION_TEXT", FLASH);
+//! REGION_ALIAS("REGION_RODATA", FLASH);
+//! REGION_ALIAS("REGION_DATA", RAM);
+//! REGION_ALIAS("REGION_BSS", RAM);
+//! REGION_ALIAS("REGION_HEAP", RAM);
+//! REGION_ALIAS("REGION_STACK", RAM);
+//!
 //! $ edit src/main.rs && cat $_
 //! ```
 //!
@@ -66,7 +72,8 @@
 //! $ mkdir .cargo && edit .cargo/config && cat $_
 //! [target.riscv32imac-unknown-none-elf]
 //! rustflags = [
-//!   "-C", "link-arg=-Tlink.x"
+//!   "-C", "link-arg=-Tmemory.x",
+//!   "-C", "link-arg=-Tlink.x",
 //! ]
 //!
 //! [build]
@@ -124,14 +131,27 @@
 //!
 //! The main information that this file must provide is the memory layout of
 //! the device in the form of the `MEMORY` command. The command is documented
-//! [here][2], but at a minimum you'll want to create two memory regions: one
-//! for Flash memory and another for RAM.
+//! [here][2], but at a minimum you'll want to create at least one memory region.
 //!
 //! [2]: https://sourceware.org/binutils/docs/ld/MEMORY.html
 //!
-//! The program instructions (the `.text` section) will be stored in the memory
-//! region named FLASH, and the program `static` variables (the sections `.bss`
-//! and `.data`) will be allocated in the memory region named RAM.
+//! To support different relocation models (RAM-only, FLASH+RAM) multiple regions are used:
+//!
+//! - `REGION_TEXT` - for `.init`, `.trap` and `.text` sections
+//! - `REGION_RODATA` - for `.rodata` section and storing initial values for `.data` section
+//! - `REGION_DATA` - for `.data` section
+//! - `REGION_BSS` - for `.bss` section
+//! - `REGION_HEAP` - for the heap area
+//! - `REGION_STACK` - for hart stacks
+//!
+//! Specific aliases for these regions must be defined in `memory.x` file (see example below).
+//!
+//! ### `_stext`
+//!
+//! This symbol provides the loading address of `.text` section. This value can be changed
+//! to override the loading address of the firmware (for example, in case of bootloader present).
+//!
+//! If omitted this symbol value will default to `ORIGIN(REGION_TEXT)`.
 //!
 //! ### `_stack_start`
 //!
@@ -140,25 +160,49 @@
 //! valid RAM address plus one (this *is* an invalid address but the processor
 //! will decrement the stack pointer *before* using its value as an address).
 //!
-//! If omitted this symbol value will default to `ORIGIN(RAM) + LENGTH(RAM)`.
+//! In case of multiple harts present, this address defines the initial stack pointer for hart 0.
+//! Stack pointer for hart `N` is calculated as  `_stack_start - N * _hart_stack_size`.
+//!
+//! If omitted this symbol value will default to `ORIGIN(REGION_STACK) + LENGTH(REGION_STACK)`.
 //!
 //! #### Example
 //!
 //! Allocating the call stack on a different RAM region.
 //!
-//! ```
+//! ``` text
 //! MEMORY
 //! {
-//!   /* call stack will go here */
-//!   CCRAM : ORIGIN = 0x10000000, LENGTH = 8K
-//!   FLASH : ORIGIN = 0x08000000, LENGTH = 256K
-//!   /* static variables will go here */
-//!   RAM : ORIGIN = 0x20000000, LENGTH = 40K
+//!   L2_LIM : ORIGIN = 0x08000000, LENGTH = 1M
+//!   RAM : ORIGIN = 0x80000000, LENGTH = 16K
+//!   FLASH : ORIGIN = 0x20000000, LENGTH = 16M
 //! }
 //!
-//! _stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
+//! REGION_ALIAS("REGION_TEXT", FLASH);
+//! REGION_ALIAS("REGION_RODATA", FLASH);
+//! REGION_ALIAS("REGION_DATA", RAM);
+//! REGION_ALIAS("REGION_BSS", RAM);
+//! REGION_ALIAS("REGION_HEAP", RAM);
+//! REGION_ALIAS("REGION_STACK", L2_LIM);
+//!
+//! _stack_start = ORIGIN(L2_LIM) + LENGTH(L2_LIM);
 //! ```
 //!
+//! ### `_max_hart_id`
+//!
+//! This symbol defines the maximum hart id suppoted. All harts with id
+//! greater than `_max_hart_id` will be redirected to `abort()`.
+//!
+//! This symbol is supposed to be redefined in platform support crates for
+//! multi-core targets.
+//!
+//! If omitted this symbol value will default to 0 (single core).
+//!
+//! ### `_hart_stack_size`
+//!
+//! This symbol defines stack area size for *one* hart.
+//!
+//! If omitted this symbol value will default to 2K.
+//!
 //! ### `_heap_size`
 //!
 //! This symbol provides the size of a heap region. The default value is 0. You can set `_heap_size`
@@ -172,7 +216,7 @@
 //!
 //! #### Example
 //!
-//! ```
+//! ``` no_run
 //! extern crate some_allocator;
 //!
 //! extern "C" {
@@ -189,13 +233,22 @@
 //! }
 //! ```
 //!
-//! ## `pre_init!`
+//! ### `_mp_hook`
+//!
+//! This function is called from all the harts and must return true only for one hart,
+//! which will perform memory initialization. For other harts it must return false
+//! and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
 //!
-//! A user-defined function can be run at the start of the reset handler, before RAM is
-//! initialized. The macro `pre_init!` can be called to set the function to be run. The function is
-//! intended to perform actions that cannot wait the time it takes for RAM to be initialized, such
-//! as disabling a watchdog. As the function is called before RAM is initialized, any access of
-//! static variables will result in undefined behavior.
+//! This function can be redefined in the following way:
+//!
+//! ``` no_run
+//! #[export_name = "_mp_hook"]
+//! pub extern "Rust" fn mp_hook() -> bool {
+//!    // ...
+//! }
+//! ```
+//!
+//! Default implementation of this function wakes hart 0 and busy-loops all the other harts.
 
 // NOTE: Adapted from cortex-m/src/lib.rs
 #![no_std]
@@ -281,7 +334,7 @@ pub extern "C" fn start_trap_rust() {
 }
 
 
-/// Default Trap Handler
+#[doc(hidden)]
 #[no_mangle]
 pub fn default_trap_handler() {}
 

From 0049fd0ed0b74d8c81506cc3eeaabf2534b2e237 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:35:57 +0300
Subject: [PATCH 088/234] Add examples

---
 riscv-rt/Cargo.toml             |  5 +++
 riscv-rt/examples/empty.rs      | 13 ++++++++
 riscv-rt/examples/multi_core.rs | 56 +++++++++++++++++++++++++++++++++
 3 files changed, 74 insertions(+)
 create mode 100644 riscv-rt/examples/empty.rs
 create mode 100644 riscv-rt/examples/multi_core.rs

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 9ba0610f..d5495535 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -15,3 +15,8 @@ riscv-rt-macros = { path = "macros", version = "0.1.5" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]
+
+[dev-dependencies]
+riscv = "0.5.3"
+riscv-rt = "0.5.0"
+panic-halt = "0.2.0"
diff --git a/riscv-rt/examples/empty.rs b/riscv-rt/examples/empty.rs
new file mode 100644
index 00000000..5699d6f4
--- /dev/null
+++ b/riscv-rt/examples/empty.rs
@@ -0,0 +1,13 @@
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+extern crate riscv_rt;
+
+use riscv_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    // do something here
+    loop { }
+}
diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs
new file mode 100644
index 00000000..f9092407
--- /dev/null
+++ b/riscv-rt/examples/multi_core.rs
@@ -0,0 +1,56 @@
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+extern crate riscv;
+extern crate riscv_rt;
+
+use riscv::register::{mie, mip, mhartid};
+use riscv::asm::wfi;
+use riscv_rt::entry;
+
+#[export_name = "_mp_hook"]
+pub extern "Rust" fn user_mp_hook() -> bool {
+    let hartid = mhartid::read();
+    if hartid == 0 {
+        true
+    } else {
+        let addr = 0x02000000 + hartid * 4;
+        unsafe {
+            // Clear IPI
+            (addr as *mut u32).write_volatile(0);
+
+            // Start listening for software interrupts
+            mie::set_msoft();
+
+            loop {
+                wfi();
+                if mip::read().msoft() {
+                    break;
+                }
+            }
+
+            // Start listening for software interrupts
+            mie::clear_msoft();
+
+            // Clear IPI
+            (addr as *mut u32).write_volatile(0);
+        }
+        false
+    }
+}
+
+#[entry]
+fn main() -> ! {
+    let hartid = mhartid::read();
+
+    if hartid == 0 {
+        // Waking hart 1...
+        let addr = 0x02000004;
+        unsafe {
+            (addr as *mut u32).write_volatile(1);
+        }
+    }
+
+    loop { }
+}

From cf8c9f286c6f46952abaf3a37a56e63c3052f0b6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:40:23 +0300
Subject: [PATCH 089/234] Check examples in CI

---
 riscv-rt/ci/script.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index e2497ee9..93d64a9a 100644
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -2,6 +2,7 @@ set -euxo pipefail
 
 main() {
     cargo check --target $TARGET
+    cargo check --target $TARGET --examples
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
         cargo check --target $TARGET --features 'inline-asm'

From 984a63d8f55c8932842ac40943e4f81ee329c88d Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:45:49 +0300
Subject: [PATCH 090/234] [macros] Remove riscv-rt dependency

---
 riscv-rt/macros/Cargo.toml | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index fb1e741c..859f8db6 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -26,6 +26,3 @@ version = "0.15.13"
 [dependencies.rand]
 version = "0.5.5"
 default-features = false
-
-[dev-dependencies]
-riscv-rt = { path = "..", version = "0.5.0" }

From f433e3d248074a30386eb2bd72df7f2b220f875f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:46:48 +0300
Subject: [PATCH 091/234] [macros] Bump version (0.1.6)

---
 riscv-rt/macros/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index 859f8db6..7adbab68 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -10,7 +10,7 @@ keywords = ["riscv", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "riscv-rt-macros"
 repository = "https://github.com/rust-embedded/riscv-rt"
-version = "0.1.5"
+version = "0.1.6"
 
 [lib]
 proc-macro = true

From 968594090eeba48fe5efbb23303a06a8341bdcfe Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:48:17 +0300
Subject: [PATCH 092/234] Update riscv-rt-macros dependency

---
 riscv-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index d5495535..0dbfe5b9 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,7 +11,7 @@ license = "ISC"
 [dependencies]
 r0 = "0.2.2"
 riscv = "0.5.3"
-riscv-rt-macros = { path = "macros", version = "0.1.5" }
+riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]

From 15fe9928bfe84258afe52186d7624aba1e731cb7 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 23 May 2019 00:48:32 +0300
Subject: [PATCH 093/234] Bump version (0.6.0)

---
 riscv-rt/Cargo.toml | 4 ++--
 riscv-rt/src/lib.rs | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 0dbfe5b9..e9b26cdf 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.5.0"
+version = "0.6.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
@@ -18,5 +18,5 @@ inline-asm = ["riscv/inline-asm"]
 
 [dev-dependencies]
 riscv = "0.5.3"
-riscv-rt = "0.5.0"
+riscv-rt = "0.6.0"
 panic-halt = "0.2.0"
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 70a35015..17dfc36f 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -30,7 +30,7 @@
 //! $ # add this crate as a dependency
 //! $ edit Cargo.toml && cat $_
 //! [dependencies]
-//! riscv-rt = "0.4.0"
+//! riscv-rt = "0.6.0"
 //! panic-halt = "0.2.0"
 //!
 //! $ # memory layout of the device

From 73f1a1ebe796d42ebc79ae228630feefebf60bae Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 25 May 2019 16:51:10 +0300
Subject: [PATCH 094/234] Rename RISCV to RISC-V

---
 riscv-rt/CODE_OF_CONDUCT.md | 4 ++--
 riscv-rt/README.md          | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-rt/CODE_OF_CONDUCT.md b/riscv-rt/CODE_OF_CONDUCT.md
index a22c4f68..fccadf9a 100644
--- a/riscv-rt/CODE_OF_CONDUCT.md
+++ b/riscv-rt/CODE_OF_CONDUCT.md
@@ -2,7 +2,7 @@
 
 ## Conduct
 
-**Contact**: [RISCV team](https://github.com/rust-embedded/wg#the-riscv-team)
+**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team)
 
 * We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic.
 * On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all.
@@ -10,7 +10,7 @@
 * Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer.
 * Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works.
 * We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups.
-* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISCV team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
+* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
 * Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome.
 
 ## Moderation
diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index d98b9822..9d4e4715 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -4,15 +4,15 @@
 
 # `riscv-rt`
 
-> Minimal runtime / startup for RISCV CPU's.
+> Minimal runtime / startup for RISC-V CPU's.
 
-This project is developed and maintained by the [RISCV team][team].
+This project is developed and maintained by the [RISC-V team][team].
 
 ## [Documentation](https://docs.rs/crate/riscv-rt)
 
 ## License
 
-Copyright 2018 [RISCV team][team]
+Copyright 2018 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -29,7 +29,7 @@ THIS SOFTWARE.
 ## Code of Conduct
 
 Contribution to this crate is organized under the terms of the [Rust Code of
-Conduct][CoC], the maintainer of this crate, the [RISCV team][team], promises
+Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [CoC]: CODE_OF_CONDUCT.md

From e33637548f095f95c0d6298051b76be89c3e3b09 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 1 Jul 2019 16:41:08 +0300
Subject: [PATCH 095/234] Fix build

---
 riscv-rt/Cargo.toml   | 1 -
 riscv-rt/ci/script.sh | 4 +++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index e9b26cdf..2ee24a58 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -18,5 +18,4 @@ inline-asm = ["riscv/inline-asm"]
 
 [dev-dependencies]
 riscv = "0.5.3"
-riscv-rt = "0.6.0"
 panic-halt = "0.2.0"
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index 93d64a9a..fea3bb89 100644
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -2,7 +2,9 @@ set -euxo pipefail
 
 main() {
     cargo check --target $TARGET
-    cargo check --target $TARGET --examples
+    if [[ $TARGET == riscv* ]]; then
+        cargo check --target $TARGET --examples
+    fi
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
         cargo check --target $TARGET --features 'inline-asm'

From eb00f87c1604b18bf3c4acac69eeecb79922cf66 Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@gmail.com>
Date: Thu, 18 Jul 2019 18:09:26 +0000
Subject: [PATCH 096/234] Add .sbss section to linker script

Rust nightly has started generating this section for RISC-V executables,
place it at the start of the bss area.
---
 riscv-rt/link.x | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 65da46ad..6f8926e8 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -66,7 +66,7 @@ SECTIONS
   .bss :
   {
     _sbss = .;
-    *(.bss .bss.*);
+    *(.sbss .sbss.* .bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
   } > REGION_BSS :virtual

From 98f7b1a72c6c0cf469eedd2890c861663611f57f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 16:30:01 +0300
Subject: [PATCH 097/234] Use ALIGN attributes properly

---
 riscv-rt/link.x | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 6f8926e8..3844de07 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -34,7 +34,7 @@ SECTIONS
     /* This section is intended to make _stext address work */
   } > REGION_TEXT :virtual
 
-  .text ALIGN(_stext,4) :
+  .text _stext :
   {
     /* Put reset handler first in .text section so it ends up as the entry */
     /* point of the program. */
@@ -47,12 +47,12 @@ SECTIONS
     *(.text .text.*);
   } > REGION_TEXT :load
 
-  .rodata ALIGN(4) :
+  .rodata : ALIGN(4)
   {
     *(.rodata .rodata.*);
   } > REGION_RODATA :load
 
-  .data ALIGN(4) :
+  .data : ALIGN(4)
   {
     _sidata = LOADADDR(.data);
     _sdata = .;

From 84079735254db501bbf6d3af99957cd6d958b602 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 16:31:03 +0300
Subject: [PATCH 098/234] Add .sdata section to linker script

---
 riscv-rt/link.x | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 3844de07..0e54e7ba 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -58,6 +58,7 @@ SECTIONS
     _sdata = .;
     /* Must be called __global_pointer$ for linker relaxations to work. */
     PROVIDE(__global_pointer$ = . + 0x800);
+    *(.sdata .sdata.*);
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;

From 03a3639de8d62d05aeec423362a5f92683cae0ef Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 16:32:25 +0300
Subject: [PATCH 099/234] Fix .data alignment issue

---
 riscv-rt/link.x | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 0e54e7ba..485a9077 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -50,6 +50,11 @@ SECTIONS
   .rodata : ALIGN(4)
   {
     *(.rodata .rodata.*);
+
+    /* 4-byte align the end (VMA) of this section.
+       This is required by LLD to ensure the LMA of the following .data
+       section will have the correct alignment. */
+    . = ALIGN(4);
   } > REGION_RODATA :load
 
   .data : ALIGN(4)

From 8f3ff84937f9be84a9df51529ef97d99c8fe4fe6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 16:33:36 +0300
Subject: [PATCH 100/234] Fix section flags

---
 riscv-rt/link.x | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 485a9077..8f874778 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -69,30 +69,30 @@ SECTIONS
     _edata = .;
   } > REGION_DATA AT > REGION_RODATA :ram_load
 
-  .bss :
+  .bss (NOLOAD) :
   {
     _sbss = .;
     *(.sbss .sbss.* .bss .bss.*);
     . = ALIGN(4);
     _ebss = .;
-  } > REGION_BSS :virtual
+  } > REGION_BSS
 
   /* fictitious region that represents the memory available for the heap */
-  .heap (INFO) :
+  .heap (NOLOAD) :
   {
     _sheap = .;
     . += _heap_size;
     . = ALIGN(4);
     _eheap = .;
-  } > REGION_HEAP :virtual
+  } > REGION_HEAP
 
   /* fictitious region that represents the memory available for the stack */
-  .stack (INFO) :
+  .stack (NOLOAD) :
   {
     _estack = .;
     . = _stack_start;
     _sstack = .;
-  } > REGION_STACK :virtual
+  } > REGION_STACK
 
   /* fake output .got section */
   /* Dynamic relocations are unsupported. This section is only used to detect

From 44c86e244df0948b483c3bcc4470d75ba76cd596 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 16:34:37 +0300
Subject: [PATCH 101/234] Fix _stext override issue

---
 riscv-rt/link.x | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 8f874778..529bc75e 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -20,19 +20,13 @@ PROVIDE(__pre_init = default_pre_init);
 */
 PROVIDE(_mp_hook = default_mp_hook);
 
-PHDRS
-{
-    load PT_LOAD;
-    ram_load PT_LOAD;
-    virtual PT_NULL;
-}
-
 SECTIONS
 {
-  .text.dummy ORIGIN(REGION_TEXT) :
+  .text.dummy (NOLOAD) :
   {
     /* This section is intended to make _stext address work */
-  } > REGION_TEXT :virtual
+    . = _stext;
+  } > REGION_TEXT
 
   .text _stext :
   {
@@ -45,7 +39,7 @@ SECTIONS
     KEEP(*(.trap.rust));
 
     *(.text .text.*);
-  } > REGION_TEXT :load
+  } > REGION_TEXT
 
   .rodata : ALIGN(4)
   {
@@ -55,7 +49,7 @@ SECTIONS
        This is required by LLD to ensure the LMA of the following .data
        section will have the correct alignment. */
     . = ALIGN(4);
-  } > REGION_RODATA :load
+  } > REGION_RODATA
 
   .data : ALIGN(4)
   {
@@ -67,7 +61,7 @@ SECTIONS
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;
-  } > REGION_DATA AT > REGION_RODATA :ram_load
+  } > REGION_DATA AT > REGION_RODATA
 
   .bss (NOLOAD) :
   {

From 1839103f1c5bbff1a0ea404f9bc5bd93f1428f8d Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 17:14:14 +0300
Subject: [PATCH 102/234] Add support for 64-bit registers in _start_trap

---
 riscv-rt/asm.S | 74 ++++++++++++++++++++++++++------------------------
 riscv-rt/asm.h | 15 ++++++++++
 2 files changed, 53 insertions(+), 36 deletions(-)
 create mode 100644 riscv-rt/asm.h

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 471c3ade..61f3bd6e 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -1,3 +1,5 @@
+#include "asm.h"
+
 /*
     Entry point of all programs (_start).
 
@@ -88,45 +90,45 @@ _start:
 .global _start_trap
 
 _start_trap:
-    addi sp, sp, -16*4
-
-    sw ra, 0*4(sp)
-    sw t0, 1*4(sp)
-    sw t1, 2*4(sp)
-    sw t2, 3*4(sp)
-    sw t3, 4*4(sp)
-    sw t4, 5*4(sp)
-    sw t5, 6*4(sp)
-    sw t6, 7*4(sp)
-    sw a0, 8*4(sp)
-    sw a1, 9*4(sp)
-    sw a2, 10*4(sp)
-    sw a3, 11*4(sp)
-    sw a4, 12*4(sp)
-    sw a5, 13*4(sp)
-    sw a6, 14*4(sp)
-    sw a7, 15*4(sp)
+    addi sp, sp, -16*REGBYTES
+
+    STORE ra, 0*REGBYTES(sp)
+    STORE t0, 1*REGBYTES(sp)
+    STORE t1, 2*REGBYTES(sp)
+    STORE t2, 3*REGBYTES(sp)
+    STORE t3, 4*REGBYTES(sp)
+    STORE t4, 5*REGBYTES(sp)
+    STORE t5, 6*REGBYTES(sp)
+    STORE t6, 7*REGBYTES(sp)
+    STORE a0, 8*REGBYTES(sp)
+    STORE a1, 9*REGBYTES(sp)
+    STORE a2, 10*REGBYTES(sp)
+    STORE a3, 11*REGBYTES(sp)
+    STORE a4, 12*REGBYTES(sp)
+    STORE a5, 13*REGBYTES(sp)
+    STORE a6, 14*REGBYTES(sp)
+    STORE a7, 15*REGBYTES(sp)
 
     jal ra, _start_trap_rust
 
-    lw ra, 0*4(sp)
-    lw t0, 1*4(sp)
-    lw t1, 2*4(sp)
-    lw t2, 3*4(sp)
-    lw t3, 4*4(sp)
-    lw t4, 5*4(sp)
-    lw t5, 6*4(sp)
-    lw t6, 7*4(sp)
-    lw a0, 8*4(sp)
-    lw a1, 9*4(sp)
-    lw a2, 10*4(sp)
-    lw a3, 11*4(sp)
-    lw a4, 12*4(sp)
-    lw a5, 13*4(sp)
-    lw a6, 14*4(sp)
-    lw a7, 15*4(sp)
-
-    addi sp, sp, 16*4
+    LOAD ra, 0*REGBYTES(sp)
+    LOAD t0, 1*REGBYTES(sp)
+    LOAD t1, 2*REGBYTES(sp)
+    LOAD t2, 3*REGBYTES(sp)
+    LOAD t3, 4*REGBYTES(sp)
+    LOAD t4, 5*REGBYTES(sp)
+    LOAD t5, 6*REGBYTES(sp)
+    LOAD t6, 7*REGBYTES(sp)
+    LOAD a0, 8*REGBYTES(sp)
+    LOAD a1, 9*REGBYTES(sp)
+    LOAD a2, 10*REGBYTES(sp)
+    LOAD a3, 11*REGBYTES(sp)
+    LOAD a4, 12*REGBYTES(sp)
+    LOAD a5, 13*REGBYTES(sp)
+    LOAD a6, 14*REGBYTES(sp)
+    LOAD a7, 15*REGBYTES(sp)
+
+    addi sp, sp, 16*REGBYTES
     mret
 
 
diff --git a/riscv-rt/asm.h b/riscv-rt/asm.h
new file mode 100644
index 00000000..529b0da7
--- /dev/null
+++ b/riscv-rt/asm.h
@@ -0,0 +1,15 @@
+#ifndef _RISCV_RT_ASM_H
+#define _RISCV_RT_ASM_H
+
+#if __riscv_xlen == 64
+# define STORE    sd
+# define LOAD     ld
+# define LOG_REGBYTES 3
+#else
+# define STORE    sw
+# define LOAD     lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif

From 6fe10d1bcde4ea57686cfc8350a561a742a31729 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 19 Jul 2019 17:38:16 +0300
Subject: [PATCH 103/234] Regenerate binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1954 -> 1838 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1954 -> 1838 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2794 -> 2642 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2794 -> 2642 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 4fa389e0ac1a52625e0003f61d67d5242bb0b456..27eed82dd5f061ffc31344411c52d5c06f49b87e 100644
GIT binary patch
delta 334
zcmZ3)zm9Lhd}cE<i;0UgglkwB7#JBC7)*eefkA_Tmw{*FT~@})4Xjd=HJFxdzQ@GL
zD9H<!Wbgt~5*!eA5Rj7Mo5Uh6$p;Y#15(BiCPN&M78jUoz@pD6I5`2RMi3&Ag`}nm
zq(*4+1QvZ&eu!)vkP;Mzu)BbiE>v6zBrY=f2}||lB36yb(^)rj{$XNZ_yZK?njFmL
z&iR9xfq@6iTg>Jj$O80{3Wx{9Ajbl^U|Enaf!g4}0w@pw#N0p;kZzDV0U+iCVxWO=
V&@nlgU0p&0C>;nFgM=A~3jlYjBc}iW

delta 496
zcmZ3-w}^kjd}ebClZlHogio+AFfcMOFqi-_1A_(w9|P~kyR3{Fjv7F2QD$*+83Usn
zkjYw9W^9ycRA3OF3nCIhL^6<={E$(0@^8lF{2=Wxz|6q4c_9-QqbDCk#0yACa6s5W
zKuQX#8pJk+2s4BMX=$i9hz%2u1G2>hCx2nqHxz;>O+%8+0<xu{;vhCmR~3*gE<8De
zMPF3_$OM8mAQlt>Ga0&olrB_U2_!B$c?C<gpdQ%2dWj_^MVU#ZC8@<=&wXIzo$SZD
zfzyJSf#DBOG52J4Hg`@FV7T#sdEspC^$tLu3Wx{9Ab$e6VA((*4b)Zuq`<%e7}T0D
z4v+?gJP3ejCNK*^qyPmHfEZ*0FA#&w1G$$Ih=Jz8!4aUQA_j)ZU)dBTQh<t*;W7xb
E0eiwZ$p8QV

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 4fa389e0ac1a52625e0003f61d67d5242bb0b456..27eed82dd5f061ffc31344411c52d5c06f49b87e 100644
GIT binary patch
delta 334
zcmZ3)zm9Lhd}cE<i;0UgglkwB7#JBC7)*eefkA_Tmw{*FT~@})4Xjd=HJFxdzQ@GL
zD9H<!Wbgt~5*!eA5Rj7Mo5Uh6$p;Y#15(BiCPN&M78jUoz@pD6I5`2RMi3&Ag`}nm
zq(*4+1QvZ&eu!)vkP;Mzu)BbiE>v6zBrY=f2}||lB36yb(^)rj{$XNZ_yZK?njFmL
z&iR9xfq@6iTg>Jj$O80{3Wx{9Ajbl^U|Enaf!g4}0w@pw#N0p;kZzDV0U+iCVxWO=
V&@nlgU0p&0C>;nFgM=A~3jlYjBc}iW

delta 496
zcmZ3-w}^kjd}ebClZlHogio+AFfcMOFqi-_1A_(w9|P~kyR3{Fjv7F2QD$*+83Usn
zkjYw9W^9ycRA3OF3nCIhL^6<={E$(0@^8lF{2=Wxz|6q4c_9-QqbDCk#0yACa6s5W
zKuQX#8pJk+2s4BMX=$i9hz%2u1G2>hCx2nqHxz;>O+%8+0<xu{;vhCmR~3*gE<8De
zMPF3_$OM8mAQlt>Ga0&olrB_U2_!B$c?C<gpdQ%2dWj_^MVU#ZC8@<=&wXIzo$SZD
zfzyJSf#DBOG52J4Hg`@FV7T#sdEspC^$tLu3Wx{9Ab$e6VA((*4b)Zuq`<%e7}T0D
z4v+?gJP3ejCNK*^qyPmHfEZ*0FA#&w1G$$Ih=Jz8!4aUQA_j)ZU)dBTQh<t*;W7xb
E0eiwZ$p8QV

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index b9289a01bc822013c03e0a67c2f2a11f191c935c..3b6e90deefdf443dbb3a142a74f956b12f92ea83 100644
GIT binary patch
delta 385
zcmaDQdP!u$d}b4Kqlt?Q#533!z<?1*I)GUY47?0H6JPeaOBS*{5PKr^Lhen`hq5nK
zKkELhda&-vrWf1Z?E0|p%b_2~{=EP2|8G;mq9mu}N6Acei|U-}AJwy^E=zSwdzQvl
zzO3A>;#mdf<h_ihlN;D&Hrp|=Fm8@wj$vfvoxGhzpOJ6!b1*5+s?R7e*_}0>QE>8d
zAX{+qbs#A;nVl_Ok{|3O2+;;*3j%53$@OgFD6&dOvLch$vn`oi#BKq!mw)prb_qto
z9n28<A0Uqc0oUZq9QlG9SRp(K2n7@k=FHbU0TuOti2`X3C<Y0^RD+CSnyknqEb0L@
f6=pg&P=;r6IF~k~!{lZzdrkppC<jjF=8y*fwX#<|

delta 513
zcmca4@=A2Vd}cEvlZlHA#1F7BfB_?rbO5s)82A`?C%)`;w=85kAa+RVh}^NF6J@8W
z&eWaLx}bN-=!)4js~dK=obI^Yd;j78-zJAiPD;+3oSpnG`6c;(@@ER26si=qDa<MS
zQg~9trwGN#dl^kN95sMu7iAVFmoYHP0hz2tWo9OsMg<1(xga7DL?i==$qyM-HuEvD
zFi!r!$imFbz_po?IhT=<Z*o41J|q9+`C#%qkQAK!pCz7AXmUKOK9KAOlERbsv&J(D
zOqOR8mlOf}1VVH{*}6blV6s1(IHTy~bhagedSK`1C6<&FWhRxDq!v#WWOoEw%epy;
zU4l`Nfd!)P2PkBKfO~Q^N50?>RtQf5LIFj8bL1xqKm*YOCJLlEpco_sQymCoGczz0
zfW(l22h<KtWI-SsD$Kwzxtmj7v;xW%V1g*)0aCn^_j779c1(WFX|E9hbwx5RQ=sAi
DOF3lS

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index b9289a01bc822013c03e0a67c2f2a11f191c935c..3b6e90deefdf443dbb3a142a74f956b12f92ea83 100644
GIT binary patch
delta 385
zcmaDQdP!u$d}b4Kqlt?Q#533!z<?1*I)GUY47?0H6JPeaOBS*{5PKr^Lhen`hq5nK
zKkELhda&-vrWf1Z?E0|p%b_2~{=EP2|8G;mq9mu}N6Acei|U-}AJwy^E=zSwdzQvl
zzO3A>;#mdf<h_ihlN;D&Hrp|=Fm8@wj$vfvoxGhzpOJ6!b1*5+s?R7e*_}0>QE>8d
zAX{+qbs#A;nVl_Ok{|3O2+;;*3j%53$@OgFD6&dOvLch$vn`oi#BKq!mw)prb_qto
z9n28<A0Uqc0oUZq9QlG9SRp(K2n7@k=FHbU0TuOti2`X3C<Y0^RD+CSnyknqEb0L@
f6=pg&P=;r6IF~k~!{lZzdrkppC<jjF=8y*fwX#<|

delta 513
zcmca4@=A2Vd}cEvlZlHA#1F7BfB_?rbO5s)82A`?C%)`;w=85kAa+RVh}^NF6J@8W
z&eWaLx}bN-=!)4js~dK=obI^Yd;j78-zJAiPD;+3oSpnG`6c;(@@ER26si=qDa<MS
zQg~9trwGN#dl^kN95sMu7iAVFmoYHP0hz2tWo9OsMg<1(xga7DL?i==$qyM-HuEvD
zFi!r!$imFbz_po?IhT=<Z*o41J|q9+`C#%qkQAK!pCz7AXmUKOK9KAOlERbsv&J(D
zOqOR8mlOf}1VVH{*}6blV6s1(IHTy~bhagedSK`1C6<&FWhRxDq!v#WWOoEw%epy;
zU4l`Nfd!)P2PkBKfO~Q^N50?>RtQf5LIFj8bL1xqKm*YOCJLlEpco_sQymCoGczz0
zfW(l22h<KtWI-SsD$Kwzxtmj7v;xW%V1g*)0aCn^_j779c1(WFX|E9hbwx5RQ=sAi
DOF3lS


From 370700c3be713dfed96af3907a8ed85704090cfe Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@gmail.com>
Date: Wed, 7 Aug 2019 14:21:57 +0000
Subject: [PATCH 104/234] link.x: Add .sdata2 sections

Clang doesn't seem to generate these, but GCC does. I'm trying to
link secp256k1, which is a C library, to my Rust code so the linker
script needs to include these sections too.
---
 riscv-rt/link.x | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 529bc75e..ae4e7a86 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -57,7 +57,7 @@ SECTIONS
     _sdata = .;
     /* Must be called __global_pointer$ for linker relaxations to work. */
     PROVIDE(__global_pointer$ = . + 0x800);
-    *(.sdata .sdata.*);
+    *(.sdata .sdata.* .sdata2 .sdata2.*);
     *(.data .data.*);
     . = ALIGN(4);
     _edata = .;

From e962e8c2ea2d1143a2c9093ff0ac4bd5725b5c49 Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@gmail.com>
Date: Thu, 8 Aug 2019 19:56:21 +0200
Subject: [PATCH 105/234] Bump version from 0.6.0 to 0.6.1

---
 riscv-rt/Cargo.toml | 2 +-
 riscv-rt/src/lib.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 2ee24a58..6067e000 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.6.0"
+version = "0.6.1"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 17dfc36f..5f7b5683 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -30,7 +30,7 @@
 //! $ # add this crate as a dependency
 //! $ edit Cargo.toml && cat $_
 //! [dependencies]
-//! riscv-rt = "0.6.0"
+//! riscv-rt = "0.6.1"
 //! panic-halt = "0.2.0"
 //!
 //! $ # memory layout of the device

From cd995c626c0cdcc7adf2ccabc4cbb864ca74a887 Mon Sep 17 00:00:00 2001
From: Ian Kronquist <iankronquist@gmail.com>
Date: Thu, 3 Oct 2019 12:12:12 -0700
Subject: [PATCH 106/234] Simple typo fix

---
 riscv-rt/examples/multi_core.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs
index f9092407..de34e8ec 100644
--- a/riscv-rt/examples/multi_core.rs
+++ b/riscv-rt/examples/multi_core.rs
@@ -30,7 +30,7 @@ pub extern "Rust" fn user_mp_hook() -> bool {
                 }
             }
 
-            // Start listening for software interrupts
+            // Stop listening for software interrupts
             mie::clear_msoft();
 
             // Clear IPI

From 4e9aa15f02c8576d74d58ca0a6b99d0ac2cbd801 Mon Sep 17 00:00:00 2001
From: Vadzim Dambrouski <pftbest@gmail.com>
Date: Fri, 22 Nov 2019 02:02:17 +0300
Subject: [PATCH 107/234] Make linker script compatible with GNU linker.

Assigning to the dot inside the section declaration is section
relative, not absolute.
---
 riscv-rt/link.x | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index ae4e7a86..1a46dbea 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -25,7 +25,7 @@ SECTIONS
   .text.dummy (NOLOAD) :
   {
     /* This section is intended to make _stext address work */
-    . = _stext;
+    . = ABSOLUTE(_stext);
   } > REGION_TEXT
 
   .text _stext :
@@ -84,7 +84,7 @@ SECTIONS
   .stack (NOLOAD) :
   {
     _estack = .;
-    . = _stack_start;
+    . = ABSOLUTE(_stack_start);
     _sstack = .;
   } > REGION_STACK
 

From 09b1f01d3525e52f04f7ab9f843c5442acd89b7e Mon Sep 17 00:00:00 2001
From: Ivan Stankovic <istankovic@users.noreply.github.com>
Date: Mon, 17 Feb 2020 22:22:28 +0100
Subject: [PATCH 108/234] Place abort in the .text section

Don't clutter the .init section needlessly.
---
 riscv-rt/asm.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 61f3bd6e..5b20f898 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -133,7 +133,7 @@ _start_trap:
 
 
 /* Make sure there is an abort when linking */
-.section .init
+.section .text
 .globl abort
 abort:
     j abort

From 0f39348af1805667987097a54cefbb67be0740a9 Mon Sep 17 00:00:00 2001
From: Ivan Stankovic <istankovic@posteo.net>
Date: Tue, 18 Feb 2020 22:22:01 +0100
Subject: [PATCH 109/234] Update binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1838 -> 2002 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1838 -> 2002 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2642 -> 2866 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2642 -> 2866 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 27eed82dd5f061ffc31344411c52d5c06f49b87e..9808bda9eb3437be74309cd8d5673a9717ae7c60 100644
GIT binary patch
literal 2002
zcma)6-Afcv6hC)2v+T=06^+=;?0eeWMJ%M&Ro9O;EkWz4adz9<Ep=^Xl9DK{k3B@x
zL$Cb}_0VfXghWJ0L`3v2WEKQL)bGsPt1}Bx2hP2}-|wC|_spGpW@m?G=ZnW{4#&b4
z4^STm$5<@cssqMqh$sr5)NVSiWxHhM${2lOy0$e%WS5-$^dZ|d%Km<T+odg;^wJ+`
zPpEyyYHs&rGeQV#;+vpvw9JU!t{{&mz2&{Mf!33F<eW~$;Ypbiow8G;Wm<H}F3~N!
zMUU(e8JQ8ivRCxUKG84x#ef_TC*?_zm0590o)Uv{Pz=eThuG+W6y&s|zCMir&qgT!
z{W+BvPW-IH+Gf<H^(T?hNJ5-RB~}P}sA8Ra!}0RM?H@<4u6(xbdBckxFYUSMS2M3~
zz1jcPm~Va8_Wsz1;~&$XGM~RJ{QfnYx}R?9dfb&BoFB{$Ee=IS?vFH$J|0b<oj;p9
zw|H)+<xniXMW4gWFo~N&G_H$O^Lf<5x2rWhb?yc74xhvhz$$w>(OPPqiklNWSUlu0
z==i_Q(a?$WXXg*UY*E5T2w0S=DxUE9-KChSCBz^~)n0sNN%iA%75r9!FF}APtqxM~
zHFPAP)S{l1Ax>0Z!FPwapaUUJ)Ly~+L%f<sLY&B|;ACXuF*40d<K>(+Zcdd;lWxIo
zCUe5NZWhrvX6Ztpck)+MJNav9Emlf1g-~ayF0-#Wp^h^>!7tztUkn(ZZQXhg(g3FV
zRX!fZ)UaV0Cwxewm>ZSOSnK>v>Nfg8jJ19dxL$n*##+A&+^`7)jIq}Fx6!C{##-lZ
zT(=nmjIq{df$RC717oc9^S~R`JKkZe8l;KwRt&Hh{HVHe&A_|VWnjEVUq!>YG2vP{
zG91_T=b}b-Vcas@!gZI73zln<k#ig}Jhe1gg6aqGzs`q+qIuD_CJLbZ>oY9ZwM)5c
zZo$Eh|7S6TabK%aiT`gAxHgR&A#nGl)ItYZb1g7CKhJB7TNKxw+Xfyqj%7Ot=d1Cr
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f@pa|g`iuc-4u#qbl<9ojYQeZ75)^e1W*zqj^n&M1

literal 1838
zcma)6&rcIU6n@iUMFa&g(okaxq7ao@pg}N%lmg{fp+G_*9$dCiY!xW(t^^x`84ku6
z4+alh{TuM$QDTfS#u!74F~)fICgMR47=3SNhi;n~dC8mkzHi>Xd7YWpsy0=dO12kW
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zsjtr+6{weEMN)g>h&h_rNU*7Z!MYWvKOFU^x1arFk6UlLHcvdSd~xcf_G<BU=FQ66
zbMJgxjqjU3T>jYpDfBt~<=gh3->bp3P<7`<XJ}|^C?4I3I>y$<s$(0m(D>GPd}3#!
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z37AMKGnzV=5IgK|^k5kEp;Z=$|Dx=-vb(CRIQrWp%a5ZRWVPsY)&Gm59?9SL0cz4@
zz6&T&hX$>MT`Xu9F<lMm<i+T1==OY@$Rp^|WWGx%*z^6uLg{<TM`s}O^&qBi<nJ#=
zLbXVvII<ABJzoKm8q_Esodc~=etRyY(1OA+`eAFG;^>*vla^<P5bj|C8Uf2F4;ejW
Pdt4nR7%^AGAmjc52nf*6

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 27eed82dd5f061ffc31344411c52d5c06f49b87e..9808bda9eb3437be74309cd8d5673a9717ae7c60 100644
GIT binary patch
literal 2002
zcma)6-Afcv6hC)2v+T=06^+=;?0eeWMJ%M&Ro9O;EkWz4adz9<Ep=^Xl9DK{k3B@x
zL$Cb}_0VfXghWJ0L`3v2WEKQL)bGsPt1}Bx2hP2}-|wC|_spGpW@m?G=ZnW{4#&b4
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z{W+BvPW-IH+Gf<H^(T?hNJ5-RB~}P}sA8Ra!}0RM?H@<4u6(xbdBckxFYUSMS2M3~
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literal 1838
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Pdt4nR7%^AGAmjc52nf*6

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index 3b6e90deefdf443dbb3a142a74f956b12f92ea83..719d802822802a53a3dfd7c2464f6b1744862071 100644
GIT binary patch
literal 2866
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zUD7$s3V?|yas+Ml{mFA}MtqIJ>k&4+*X0U6Ana|Z*9PEi3P$E7G2f0_<x5=W%lkz6
ztP{SZB(C#^1c&leZ<oY%{x!j;{MQScl*DyDwPzB_U*$_&=gWIf`EMXcArja5Gh&_c
zr(c2;iR=8!f<W&^J;!?rE_)h5yA^zsut^!hK7m^85-kGXgPOiIDH7k0fXauMdwayQ
za;QDW*9B=g_OKQ6><JHIS1iwhSk84JRzZuSMMQl9{o{PoE|^1(HDcqGet9v=^PFPt
zrf0h{jsMmLdQulqYog6kG@wL$RUP#?oj-NoRF&Zy%SB73^CMY>55<w+jKuc|T<`2@
z#Dj$PP~|XAXwU!kPoi&7{W8A(KhWb-KMtzj5cSUq2dba$hhBesNc<0olVp8W9rgGp
zaV03eJW%<bDL!>+JwEMEd+O(Eh(K{%Q$_kqtP_o(_*=w<>JmhXPkl)G%e<)H;n|G|
zT2-AF@efuJ-_Yw1%AJ^Z1+hsKwi+>d^!SvMes>UpSphmUQACeV{U*qNP}E;ge96@P
F{{nXK?uY;Y

delta 901
zcmZ`$y)Q#i6u<Y~_t8ErN_q7akq$*8zSBsEM?#wriHL<n#DW-vv4fZljX`q;W5r(}
z445Pqq9%*oWU!d9Ip_7Xm8MSe?)jZ_e&=`YJNL5rC47=oBZ;Bx`9NgL6rM>uT@Se;
zC;}q;v8vwhHCT|n`rVg2gS4E7CpiFzRy)jUtx|(Q&4G2T*P>P-bjWIs(nSXIjY<iV
zVyVNY=CtWz&Eu30?h$Eb`(RNKds`(vjVm=HP54o_!C7u{&<EjF@0Yb;8FVI$=tNPM
zs`X|0(!Ak6If5G;N6`CW(})|bh(d6RsLewUsG4RLsWvbsSIk$c9x#VgZHSrCi51S!
zo$45qJ7OF{-^iF;hH)SII>?!h48yg#3vp`{_AM8;Zne<;Xm9*t+=0&qdzRCqmEr>E
zLPu;>kuR_d`!APb2z~#t;msHBs5+Sij$z3cUDh#jIa72uJpP*p+E^eS%_5_Xk&WY5
zZNf9m`D0TFtX5OMFsQezLh7`gO7$e{+K!As-X9yA#(FiaN7hPVos6_dr=$ftc4t$H
e|D*UnHOL4+&W=kL^7dqRJwMJO=KmVEl~TW)Hd3Pi

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index 3b6e90deefdf443dbb3a142a74f956b12f92ea83..719d802822802a53a3dfd7c2464f6b1744862071 100644
GIT binary patch
literal 2866
zcmbVNOKTKC5U$=$qQ+Nz#uqYbe4(yuvMdUso7HSy8>0a|I+<N3?rM^aGh>WF5<5o^
z67b+vJb3WnK|#TT2M^-WpAbaEL%<aS22r$Xr+e-6&Ri^*uIjJ9>Z+RVso8bXa`J^!
zjYo~85?7|at&WC~XqAM)MgWN7Gb$g`^(@B&D_6qNpO~IwjR81CH$Q&F@nR)EURac5
zB2n4CHF+ZG#~Ey#?#N~$jA0O87<`9+Gl>GcZ;<N%sfw9`wXg=*BlmnNj!%N8SUYcL
zX`W_h_!)MVpJg4qgJpPzb@EQu#k*KH?`A!`hxPJamgQO2$NShhevb9?{)ZU!0cYUu
zOMQD4L3<_w`GvPoDxdz@jB6V(M~T0PT#B@@3#qm`1`h?-ogIjm%F{o#-e{QH{At^l
zo%2q4d|`5N>eth`XP=&bc{%^O{AS_p;=5m8%YS~)3_i}K^B?n(smD|4>5tP5_7giZ
z^m(Y^){|SAiO&-&EEkM8mASD}D*&4u0CtD5?W-fp==~7BL#(N){Q%A?2Lfy-n)S|j
zGEr<Di<=`fSTy8uP<_JeXy8fEwV;bpD^aMc1rdoteGTrPaX5az#)I}*R)flYGTMs7
zb0PSYhSM|(D*{l$SJvRi5NQgii>_%?4I5xf2)?(1``M~)heG(rL-6hjUi*G7hVZQr
z9AeqH0j7C%xRkSo&9PE()U%xyFh{Hjvw#i2EM8H1K>oUD3;r6m2ttaJ_L2@Ex`lJo
zUD7$s3V?|yas+Ml{mFA}MtqIJ>k&4+*X0U6Ana|Z*9PEi3P$E7G2f0_<x5=W%lkz6
ztP{SZB(C#^1c&leZ<oY%{x!j;{MQScl*DyDwPzB_U*$_&=gWIf`EMXcArja5Gh&_c
zr(c2;iR=8!f<W&^J;!?rE_)h5yA^zsut^!hK7m^85-kGXgPOiIDH7k0fXauMdwayQ
za;QDW*9B=g_OKQ6><JHIS1iwhSk84JRzZuSMMQl9{o{PoE|^1(HDcqGet9v=^PFPt
zrf0h{jsMmLdQulqYog6kG@wL$RUP#?oj-NoRF&Zy%SB73^CMY>55<w+jKuc|T<`2@
z#Dj$PP~|XAXwU!kPoi&7{W8A(KhWb-KMtzj5cSUq2dba$hhBesNc<0olVp8W9rgGp
zaV03eJW%<bDL!>+JwEMEd+O(Eh(K{%Q$_kqtP_o(_*=w<>JmhXPkl)G%e<)H;n|G|
zT2-AF@efuJ-_Yw1%AJ^Z1+hsKwi+>d^!SvMes>UpSphmUQACeV{U*qNP}E;ge96@P
F{{nXK?uY;Y

delta 901
zcmZ`$y)Q#i6u<Y~_t8ErN_q7akq$*8zSBsEM?#wriHL<n#DW-vv4fZljX`q;W5r(}
z445Pqq9%*oWU!d9Ip_7Xm8MSe?)jZ_e&=`YJNL5rC47=oBZ;Bx`9NgL6rM>uT@Se;
zC;}q;v8vwhHCT|n`rVg2gS4E7CpiFzRy)jUtx|(Q&4G2T*P>P-bjWIs(nSXIjY<iV
zVyVNY=CtWz&Eu30?h$Eb`(RNKds`(vjVm=HP54o_!C7u{&<EjF@0Yb;8FVI$=tNPM
zs`X|0(!Ak6If5G;N6`CW(})|bh(d6RsLewUsG4RLsWvbsSIk$c9x#VgZHSrCi51S!
zo$45qJ7OF{-^iF;hH)SII>?!h48yg#3vp`{_AM8;Zne<;Xm9*t+=0&qdzRCqmEr>E
zLPu;>kuR_d`!APb2z~#t;msHBs5+Sij$z3cUDh#jIa72uJpP*p+E^eS%_5_Xk&WY5
zZNf9m`D0TFtX5OMFsQezLh7`gO7$e{+K!As-X9yA#(FiaN7hPVos6_dr=$ftc4t$H
e|D*UnHOL4+&W=kL^7dqRJwMJO=KmVEl~TW)Hd3Pi


From 23605f5b3561445b5222ef2ad33768c123cfc1cf Mon Sep 17 00:00:00 2001
From: Ein Terakawa <applause@elfmimi.jp>
Date: Fri, 28 Feb 2020 01:41:04 +0900
Subject: [PATCH 110/234] Assure address of PC at startup.

---
 riscv-rt/asm.S | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 5b20f898..794902db 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -12,6 +12,25 @@
 .global _start
 
 _start:
+    /* Jump to the absolute address defined by the linker script. */
+    // for 32bit
+    .if __riscv_xlen == 32
+    lui ra, %hi(_abs_start)
+    jr %lo(_abs_start)(ra)
+    .endif
+
+    // for 64bit
+    .if __riscv_xlen == 64
+1:
+    auipc ra, %pcrel_hi(1f)
+    ld ra, %pcrel_lo(1b)(ra)
+    jr ra
+    .align  3
+1:
+    .dword _abs_start
+    .endif
+
+_abs_start:
     .cfi_startproc
     .cfi_undefined ra
 

From 7e4c1b972c4ec52453966e1afab5503486890a7f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 27 Feb 2020 20:47:59 +0300
Subject: [PATCH 111/234] Update binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 2002 -> 1970 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 2002 -> 1970 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2866 -> 2986 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2866 -> 2986 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 9808bda9eb3437be74309cd8d5673a9717ae7c60..bd203144706ffcf67c44532c593ea123b74bfcf6 100644
GIT binary patch
literal 1970
zcma)6-Afcv6hC*@kF+$+N^v9B4=h5rRTs$+S$F+*T}|?Xh{jo6bxU2FnZ%?IuMa)+
z6bAa*Lw|ui_*h6pghWV$MD#CY7C{eT=gi!@&MZV8ICp-(-#PcpoqOlpvL;m<n`+Lz
z=yjUkMlEa~z1~2bOc>1t05|%qbVWB*%>Xr)#L*&(p{a8KT0$S2uh9%&(t6*&-qH{V
znB{9P`9;cT?!&f7J7WxAVi|)UaKHd|GQi{kGkhNMArIKI4P=u`0D6DWj~?Jb*1}s@
zh=*91hgmCcWo^8Twexn?!8=$d?_^!Pi*@sE*28;PghyB}?`2UQWqrJF4PW?_GtjGo
z-#1){mt8RSa}$!gFMk(ftO(a9^%t%oS3SEDtj}PuCUW&B1ODXh{;$T{S+7oSmcBmw
zMteK|ZgK0u`wJg@+jSosK3(2v{v7(!{`K4L{-5RGN~k=%9u7sfqp`ldKG)#NVENGc
zP-u92I5x63Ql{$Q^`Er11K8pKuzQSo@?6=pF9qmlMC>pRw_`WyNa;`y%ni7~HgiL!
zIpau5%Y<Wy)A_0`o`MM6kZtBiQ=&EhW*UEF<0**14LQ(c6AExWg$@o-k;eTF&Y;1;
z0m5ngs)J|4sDlGcr*Tl!m@a;QU&QYPMVXvV#?)zLE}57$;#wsrGwOmeh5ex<#%(P!
zc1ujNV%R~XBo^b21`^Gr-O(M5rI><POAQ^ou+mJ40O|##Q}hU(u+-@siu0|c0eqC?
zSoj(~N{=64nSTQ%kI)HAozAaV90Xyh)Adk7cLf?@scVQ!PmqfD1G?1b5qpGASnBjY
z6c^!uMp){P5tke#6@akRClD8kJy{_v8m64^DICze=#5!~04mWdvQ22>b3zB7es{)D
zWB4>Q>p3Nn7N1sqMts2l-?(b1;EU-x_)Il1n?Th{pgYil@hN3OQ)lAVYYsJfF^l?I
zE{E<pyjD^su?H18*Pw`0VjELm($>&?iV?389K)vBdw~SXC96iKp8j7R&9|?Q_$s<I
zS+5oa`}+J?*o#40AN`hceJzOX^|p{l(51<GbO+e$^&_G0qk43VvL4N)IdY#$kW?d=
zMtNi%==OTokyN5a^{6E%M)mErkU}d8qv#aNL#I6Y?P!kNJB08Y7jU0|FsegFEo0AH
M!U98P#2RGYUpOM&GXMYp

delta 904
zcmZ9LJ4*vW6ov0>+>P;-#8*}YpOHjG(ZnK!AcBZm3JQW4qbP}>gd_%ST(ndWb^d_Z
z+W8wSEXCH!POz~PwDH{8he<BXo$s8vdxx3beGI+^ukW;E;^scy`BFzDh-eyvC{96Y
zA#r!}v8B!a$Yn9AS>LiOj^lH2EEjUcoid4Dpk62^6S+iwGJU`)!)XUezKed@prtHs
zXNRsfxN;@w9x?dHuhthl*RJ2L(We#KLx7J0l@hv<rilLc4`D;2q9g=1YxHoH7Bp6+
ziBdIssY?54wMr9ZaEo5>hH~9^Y>hJ^_^1)5U>R)IvrDvs(H&H%IB6rTVeWB!X4mH{
ziiGVVX4l^Xo6fB;JHAEx5Z$dv2xj+zLvWAdGrK<Dd87>q!R-3yV6%Z;B4*d$1c#kN
zUNE;KAqFwR9k+U8m-FtUFov9$!W`3ORNn|ss1Ix+Qz{j5+ef9{qCC?xff*lB6N;MT
zr(P6SGHnb67U6v<@6zZKPx8Tt1ycBw?YcL3A^B^>ta*660sDL-kc#;l(ISsY#SH#|
v5m#X5UxI^YO_80lFt#w7A$f2=J}~!2KQEr~Pyw&~#6MtWQIz#o{(Juc$S+I#

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 9808bda9eb3437be74309cd8d5673a9717ae7c60..bd203144706ffcf67c44532c593ea123b74bfcf6 100644
GIT binary patch
literal 1970
zcma)6-Afcv6hC*@kF+$+N^v9B4=h5rRTs$+S$F+*T}|?Xh{jo6bxU2FnZ%?IuMa)+
z6bAa*Lw|ui_*h6pghWV$MD#CY7C{eT=gi!@&MZV8ICp-(-#PcpoqOlpvL;m<n`+Lz
z=yjUkMlEa~z1~2bOc>1t05|%qbVWB*%>Xr)#L*&(p{a8KT0$S2uh9%&(t6*&-qH{V
znB{9P`9;cT?!&f7J7WxAVi|)UaKHd|GQi{kGkhNMArIKI4P=u`0D6DWj~?Jb*1}s@
zh=*91hgmCcWo^8Twexn?!8=$d?_^!Pi*@sE*28;PghyB}?`2UQWqrJF4PW?_GtjGo
z-#1){mt8RSa}$!gFMk(ftO(a9^%t%oS3SEDtj}PuCUW&B1ODXh{;$T{S+7oSmcBmw
zMteK|ZgK0u`wJg@+jSosK3(2v{v7(!{`K4L{-5RGN~k=%9u7sfqp`ldKG)#NVENGc
zP-u92I5x63Ql{$Q^`Er11K8pKuzQSo@?6=pF9qmlMC>pRw_`WyNa;`y%ni7~HgiL!
zIpau5%Y<Wy)A_0`o`MM6kZtBiQ=&EhW*UEF<0**14LQ(c6AExWg$@o-k;eTF&Y;1;
z0m5ngs)J|4sDlGcr*Tl!m@a;QU&QYPMVXvV#?)zLE}57$;#wsrGwOmeh5ex<#%(P!
zc1ujNV%R~XBo^b21`^Gr-O(M5rI><POAQ^ou+mJ40O|##Q}hU(u+-@siu0|c0eqC?
zSoj(~N{=64nSTQ%kI)HAozAaV90Xyh)Adk7cLf?@scVQ!PmqfD1G?1b5qpGASnBjY
z6c^!uMp){P5tke#6@akRClD8kJy{_v8m64^DICze=#5!~04mWdvQ22>b3zB7es{)D
zWB4>Q>p3Nn7N1sqMts2l-?(b1;EU-x_)Il1n?Th{pgYil@hN3OQ)lAVYYsJfF^l?I
zE{E<pyjD^su?H18*Pw`0VjELm($>&?iV?389K)vBdw~SXC96iKp8j7R&9|?Q_$s<I
zS+5oa`}+J?*o#40AN`hceJzOX^|p{l(51<GbO+e$^&_G0qk43VvL4N)IdY#$kW?d=
zMtNi%==OTokyN5a^{6E%M)mErkU}d8qv#aNL#I6Y?P!kNJB08Y7jU0|FsegFEo0AH
M!U98P#2RGYUpOM&GXMYp

delta 904
zcmZ9LJ4*vW6ov0>+>P;-#8*}YpOHjG(ZnK!AcBZm3JQW4qbP}>gd_%ST(ndWb^d_Z
z+W8wSEXCH!POz~PwDH{8he<BXo$s8vdxx3beGI+^ukW;E;^scy`BFzDh-eyvC{96Y
zA#r!}v8B!a$Yn9AS>LiOj^lH2EEjUcoid4Dpk62^6S+iwGJU`)!)XUezKed@prtHs
zXNRsfxN;@w9x?dHuhthl*RJ2L(We#KLx7J0l@hv<rilLc4`D;2q9g=1YxHoH7Bp6+
ziBdIssY?54wMr9ZaEo5>hH~9^Y>hJ^_^1)5U>R)IvrDvs(H&H%IB6rTVeWB!X4mH{
ziiGVVX4l^Xo6fB;JHAEx5Z$dv2xj+zLvWAdGrK<Dd87>q!R-3yV6%Z;B4*d$1c#kN
zUNE;KAqFwR9k+U8m-FtUFov9$!W`3ORNn|ss1Ix+Qz{j5+ef9{qCC?xff*lB6N;MT
zr(P6SGHnb67U6v<@6zZKPx8Tt1ycBw?YcL3A^B^>ta*660sDL-kc#;l(ISsY#SH#|
v5m#X5UxI^YO_80lFt#w7A$f2=J}~!2KQEr~Pyw&~#6MtWQIz#o{(Juc$S+I#

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index 719d802822802a53a3dfd7c2464f6b1744862071..50d6c134cf78f62d9d23d26779e2ba148d5a3f8e 100644
GIT binary patch
literal 2986
zcmbtV-D@0G6hC*iN!w^_ZM4-^WvitM+U@3ppipG8Z8mAUZL|-?CnvMpjaf~yab`@{
zAW3fo!8buL;FIJbh!0W}D)^w#htfYIlv4UoaK#9DsMK@jp0m#0odwYYbI-ZI`#blX
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zZaw_1`RK2;>5X!sa;M^~Y^)Sk@2vJ#H><^&do#UPH?I~O_ZoZs5VCn%;8VO-wR{QG
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zDs<sbb-|}&ymQ~?y6_uaaPa(c$fY1x%4Z>08gz!@b`U)8y}5eXpYs;$wS}k}90PCO
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z$r1dLe8FwL+;7TffE-x_xA`kPPI;O)VgSKy{u=Wsf2mOf32yU0V?O1d<O^=|<sDM~
zPqQy6!EOH6%%S}I*(N2p&0k^;?Pc;_Z6xr6Y?FF1fm2Q*SvKB4Eq8>VV~oFqI{7LE
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zm2>z%DvQoko!WB6zKb7;V^piP`*hy)#@rUe7%o3NIxiA>8x&^`bx;I9jyB=;AF4p4
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v7MolaIljw@QO(+y;!kthXO9qEXYh0CB!s7JAygmI{9oZmeYwRnhVB11V9@Ni

literal 2866
zcmbVNOKTKC5U$=$qQ+Nz#uqYbe4(yuvMdUso7HSy8>0a|I+<N3?rM^aGh>WF5<5o^
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F{{nXK?uY;Y

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index 719d802822802a53a3dfd7c2464f6b1744862071..50d6c134cf78f62d9d23d26779e2ba148d5a3f8e 100644
GIT binary patch
literal 2986
zcmbtV-D@0G6hC*iN!w^_ZM4-^WvitM+U@3ppipG8Z8mAUZL|-?CnvMpjaf~yab`@{
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z5@S!sb`R`NU}PR*+=4;kzH1E#zT5@>%EGCefxR8*BqIA$_Tl*$@1VoUF8HY!H@lbg
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literal 2866
zcmbVNOKTKC5U$=$qQ+Nz#uqYbe4(yuvMdUso7HSy8>0a|I+<N3?rM^aGh>WF5<5o^
z67b+vJb3WnK|#TT2M^-WpAbaEL%<aS22r$Xr+e-6&Ri^*uIjJ9>Z+RVso8bXa`J^!
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z^m(Y^){|SAiO&-&EEkM8mASD}D*&4u0CtD5?W-fp==~7BL#(N){Q%A?2Lfy-n)S|j
zGEr<Di<=`fSTy8uP<_JeXy8fEwV;bpD^aMc1rdoteGTrPaX5az#)I}*R)flYGTMs7
zb0PSYhSM|(D*{l$SJvRi5NQgii>_%?4I5xf2)?(1``M~)heG(rL-6hjUi*G7hVZQr
z9AeqH0j7C%xRkSo&9PE()U%xyFh{Hjvw#i2EM8H1K>oUD3;r6m2ttaJ_L2@Ex`lJo
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ztP{SZB(C#^1c&leZ<oY%{x!j;{MQScl*DyDwPzB_U*$_&=gWIf`EMXcArja5Gh&_c
zr(c2;iR=8!f<W&^J;!?rE_)h5yA^zsut^!hK7m^85-kGXgPOiIDH7k0fXauMdwayQ
za;QDW*9B=g_OKQ6><JHIS1iwhSk84JRzZuSMMQl9{o{PoE|^1(HDcqGet9v=^PFPt
zrf0h{jsMmLdQulqYog6kG@wL$RUP#?oj-NoRF&Zy%SB73^CMY>55<w+jKuc|T<`2@
z#Dj$PP~|XAXwU!kPoi&7{W8A(KhWb-KMtzj5cSUq2dba$hhBesNc<0olVp8W9rgGp
zaV03eJW%<bDL!>+JwEMEd+O(Eh(K{%Q$_kqtP_o(_*=w<>JmhXPkl)G%e<)H;n|G|
zT2-AF@efuJ-_Yw1%AJ^Z1+hsKwi+>d^!SvMes>UpSphmUQACeV{U*qNP}E;ge96@P
F{{nXK?uY;Y


From f956817f402bbb57af1d541b9f51bf08b0a44bea Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 1 Feb 2020 15:22:19 +0300
Subject: [PATCH 112/234] Pass trap frame pointer to the _start_trap_rust
 function

---
 riscv-rt/asm.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 794902db..e46b9a17 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -128,6 +128,7 @@ _start_trap:
     STORE a6, 14*REGBYTES(sp)
     STORE a7, 15*REGBYTES(sp)
 
+    add a0, sp, zero
     jal ra, _start_trap_rust
 
     LOAD ra, 0*REGBYTES(sp)

From 063c0096e1cdbd81933dbf86e8bc3f950bbb5fc0 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 1 Feb 2020 15:22:51 +0300
Subject: [PATCH 113/234] Regenerate binaries

---
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 1970 -> 2090 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 1970 -> 2090 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 2986 -> 3138 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 2986 -> 3138 bytes
 4 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index bd203144706ffcf67c44532c593ea123b74bfcf6..2c5d147910804884d2b82715b9d66b394454f3b2 100644
GIT binary patch
delta 463
zcmdnQze-@jd?rhyi3>G_HCP!K7#SECOn{hyL4$#xfp6m7-R#D!j12ET?4LZFF<8S<
z11M9JS)5$Pz$gb~vKEyY8)X_57{up-h(r*P3?wE$WK@{U#k7SVWD*Q8GjMO-%Ou9g
zC^-2Fvo$0CWC0d&Ndbs#6p%88DvSft(gKqmSi~8HCP%R7OA13IijdTlfz$|3UI0`h
zGI<A3jUYtLBp@Xy3Sp~(*kY4d8wB;hPS#5-DJjZKDlJJZp4`Zq$eF^-z`z4k!!!9c
z>vYZnAWs44eV)nPY|4xQlh?B;b53A^skqH1&nPqbH=BC>9H5vANEZ-u0x^&aW`_Z3
zpb-T?3Jg4eW@*AWKpGUXAOND7z$^$+0u(3!VqPGZ4~RkLfdU0&HqbmccmmW^%fK+X
Ql3h{a08mi|Tn1q_050`GQUCw|

delta 321
zcmZ1_u!(=dd?pKni3>G_Z?G^hFfuSOm;f;Yg9Za11MkGUyP4mA_&<3*WANk$tWuLL
zn6_>H$0W+gC@@)s#hQ_CasZ3CBtKX^LllrQhA<i8fV4FK<OUXTM#0H5So9@@AQDAL
zYRW)rgeE@#su7<21E@v-qGl415)^^3l|XFK$quXylP|GqO#Z=Y#i_!~z`z3(=ALZL
zHl5P|$Ws71ntSqXHf2Vi$^Y4uIRk+HfT+-BmuHli?9Hxj8Uqwl0qFu_P9O$y!D>MM
oWddRtZ~+P=05M2E@8t9B(u_+czh+mLXaH&mgDC>iAblVJ0Ne&JZ~y=R

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index bd203144706ffcf67c44532c593ea123b74bfcf6..2c5d147910804884d2b82715b9d66b394454f3b2 100644
GIT binary patch
delta 463
zcmdnQze-@jd?rhyi3>G_HCP!K7#SECOn{hyL4$#xfp6m7-R#D!j12ET?4LZFF<8S<
z11M9JS)5$Pz$gb~vKEyY8)X_57{up-h(r*P3?wE$WK@{U#k7SVWD*Q8GjMO-%Ou9g
zC^-2Fvo$0CWC0d&Ndbs#6p%88DvSft(gKqmSi~8HCP%R7OA13IijdTlfz$|3UI0`h
zGI<A3jUYtLBp@Xy3Sp~(*kY4d8wB;hPS#5-DJjZKDlJJZp4`Zq$eF^-z`z4k!!!9c
z>vYZnAWs44eV)nPY|4xQlh?B;b53A^skqH1&nPqbH=BC>9H5vANEZ-u0x^&aW`_Z3
zpb-T?3Jg4eW@*AWKpGUXAOND7z$^$+0u(3!VqPGZ4~RkLfdU0&HqbmccmmW^%fK+X
Ql3h{a08mi|Tn1q_050`GQUCw|

delta 321
zcmZ1_u!(=dd?pKni3>G_Z?G^hFfuSOm;f;Yg9Za11MkGUyP4mA_&<3*WANk$tWuLL
zn6_>H$0W+gC@@)s#hQ_CasZ3CBtKX^LllrQhA<i8fV4FK<OUXTM#0H5So9@@AQDAL
zYRW)rgeE@#su7<21E@v-qGl415)^^3l|XFK$quXylP|GqO#Z=Y#i_!~z`z3(=ALZL
zHl5P|$Ws71ntSqXHf2Vi$^Y4uIRk+HfT+-BmuHli?9Hxj8Uqwl0qFu_P9O$y!D>MM
oWddRtZ~+P=05M2E@8t9B(u_+czh+mLXaH&mgDC>iAblVJ0Ne&JZ~y=R

diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index 50d6c134cf78f62d9d23d26779e2ba148d5a3f8e..6d6cf156ea54b04573aab2e05e18733f5a84cb33 100644
GIT binary patch
delta 443
zcmZ1_en?`%d}d2Ci;0U2#BZ=OfB_?rbO5s)82B0ZCceDPZp_Na@czU8$@>}AC%<Ae
z&~VfM$`@r8CzmlW$^n_IMP+6tnMMT$@wp%(5kw>diOGUYDx1xid>AJyFtIQ*GjMM%
zWNu|-6b6b5Pv&Bs!YDX-KC3>X(B$)A@;{IinXJzi&nP;%pG_Y~?gx@$liveHgeUv6
zi%W`w-31}kplm@PEit*CeWjot*hzYcB_&0fNu?#J#gh#=EP+;YOwQtn5bR)qXpn&F
z<C%P!<GtVlsAvHbL>MT_Y0elhnVZX8PyiYt2pz#(`JNh3Q4g3oK$;VXIiP%)>M$Um
znSr4IDh#IzKmiN{nv=OX<$(dqz`z6w577ls@d&6(c!4qklf}8U8GlT6=C<c7fZCe@
G(gy$o(n@*&

delta 368
zcmX>ku}XZxd}a$nvx$og#2eTdz<?1*I)GUY415f{6JK6te*fYB<im{WEFjUzuNVy`
zPvDT*oW|tCxcL-w2_vJ><Ul6j$w91B7zHLjXVqsEoGi`;BHe+c@Z@r~ct(-Q*MV%2
z$?WX<jG~jx+2aj`z&1dLMNqaNkQPG{S3(jOpM0Es<>V#~hsg&xq68hlPGMk>fU4l0
ztj+meFaj!CzyuKnigKAV`b<vdG8a6-1`$K(Sk0BM_y8*E0W$|ka{@63lrJ&4np<A9
n02CxZ-~ct32gv51yq;T|al_=>-1Zt8(2xrQt3nV^ZEyhqvPU(%

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index 50d6c134cf78f62d9d23d26779e2ba148d5a3f8e..6d6cf156ea54b04573aab2e05e18733f5a84cb33 100644
GIT binary patch
delta 443
zcmZ1_en?`%d}d2Ci;0U2#BZ=OfB_?rbO5s)82B0ZCceDPZp_Na@czU8$@>}AC%<Ae
z&~VfM$`@r8CzmlW$^n_IMP+6tnMMT$@wp%(5kw>diOGUYDx1xid>AJyFtIQ*GjMM%
zWNu|-6b6b5Pv&Bs!YDX-KC3>X(B$)A@;{IinXJzi&nP;%pG_Y~?gx@$liveHgeUv6
zi%W`w-31}kplm@PEit*CeWjot*hzYcB_&0fNu?#J#gh#=EP+;YOwQtn5bR)qXpn&F
z<C%P!<GtVlsAvHbL>MT_Y0elhnVZX8PyiYt2pz#(`JNh3Q4g3oK$;VXIiP%)>M$Um
znSr4IDh#IzKmiN{nv=OX<$(dqz`z6w577ls@d&6(c!4qklf}8U8GlT6=C<c7fZCe@
G(gy$o(n@*&

delta 368
zcmX>ku}XZxd}a$nvx$og#2eTdz<?1*I)GUY415f{6JK6te*fYB<im{WEFjUzuNVy`
zPvDT*oW|tCxcL-w2_vJ><Ul6j$w91B7zHLjXVqsEoGi`;BHe+c@Z@r~ct(-Q*MV%2
z$?WX<jG~jx+2aj`z&1dLMNqaNkQPG{S3(jOpM0Es<>V#~hsg&xq68hlPGMk>fU4l0
ztj+meFaj!CzyuKnigKAV`b<vdG8a6-1`$K(Sk0BM_y8*E0W$|ka{@63lrJ&4np<A9
n02CxZ-~ct32gv51yq;T|al_=>-1Zt8(2xrQt3nV^ZEyhqvPU(%


From f233381982852529e41c784cc0b5d7e880dc58f4 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 1 Feb 2020 19:56:33 +0300
Subject: [PATCH 114/234] Implement interrupt and exception handling

---
 riscv-rt/link.x     |  13 ++-
 riscv-rt/src/lib.rs | 203 +++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 203 insertions(+), 13 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 1a46dbea..a2d48244 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -4,7 +4,18 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
-PROVIDE(trap_handler = default_trap_handler);
+PROVIDE(UserSoft = DefaultHandler);
+PROVIDE(SupervisorSoft = DefaultHandler);
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(UserTimer = DefaultHandler);
+PROVIDE(SupervisorTimer = DefaultHandler);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(UserExternal = DefaultHandler);
+PROVIDE(SupervisorExternal = DefaultHandler);
+PROVIDE(MachineExternal = DefaultHandler);
+
+PROVIDE(DefaultHandler = DefaultInterruptHandler);
+PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
 /* # Pre-initialization function */
 /* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 5f7b5683..fcc60fcb 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -249,6 +249,84 @@
 //! ```
 //!
 //! Default implementation of this function wakes hart 0 and busy-loops all the other harts.
+//!
+//! ### `ExceptionHandler`
+//!
+//! This function is called when exception is occured. The exception reason can be decoded from the
+//! `mcause` register.
+//!
+//! This function can be redefined in the following way:
+//!
+//! ``` no_run
+//! #[export_name = "ExceptionHandler"]
+//! fn custom_exception_handler(trap_frame: &riscv_rt::TrapFrame) -> ! {
+//!     // ...
+//! }
+//! ```
+//! or
+//! ``` no_run
+//! #[no_mangle]
+//! fn ExceptionHandler(trap_frame: &riscv_rt::TrapFrame) -> ! {
+//!     // ...
+//! }
+//! ```
+//!
+//! Default implementation of this function stucks in a busy-loop.
+//!
+//!
+//! ### Core interrupt handlers
+//!
+//! This functions are called when corresponding interrupt is occured.
+//! You can define an interrupt handler with one of the following names:
+//! * `UserSoft`
+//! * `SupervisorSoft`
+//! * `MachineSoft`
+//! * `UserTimer`
+//! * `SupervisorTimer`
+//! * `MachineTimer`
+//! * `UserExternal`
+//! * `SupervisorExternal`
+//! * `MachineExternal`
+//!
+//! For example:
+//! ``` no_run
+//! #[export_name = "MachineTimer"]
+//! fn custom_timer_handler() {
+//!     // ...
+//! }
+//! ```
+//! or
+//! ``` no_run
+//! #[no_mangle]
+//! fn MachineTimer() {
+//!     // ...
+//! }
+//! ```
+//!
+//! If interrupt handler is not explicitly defined, `DefaultHandler` is called.
+//!
+//! ### `DefaultHandler`
+//!
+//! This function is called when interrupt without defined interrupt handler is occured.
+//! The interrupt reason can be decoded from the `mcause` register.
+//!
+//! This function can be redefined in the following way:
+//!
+//! ``` no_run
+//! #[export_name = "DefaultHandler"]
+//! fn custom_interrupt_handler() {
+//!     // ...
+//! }
+//! ```
+//! or
+//! ``` no_run
+//! #[no_mangle]
+//! fn DefaultHandler() {
+//!     // ...
+//! }
+//! ```
+//!
+//! Default implementation of this function stucks in a busy-loop.
 
 // NOTE: Adapted from cortex-m/src/lib.rs
 #![no_std]
@@ -261,7 +339,7 @@ extern crate r0;
 
 pub use macros::{entry, pre_init};
 
-use riscv::register::mstatus;
+use riscv::register::mcause;
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -310,33 +388,134 @@ pub unsafe extern "C" fn start_rust() -> ! {
     main();
 }
 
+/// Registers saved in trap handler
+#[allow(missing_docs)]
+#[repr(C)]
+pub struct TrapFrame {
+    pub ra: usize,
+    pub t0: usize,
+    pub t1: usize,
+    pub t2: usize,
+    pub t3: usize,
+    pub t4: usize,
+    pub t5: usize,
+    pub t6: usize,
+    pub a0: usize,
+    pub a1: usize,
+    pub a2: usize,
+    pub a3: usize,
+    pub a4: usize,
+    pub a5: usize,
+    pub a6: usize,
+    pub a7: usize,
+}
+
 
 /// Trap entry point rust (_start_trap_rust)
 ///
-/// mcause is read to determine the cause of the trap. XLEN-1 bit indicates
-/// if it's an interrupt or an exception. The result is converted to an element
-/// of the Interrupt or Exception enum and passed to handle_interrupt or
-/// handle_exception.
+/// `mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
+/// if it's an interrupt or an exception. The result is examined and ExceptionHandler
+/// or one of the core interrupt handlers is called.
 #[link_section = ".trap.rust"]
 #[export_name = "_start_trap_rust"]
-pub extern "C" fn start_trap_rust() {
+pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     extern "C" {
-        fn trap_handler();
+        fn ExceptionHandler(trap_frame: &TrapFrame) -> !;
+        fn DefaultHandler();
     }
 
     unsafe {
-        // dispatch trap to handler
-        trap_handler();
+        let cause = mcause::read();
+        if cause.is_exception() {
+            ExceptionHandler(&*trap_frame)
+        } else {
+            let code = cause.code();
+            if code < __INTERRUPTS.len() {
+                let h = &__INTERRUPTS[code];
+                if h.reserved == 0 {
+                    DefaultHandler();
+                } else {
+                    (h.handler)();
+                }
+            } else {
+                DefaultHandler();
+            }
+        }
+    }
+}
 
-        // mstatus, remain in M-mode after mret
-        mstatus::set_mpp(mstatus::MPP::Machine);
+#[doc(hidden)]
+#[no_mangle]
+#[allow(unused_variables, non_snake_case)]
+pub fn DefaultExceptionHandler(trap_frame: &TrapFrame) -> ! {
+    loop {
+        // Prevent this from turning into a UDF instruction
+        // see rust-lang/rust#28728 for details
+        continue;
     }
 }
 
+#[doc(hidden)]
+#[no_mangle]
+#[allow(unused_variables, non_snake_case)]
+pub fn DefaultInterruptHandler() {
+    loop {
+        // Prevent this from turning into a UDF instruction
+        // see rust-lang/rust#28728 for details
+        continue;
+    }
+}
+
+/* Interrupts */
+#[doc(hidden)]
+pub enum Interrupt {
+    UserSoft,
+    SupervisorSoft,
+    MachineSoft,
+    UserTimer,
+    SupervisorTimer,
+    MachineTimer,
+    UserExternal,
+    SupervisorExternal,
+    MachineExternal,
+}
+
+pub use self::Interrupt as interrupt;
+
+extern "C" {
+    fn UserSoft();
+    fn SupervisorSoft();
+    fn MachineSoft();
+    fn UserTimer();
+    fn SupervisorTimer();
+    fn MachineTimer();
+    fn UserExternal();
+    fn SupervisorExternal();
+    fn MachineExternal();
+}
+
+#[doc(hidden)]
+pub union Vector {
+    handler: unsafe extern "C" fn(),
+    reserved: usize,
+}
 
 #[doc(hidden)]
 #[no_mangle]
-pub fn default_trap_handler() {}
+pub static __INTERRUPTS: [Vector; 12] = [
+    Vector { handler: UserSoft },
+    Vector { handler: SupervisorSoft },
+    Vector { reserved: 0 },
+    Vector { handler: MachineSoft },
+    Vector { handler: UserTimer },
+    Vector { handler: SupervisorTimer },
+    Vector { reserved: 0 },
+    Vector { handler: MachineTimer },
+    Vector { handler: UserExternal },
+    Vector { handler: SupervisorExternal },
+    Vector { reserved: 0 },
+    Vector { handler: MachineExternal },
+];
 
 #[doc(hidden)]
 #[no_mangle]

From 45c729ef43c905e95a748225cae8331b7595fb30 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 1 Feb 2020 20:05:20 +0300
Subject: [PATCH 115/234] Remove #![deny(warnings)] (anti-pattern)

---
 riscv-rt/src/lib.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index fcc60fcb..cda81947 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -331,7 +331,6 @@
 // NOTE: Adapted from cortex-m/src/lib.rs
 #![no_std]
 #![deny(missing_docs)]
-#![deny(warnings)]
 
 extern crate riscv;
 extern crate riscv_rt_macros as macros;

From 579f68ddf7ccc5e1328c81cdac649b2df022271a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Feb 2020 22:33:39 +0300
Subject: [PATCH 116/234] Replace mul instruction with a loop for rv32i

---
 riscv-rt/asm.S | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index e46b9a17..96fddd80 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -84,7 +84,18 @@ _abs_start:
     la sp, _stack_start
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)
+#ifdef __riscv_mul
     mul t0, a2, t0
+#else
+    beqz a2, 2f  // Jump if single-hart
+    mv t1, a2
+    mv t2, t0
+1:
+    add t0, t0, t2
+    addi t1, t1, -1
+    bnez t1, 1b
+2:
+#endif
     sub sp, sp, t0
 
     // Set frame pointer

From 88f0e911bced45de70bd4556d47381004fa3e366 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Feb 2020 22:38:47 +0300
Subject: [PATCH 117/234] Remove asm.h

---
 riscv-rt/asm.S | 11 ++++++++++-
 riscv-rt/asm.h | 15 ---------------
 2 files changed, 10 insertions(+), 16 deletions(-)
 delete mode 100644 riscv-rt/asm.h

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 96fddd80..2580bd3a 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -1,4 +1,13 @@
-#include "asm.h"
+#if __riscv_xlen == 64
+# define STORE    sd
+# define LOAD     ld
+# define LOG_REGBYTES 3
+#else
+# define STORE    sw
+# define LOAD     lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
 
 /*
     Entry point of all programs (_start).
diff --git a/riscv-rt/asm.h b/riscv-rt/asm.h
deleted file mode 100644
index 529b0da7..00000000
--- a/riscv-rt/asm.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _RISCV_RT_ASM_H
-#define _RISCV_RT_ASM_H
-
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
-#else
-# define STORE    sw
-# define LOAD     lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#endif

From b729dbfb09e353174d270434c11625ba08d7009f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Feb 2020 22:40:53 +0300
Subject: [PATCH 118/234] Add support for riscv32i

---
 riscv-rt/assemble.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index f3e9c1e2..a0db0ff6 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -11,6 +11,9 @@ riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
 riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
 ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o

From abd84cc73fa93d5ddc52e04a9d51bb2eb0228708 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Feb 2020 22:43:30 +0300
Subject: [PATCH 119/234] Generate debug info

---
 riscv-rt/assemble.sh | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index a0db0ff6..9a13a620 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -7,14 +7,14 @@ crate=riscv-rt
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
-riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
 ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
 
-riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
 ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
 

From d771a9ebd9394cb909c9f430b2976897e73b6a8a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 26 Feb 2020 22:43:49 +0300
Subject: [PATCH 120/234] Regenerate binaries

---
 riscv-rt/bin/riscv32i-unknown-none-elf.a    | Bin 0 -> 7994 bytes
 riscv-rt/bin/riscv32imac-unknown-none-elf.a | Bin 2090 -> 7558 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a  | Bin 2090 -> 7558 bytes
 riscv-rt/bin/riscv64gc-unknown-none-elf.a   | Bin 3138 -> 12306 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a | Bin 3138 -> 12306 bytes
 5 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 riscv-rt/bin/riscv32i-unknown-none-elf.a

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..2d44739deb305fe0002266d077eb683218076d2e
GIT binary patch
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literal 0
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diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
index 2c5d147910804884d2b82715b9d66b394454f3b2..c37cf08cc51706295436fa6cff584dfbc87119ae 100644
GIT binary patch
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delta 572
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diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 2c5d147910804884d2b82715b9d66b394454f3b2..c37cf08cc51706295436fa6cff584dfbc87119ae 100644
GIT binary patch
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delta 572
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diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64gc-unknown-none-elf.a
index 6d6cf156ea54b04573aab2e05e18733f5a84cb33..4939161ae844773118ea830cfffde53cfe0f9742 100644
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diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
index 6d6cf156ea54b04573aab2e05e18733f5a84cb33..4939161ae844773118ea830cfffde53cfe0f9742 100644
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KLl97XZ~*{U0aMrj


From ef6d9e709ade17ad02773b45b73eba50e4adb37e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 08:22:29 +0300
Subject: [PATCH 121/234] Add assemble.ps1

---
 riscv-rt/assemble.ps1 | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 riscv-rt/assemble.ps1

diff --git a/riscv-rt/assemble.ps1 b/riscv-rt/assemble.ps1
new file mode 100644
index 00000000..942a1f03
--- /dev/null
+++ b/riscv-rt/assemble.ps1
@@ -0,0 +1,17 @@
+# remove existing blobs because otherwise this will append object files to the old blobs
+Remove-Item -Force bin/*.a
+
+$crate = "riscv-rt"
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+
+Remove-Item bin/$crate.o

From bdaeb8e04a9ffc80d4e20589873c58e49efd9dd3 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 08:23:23 +0300
Subject: [PATCH 122/234] Use riscv64-unknown-elf-ar in assemble.sh

---
 riscv-rt/assemble.sh | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index 9a13a620..a4827638 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -8,14 +8,14 @@ crate=riscv-rt
 rm -f bin/*.a
 
 riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
 
 riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
 
 riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
 
 rm bin/$crate.o

From 9c172dac76c011d4e4bfe11b108af3041d4e02ac Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 20:38:47 +0200
Subject: [PATCH 123/234] Update dependencies

---
 riscv-rt/Cargo.toml | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 6067e000..5eab902c 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -9,13 +9,12 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 
 [dependencies]
-r0 = "0.2.2"
-riscv = "0.5.3"
+r0 = "1.0.0"
+riscv = "0.5.5"
 riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
 [features]
 inline-asm = ["riscv/inline-asm"]
 
 [dev-dependencies]
-riscv = "0.5.3"
 panic-halt = "0.2.0"

From d748c84982b3a39e585884dc6cb67c41aac5c6ed Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 20:41:13 +0200
Subject: [PATCH 124/234] [CI] allow 64-bit targets on stable

---
 riscv-rt/.travis.yml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 52f2755e..eb3551a0 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -14,8 +14,6 @@ if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_req
 
 matrix:
   exclude:
-    - rust: stable
-      env: TARGET=riscv64imac-unknown-none-elf
     - rust: 1.31.0 # MSRV
       env: TARGET=riscv64imac-unknown-none-elf
 

From c00efce87e4d08719e8e7ad78d82a7b5c03b3b3b Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 20:41:33 +0200
Subject: [PATCH 125/234] [CI] Remove obsolete hack

---
 riscv-rt/.travis.yml | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index eb3551a0..4e77ce8a 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -30,9 +30,6 @@ script:
 after_script: set +e
 
 cache: cargo
-before_cache:
-  # Travis can't cache files that are not readable by "others"
-  - chmod -R a+r $HOME/.cargo
 
 branches:
   only:

From 05073ff37a57141786cd0ccdd8e17ea23e2ba2db Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 20:46:37 +0200
Subject: [PATCH 126/234] [CI] Check riscv32i-unknown-none-elf target

---
 riscv-rt/.travis.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 4e77ce8a..0bd3108a 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -7,6 +7,7 @@ rust:
 
 env:
 - TARGET=x86_64-unknown-linux-gnu
+- TARGET=riscv32i-unknown-none-elf
 - TARGET=riscv32imac-unknown-none-elf
 - TARGET=riscv64imac-unknown-none-elf
 

From ab9cccc169ad29836e4b777c33fb24a5f4f32430 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 7 Mar 2020 22:23:19 +0200
Subject: [PATCH 127/234] Set MSRV to 1.38

---
 riscv-rt/.travis.yml | 8 +-------
 riscv-rt/src/lib.rs  | 4 +---
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 0bd3108a..c911f7d8 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -3,7 +3,7 @@ language: rust
 rust:
 - nightly
 - stable
-- 1.31.0 # MSRV
+- 1.38.0 # MSRV
 
 env:
 - TARGET=x86_64-unknown-linux-gnu
@@ -13,12 +13,6 @@ env:
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-matrix:
-  exclude:
-    - rust: 1.31.0 # MSRV
-      env: TARGET=riscv64imac-unknown-none-elf
-
-
 before_install: set -e
 
 install:
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index cda81947..7985c957 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -2,10 +2,8 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.31 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.38 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
-//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
-//! are not supported on stable yet.
 //!
 //! # Features
 //!

From 5343baf47e65f2587c3684c983e4ee36d8c1ee0c Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 10 Mar 2020 15:55:43 +0300
Subject: [PATCH 128/234] Add CHANGELOG.md

---
 riscv-rt/CHANGELOG.md | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 riscv-rt/CHANGELOG.md

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
new file mode 100644
index 00000000..387dcf5e
--- /dev/null
+++ b/riscv-rt/CHANGELOG.md
@@ -0,0 +1,28 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [Unreleased]
+
+### Added
+
+- Assure address of PC at startup
+- Implement interrupt and exception handling
+- Add support for the `riscv32i-unknown-none-elf` target
+- Added Changelog
+
+### Fixed
+
+- Fix linker script compatibility with GNU linker
+
+### Changed
+
+- Move `abort` out of the `.init` section
+- Update `r0` to v1.0.0
+- Set MSRV to 1.38
+
+
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.6.1...HEAD

From 4fc49a48ae3022b5faf7aa2b63182f76c9335119 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Tue, 10 Mar 2020 16:00:10 +0300
Subject: [PATCH 129/234] Release v0.7.0

---
 riscv-rt/CHANGELOG.md | 5 ++++-
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 387dcf5e..517c5092 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.0] - 2020-03-10
+
 ### Added
 
 - Assure address of PC at startup
@@ -25,4 +27,5 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.6.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...HEAD
+[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 5eab902c..62ff8bce 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.6.1"
+version = "0.7.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

From 9cfcd277e2f9796c0c013bb70c29c0333a661554 Mon Sep 17 00:00:00 2001
From: Diego Barrios Romero <eldruin@gmail.com>
Date: Tue, 21 Apr 2020 22:37:14 +0200
Subject: [PATCH 130/234] Document MSRV on README

---
 riscv-rt/README.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index 9d4e4715..af56b274 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -10,6 +10,11 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## [Documentation](https://docs.rs/crate/riscv-rt)
 
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.38.0 and up. It *might*
+compile with older versions but that may change in any new patch release.
+
 ## License
 
 Copyright 2018 [RISC-V team][team]

From 642ef2944e431e2a40b14fdcf1de8d19f29c15a6 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 Apr 2020 00:05:17 +0300
Subject: [PATCH 131/234] Update CI scripts

---
 riscv-rt/.travis.yml   |  9 ++-------
 riscv-rt/ci/install.sh | 16 +++++++---------
 riscv-rt/ci/script.sh  | 27 +++++++++++++--------------
 3 files changed, 22 insertions(+), 30 deletions(-)
 mode change 100644 => 100755 riscv-rt/ci/install.sh
 mode change 100644 => 100755 riscv-rt/ci/script.sh

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index c911f7d8..fac3944e 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -13,16 +13,11 @@ env:
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
-before_install: set -e
-
 install:
-  - bash ci/install.sh
-  - export PATH="$PATH:$PWD/gcc/bin"
+  - ci/install.sh
 
 script:
-  - bash ci/script.sh
-
-after_script: set +e
+  - ci/script.sh
 
 cache: cargo
 
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
old mode 100644
new mode 100755
index fa989702..b8beed22
--- a/riscv-rt/ci/install.sh
+++ b/riscv-rt/ci/install.sh
@@ -1,12 +1,10 @@
-set -euxo pipefail
+#!/usr/bin/env bash
 
-main() {
-    if [ $TARGET != x86_64-unknown-linux-gnu ]; then
-        rustup target add $TARGET
-    fi
+set -euxo pipefail
 
-    mkdir gcc
-    curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
-}
+if [ $TARGET != x86_64-unknown-linux-gnu ]; then
+    rustup target add $TARGET
+fi
 
-main
+mkdir gcc
+curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
old mode 100644
new mode 100755
index fea3bb89..561440e8
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -1,18 +1,17 @@
-set -euxo pipefail
+#!/usr/bin/env bash
 
-main() {
-    cargo check --target $TARGET
-    if [[ $TARGET == riscv* ]]; then
-        cargo check --target $TARGET --examples
-    fi
+set -euxo pipefail
 
-    if [ $TRAVIS_RUST_VERSION = nightly ]; then
-        cargo check --target $TARGET --features 'inline-asm'
-    fi
+cargo check --target $TARGET
+if [[ $TARGET == riscv* ]]; then
+    cargo check --target $TARGET --examples
+fi
 
-    if [ $TARGET = x86_64-unknown-linux-gnu ]; then
-        ./check-blobs.sh
-    fi
-}
+if [ $TRAVIS_RUST_VERSION = nightly ]; then
+    cargo check --target $TARGET --features 'inline-asm'
+fi
 
-main
+if [ $TARGET = x86_64-unknown-linux-gnu ]; then
+    PATH="$PATH:$PWD/gcc/bin"
+    ./check-blobs.sh
+fi

From 9c492da0ecba934eb310e5b6546eb7faabfe1f3d Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 Apr 2020 00:06:15 +0300
Subject: [PATCH 132/234] Allow nightly build to fail

---
 riscv-rt/.travis.yml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index fac3944e..9c9cb8a6 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -13,6 +13,10 @@ env:
 
 if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
+matrix:
+  allow_failures:
+    - rust: nightly
+
 install:
   - ci/install.sh
 

From 4ea6ec401931b99fd7e1bddd5e4453b1151596e3 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 Apr 2020 00:11:52 +0300
Subject: [PATCH 133/234] Check blobs in a separate target

---
 riscv-rt/.travis.yml   |  6 ++++++
 riscv-rt/ci/install.sh | 10 +++++++---
 riscv-rt/ci/script.sh  | 17 ++++++++++-------
 3 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 9c9cb8a6..4a9348ed 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -16,6 +16,12 @@ if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_req
 matrix:
   allow_failures:
     - rust: nightly
+  include:
+    - env: CHECK_BLOBS=1
+      rust:
+      language: bash
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
 
 install:
   - ci/install.sh
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
index b8beed22..2a475e2c 100755
--- a/riscv-rt/ci/install.sh
+++ b/riscv-rt/ci/install.sh
@@ -2,9 +2,13 @@
 
 set -euxo pipefail
 
-if [ $TARGET != x86_64-unknown-linux-gnu ]; then
+if [ -n "${TARGET:-}" ]; then
     rustup target add $TARGET
 fi
 
-mkdir gcc
-curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
+if [ -n "${CHECK_BLOBS:-}" ]; then
+    if [ ! -d gcc/bin ]; then
+        mkdir gcc
+        curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
+    fi
+fi
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index 561440e8..590797d8 100755
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -2,16 +2,19 @@
 
 set -euxo pipefail
 
-cargo check --target $TARGET
-if [[ $TARGET == riscv* ]]; then
-    cargo check --target $TARGET --examples
-fi
+if [ -n "${TARGET:-}" ]; then
+    cargo check --target $TARGET
+
+    if [[ $TARGET == riscv* ]]; then
+        cargo check --target $TARGET --examples
+    fi
 
-if [ $TRAVIS_RUST_VERSION = nightly ]; then
-    cargo check --target $TARGET --features 'inline-asm'
+    if [ $TRAVIS_RUST_VERSION = nightly ]; then
+        cargo check --target $TARGET --features inline-asm
+    fi
 fi
 
-if [ $TARGET = x86_64-unknown-linux-gnu ]; then
+if [ -n "${CHECK_BLOBS:-}" ]; then
     PATH="$PATH:$PWD/gcc/bin"
     ./check-blobs.sh
 fi

From e8918a76444ba0ab91fb4dba07b22d44ceb43f71 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 22 Apr 2020 00:13:31 +0300
Subject: [PATCH 134/234] Enable gcc caching

---
 riscv-rt/.travis.yml   | 5 ++++-
 riscv-rt/ci/install.sh | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index 4a9348ed..cb0673df 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -29,7 +29,10 @@ install:
 script:
   - ci/script.sh
 
-cache: cargo
+cache:
+  cargo: true
+  directories:
+    - gcc
 
 branches:
   only:
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
index 2a475e2c..0130ccd8 100755
--- a/riscv-rt/ci/install.sh
+++ b/riscv-rt/ci/install.sh
@@ -8,7 +8,7 @@ fi
 
 if [ -n "${CHECK_BLOBS:-}" ]; then
     if [ ! -d gcc/bin ]; then
-        mkdir gcc
+        mkdir -p gcc
         curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
     fi
 fi

From b67cb52045e994fb845221a5e72830dd334e32b0 Mon Sep 17 00:00:00 2001
From: Ilya Epifanov <elijah.epifanov@gmail.com>
Date: Fri, 15 May 2020 22:51:38 +0200
Subject: [PATCH 135/234] Only checking for necessary extensions when linking,
 made debug information location-independent

---
 riscv-rt/Cargo.toml                           |   3 +++
 riscv-rt/assemble.ps1                         |  16 +++++++---------
 riscv-rt/assemble.sh                          |  16 +++++++---------
 riscv-rt/bin/riscv32i-unknown-none-elf.a      | Bin 7994 -> 7954 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a     | Bin 0 -> 7814 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a     | Bin 0 -> 7642 bytes
 riscv-rt/bin/riscv32imac-unknown-none-elf.a   | Bin 7558 -> 0 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a    | Bin 7558 -> 7510 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a      | Bin 0 -> 12882 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a     | Bin 0 -> 12738 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a     | Bin 0 -> 12370 bytes
 riscv-rt/bin/riscv64imac-unknown-none-elf.a   | Bin 12306 -> 0 bytes
 ...ne-elf.a => riscv64imc-unknown-none-elf.a} | Bin 12306 -> 12250 bytes
 riscv-rt/build.rs                             |   8 ++++++++
 14 files changed, 25 insertions(+), 18 deletions(-)
 create mode 100644 riscv-rt/bin/riscv32ic-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32im-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imac-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64i-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64ic-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64im-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imac-unknown-none-elf.a
 rename riscv-rt/bin/{riscv64gc-unknown-none-elf.a => riscv64imc-unknown-none-elf.a} (75%)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 62ff8bce..1daf8799 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -18,3 +18,6 @@ inline-asm = ["riscv/inline-asm"]
 
 [dev-dependencies]
 panic-halt = "0.2.0"
+
+[build-dependencies]
+riscv-target = "0.1.2"
diff --git a/riscv-rt/assemble.ps1 b/riscv-rt/assemble.ps1
index 942a1f03..9e615050 100644
--- a/riscv-rt/assemble.ps1
+++ b/riscv-rt/assemble.ps1
@@ -2,16 +2,14 @@
 Remove-Item -Force bin/*.a
 
 $crate = "riscv-rt"
+$extension_sets = @("i", "im", "ic", "imc")
 
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+foreach ($ext in $extension_sets) {
+    riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32$ext asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
 
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64$ext asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
+}
 
 Remove-Item bin/$crate.o
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index a4827638..997d9ae8 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -7,15 +7,13 @@ crate=riscv-rt
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+for ext in i ic im imc
+do
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32 -march=rv32${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf.a bin/$crate.o
 
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
-
-riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
-riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64 -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
+done
 
 rm bin/$crate.o
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 2d44739deb305fe0002266d077eb683218076d2e..861d6413f927de661fd5853a048f784591adfdfd 100644
GIT binary patch
delta 170
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z@w~x&j3tvdOV4L)m>ewQ&$wgqVjy{B@@F8~G1*zRobkfs-Ll$@GLxUnDl@K_%q^$R
z=rP$CNM4v64J0Q_ZkAJL`ol7Ljhq^z#N^9B&I{hjf8^98wn#ECoPyd1q8OoU00Idx
Ag#Z8m

delta 208
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sxG|92F*#aJok@jta*LcAqr>FYK#l<4<STM&5_cpS7)~)D03(zM0EZ(#e*gdg

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
new file mode 100644
index 0000000000000000000000000000000000000000..77d72b1b1af2454811f95c33e41d15cee94fca86
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32imac-unknown-none-elf.a b/riscv-rt/bin/riscv32imac-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imac-unknown-none-elf.a b/riscv-rt/bin/riscv64imac-unknown-none-elf.a
deleted file mode 100644
index 4939161ae844773118ea830cfffde53cfe0f9742..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/riscv-rt/bin/riscv64gc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
similarity index 75%
rename from riscv-rt/bin/riscv64gc-unknown-none-elf.a
rename to riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 4939161ae844773118ea830cfffde53cfe0f9742..87327eb93a9032b466f09fd7ee9376fc215fffb1 100644
GIT binary patch
delta 203
zcmbP~a4UYo0%ijXgNcjvnLcQ2yu!;OQj}SoT&7!8!r<-~s^A!`V5DbkGFg>1mXUdK
zGpmM_G6MqxSP288B#_BkRAy$9X;fekpF8;!tLEl!tXsGk1tu?K5#GE{V2vbW!sKkN
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zxnS~YJ$t4b>XYB-*|A?>0ougCFxik@e6okW64MWs$vOIVOcw+vuhF+-RG9o)UmXC;
CHbB(?

delta 257
zcmcZ=KPh3t0%k*Fvx$rKnKU#vUg2d?&&bbB)lbPRPAtyVPf0D)FDflA(NE1yN=->g
zP0=sUFUl@1NK8(h{D4J-(})2ICVyp#Wn`Qj%&MWT0Te3AEKV+CV3Y$gS&PcdOfroM
z4B~S^L?Vbt1`?AOvZ!p{$GU}!(E`X6-rOdzMv`&HWMi%Wj2k8!Yu7U=h)&+3T?dpk
z)~RP=P@B9(XCLE)$;G<vla2VqCSTB1Vr-cFS=Sy&8td6JUYK00XU`;{F?oxg9VY`T
l#95k?f9shu8L&<^(YIsb5Sm<~Z^sz{avu<!np~|V4*;MqOZWf)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index be724270..59356346 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,4 +1,7 @@
 // NOTE: Adapted from cortex-m/build.rs
+extern crate riscv_target;
+
+use riscv_target::Target;
 use std::env;
 use std::fs;
 use std::io::Write;
@@ -10,6 +13,11 @@ fn main() {
     let name = env::var("CARGO_PKG_NAME").unwrap();
 
     if target.starts_with("riscv") {
+        let mut target = Target::from_target_str(&target);
+        target.retain_extensions("imc");
+
+        let target = target.to_string();    
+
         fs::copy(
             format!("bin/{}.a", target),
             out_dir.join(format!("lib{}.a", name)),

From 12fb268f1281a3e4d5b1f874ad276cc33ea54c43 Mon Sep 17 00:00:00 2001
From: Ilya Epifanov <elijah.epifanov@gmail.com>
Date: Fri, 15 May 2020 23:14:15 +0200
Subject: [PATCH 136/234] =?UTF-8?q?fixed=20the=20assemble.ps1=20PowerShell?=
 =?UTF-8?q?=E2=84=A2=20script?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 riscv-rt/assemble.ps1 | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/assemble.ps1 b/riscv-rt/assemble.ps1
index 9e615050..389014a7 100644
--- a/riscv-rt/assemble.ps1
+++ b/riscv-rt/assemble.ps1
@@ -3,12 +3,13 @@ Remove-Item -Force bin/*.a
 
 $crate = "riscv-rt"
 $extension_sets = @("i", "im", "ic", "imc")
+$pwd = Get-Location
 
 foreach ($ext in $extension_sets) {
-    riscv64-unknown-elf-gcc -ggdb3 -c -mabi=ilp32 -march=rv32$ext asm.S -o bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c -mabi=ilp32 -march=rv32$ext asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
 
-    riscv64-unknown-elf-gcc -ggdb3 -c -mabi=lp64 -march=rv64$ext asm.S -o bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c -mabi=lp64 -march=rv64$ext asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
 }
 

From c255c0c67e334f416083d8b5842965c0d03932f7 Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Sat, 16 May 2020 11:12:42 -0600
Subject: [PATCH 137/234] fix rust fmt to not mangle externs

---
 riscv-rt/build.rs               |  5 +++--
 riscv-rt/examples/empty.rs      |  2 +-
 riscv-rt/examples/multi_core.rs |  5 +++--
 riscv-rt/src/lib.rs             | 35 +++++++++++++++++++++++----------
 4 files changed, 32 insertions(+), 15 deletions(-)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 59356346..dff0f3e3 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -16,12 +16,13 @@ fn main() {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imc");
 
-        let target = target.to_string();    
+        let target = target.to_string();
 
         fs::copy(
             format!("bin/{}.a", target),
             out_dir.join(format!("lib{}.a", name)),
-        ).unwrap();
+        )
+        .unwrap();
 
         println!("cargo:rustc-link-lib=static={}", name);
         println!("cargo:rustc-link-search={}", out_dir.display());
diff --git a/riscv-rt/examples/empty.rs b/riscv-rt/examples/empty.rs
index 5699d6f4..5e4d2384 100644
--- a/riscv-rt/examples/empty.rs
+++ b/riscv-rt/examples/empty.rs
@@ -9,5 +9,5 @@ use riscv_rt::entry;
 #[entry]
 fn main() -> ! {
     // do something here
-    loop { }
+    loop {}
 }
diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs
index de34e8ec..efff6b04 100644
--- a/riscv-rt/examples/multi_core.rs
+++ b/riscv-rt/examples/multi_core.rs
@@ -5,11 +5,12 @@ extern crate panic_halt;
 extern crate riscv;
 extern crate riscv_rt;
 
-use riscv::register::{mie, mip, mhartid};
 use riscv::asm::wfi;
+use riscv::register::{mhartid, mie, mip};
 use riscv_rt::entry;
 
 #[export_name = "_mp_hook"]
+#[rustfmt::skip]
 pub extern "Rust" fn user_mp_hook() -> bool {
     let hartid = mhartid::read();
     if hartid == 0 {
@@ -52,5 +53,5 @@ fn main() -> ! {
         }
     }
 
-    loop { }
+    loop {}
 }
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 7985c957..850b5832 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -330,9 +330,9 @@
 #![no_std]
 #![deny(missing_docs)]
 
+extern crate r0;
 extern crate riscv;
 extern crate riscv_rt_macros as macros;
-extern crate r0;
 
 pub use macros::{entry, pre_init};
 
@@ -355,7 +355,6 @@ extern "C" {
     static _sidata: u32;
 }
 
-
 /// Rust entry point (_start_rust)
 ///
 /// Zeros bss section, initializes data section and calls main. This function
@@ -363,6 +362,7 @@ extern "C" {
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
 pub unsafe extern "C" fn start_rust() -> ! {
+    #[rustfmt::skip]
     extern "Rust" {
         // This symbol will be provided by the user via `#[entry]`
         fn main() -> !;
@@ -407,7 +407,6 @@ pub struct TrapFrame {
     pub a7: usize,
 }
 
-
 /// Trap entry point rust (_start_trap_rust)
 ///
 /// `mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
@@ -501,25 +500,41 @@ pub union Vector {
 #[no_mangle]
 pub static __INTERRUPTS: [Vector; 12] = [
     Vector { handler: UserSoft },
-    Vector { handler: SupervisorSoft },
+    Vector {
+        handler: SupervisorSoft,
+    },
     Vector { reserved: 0 },
-    Vector { handler: MachineSoft },
+    Vector {
+        handler: MachineSoft,
+    },
     Vector { handler: UserTimer },
-    Vector { handler: SupervisorTimer },
+    Vector {
+        handler: SupervisorTimer,
+    },
     Vector { reserved: 0 },
-    Vector { handler: MachineTimer },
-    Vector { handler: UserExternal },
-    Vector { handler: SupervisorExternal },
+    Vector {
+        handler: MachineTimer,
+    },
+    Vector {
+        handler: UserExternal,
+    },
+    Vector {
+        handler: SupervisorExternal,
+    },
     Vector { reserved: 0 },
-    Vector { handler: MachineExternal },
+    Vector {
+        handler: MachineExternal,
+    },
 ];
 
 #[doc(hidden)]
 #[no_mangle]
+#[rustfmt::skip]
 pub unsafe extern "Rust" fn default_pre_init() {}
 
 #[doc(hidden)]
 #[no_mangle]
+#[rustfmt::skip]
 pub extern "Rust" fn default_mp_hook() -> bool {
     use riscv::register::mhartid;
     match mhartid::read() {

From ef768fbd97968c1ac49aa9fc487734cb18c12673 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 17 May 2020 08:26:27 +0300
Subject: [PATCH 138/234] Check code style on CI

---
 riscv-rt/.travis.yml   | 3 +++
 riscv-rt/ci/install.sh | 4 ++++
 riscv-rt/ci/script.sh  | 4 ++++
 3 files changed, 11 insertions(+)

diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
index cb0673df..0cd5a417 100644
--- a/riscv-rt/.travis.yml
+++ b/riscv-rt/.travis.yml
@@ -21,6 +21,9 @@ matrix:
       rust:
       language: bash
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+    - env: RUSTFMT=1
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
 
 install:
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
index 0130ccd8..2378704d 100755
--- a/riscv-rt/ci/install.sh
+++ b/riscv-rt/ci/install.sh
@@ -12,3 +12,7 @@ if [ -n "${CHECK_BLOBS:-}" ]; then
         curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
     fi
 fi
+
+if [ -n "${RUSTFMT:-}" ]; then
+    rustup component add rustfmt
+fi
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
index 590797d8..e35612e4 100755
--- a/riscv-rt/ci/script.sh
+++ b/riscv-rt/ci/script.sh
@@ -18,3 +18,7 @@ if [ -n "${CHECK_BLOBS:-}" ]; then
     PATH="$PATH:$PWD/gcc/bin"
     ./check-blobs.sh
 fi
+
+if [ -n "${RUSTFMT:-}" ]; then
+    cargo fmt -- --check
+fi

From 48cc1ec1fe9596b852efb839a9811aea25493458 Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@protonmail.com>
Date: Mon, 1 Jun 2020 10:13:51 +0000
Subject: [PATCH 139/234] Exception handler may return

---
 riscv-rt/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 850b5832..90eb68dc 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -416,7 +416,7 @@ pub struct TrapFrame {
 #[export_name = "_start_trap_rust"]
 pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     extern "C" {
-        fn ExceptionHandler(trap_frame: &TrapFrame) -> !;
+        fn ExceptionHandler(trap_frame: &TrapFrame);
         fn DefaultHandler();
     }
 

From 763876165563bd12fc5eab2dc0b144c6de2696ca Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@protonmail.com>
Date: Mon, 1 Jun 2020 20:51:23 +0000
Subject: [PATCH 140/234] Surround use of absolute offset with "norelax"

This prevents an unsupported `R_RISCV_ALIGN` relocation from being
generated by disabling link-time relaxing for the appropriate part.

Fixes #55.
---
 riscv-rt/asm.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 2580bd3a..6bf78b10 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -30,6 +30,8 @@ _start:
 
     // for 64bit
     .if __riscv_xlen == 64
+.option push
+.option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
 1:
     auipc ra, %pcrel_hi(1f)
     ld ra, %pcrel_lo(1b)(ra)
@@ -37,6 +39,7 @@ _start:
     .align  3
 1:
     .dword _abs_start
+.option pop
     .endif
 
 _abs_start:

From ced1ad478279b8830beb77eff4c88c22655879a9 Mon Sep 17 00:00:00 2001
From: "Wladimir J. van der Laan" <laanwj@protonmail.com>
Date: Mon, 1 Jun 2020 20:58:22 +0000
Subject: [PATCH 141/234] Regenerate binaries

---
 riscv-rt/bin/riscv32i-unknown-none-elf.a   | Bin 7954 -> 7954 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a  | Bin 7814 -> 7814 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a  | Bin 7642 -> 7642 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a | Bin 7510 -> 7510 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a   | Bin 12882 -> 12810 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a  | Bin 12738 -> 12666 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a  | Bin 12370 -> 12298 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a | Bin 12250 -> 12178 bytes
 8 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 861d6413f927de661fd5853a048f784591adfdfd..5898b7db0bb47474d0c3b3a9d6c301e794ec4f28 100644
GIT binary patch
delta 103
zcmbPaH_2{-1ec+yrJ;d|sj;!iM5P!x1W!T1(7?a|i8M1a**NDXBcteKdzS3UADI1s
pm}hb{b3IcV<K+2FNt5kZS{b)aKEl$$Xf)ZE)s&HOb2DqdBmi-@9I*fZ

delta 103
zcmbPaH_2{-1ebvV3`|stkwfql6d-H}X=Y*qRJL)>Pew+e$@VPSlRq%~0Wr_yXy$sR
iX2!|$nUW^kv9vO7ntX(%gVAKNFRLjd^X6vOen|k=lp3)B

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 77d72b1b1af2454811f95c33e41d15cee94fca86..ee7f532ee015f0bb3df82216acb39f2ae15dd274 100644
GIT binary patch
delta 103
zcmZp(ZL^&q!DVP_X=q?#YHVyWQ7J|a!BbE$G%zqgBF)T9HqOarWE7pekvV(v17@4a
r4a{<r&ob3BwJ}Z>WJ;R6fw`4&>tr*QHb$e#ds$2w88?4snJftaQ*<1l

delta 103
zcmZp(ZL^&q!DXNT0~3{E<Pbas1qd5LnwgjYm2I4p&B!P;c_VZ7<Oj?)lN*@jCZA=h
kXKH4gEXb5Jc>{AR<EF`GENzS?llQWiGBR)e%raRL0J%{bpa1{>

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 845b829a75356dc562bc88d2a05db5aa7efce949..466d6d4237c13d5f42c7e3a5a00f5a8446b8c32b 100644
GIT binary patch
delta 122
zcmca*eam`+1ec+yrJ;d|sj;!iM5P!x1W!T1(7?a|i8M1a**NDZBcteKMi%kOHY_%i
z4Ol!TUtrdn?9QCX+Q!Jp%rx1M#eH%Di}GY{7GAK51QtWat&=CQbTJxDmSr_%WZWFg
H+AaYANDCf1

delta 122
zcmca*eam`+1ebvV3`|stkwfql6d-H}X=Y*qRJL)>Q$|Li$&4)GlWkaRCL6GLOuoRZ
zHQAjxk+qqTk(p_-A&dLu1QzAV+$_9c6$vbcjGHD;V(DTunJmj{%E-Jqn6+I30Egim
AIsgCw

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 7942db62a09e9a12b7756c8aaeeca1ec94ebb36e..0d7b051285c7a79f9deecb58ca59e839042a0b7d 100644
GIT binary patch
delta 128
zcmca+b<Jvm1ec+yrJ;d|sj;!iM5P!x1W!T1(7?a|i8M1a**GVWkx_K>KSni1);2~)
zW~RvtnS&=gF!N02WCGy?Am*O@pP7$w>tsHbHZCIu5cm%SlM5wPI7Pr*1_s8>r&+os
E0PPGPrT_o{

delta 128
zcmca+b<Jvm1ebvV3`|stkwfql6d-H}X=Y*qRJL(WA|s>F=6{T8jI7O!jLb}v7cvJ=
yc3|e2%*h182|&y}`9Cus<EF`cENxsS3?T3y2qqUws&I;cxeN@<n@_WJO8@{MtsSNS

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index f72359535d7c0a5694aeb6a77af134409dd87a00..ef6e4e75936417b3b22a5a4260fc29fbf3ddccbe 100644
GIT binary patch
delta 216
zcmcbV(v>nng3Hj<($K)f)Y#Z$qEd`1f~TNhXkcJ~M4FkI0C`4cCI%B1>oY1$ysXX0
zu<`#!Mge6;W=2j11{ldbIgv$t@*EbM$rD&SCL6G5O>SjwW^H3+WM-N?k;Q%T0T$)S
z*(|(Z6$e;M8MjXU#<GslX!26lSVqRp%xwL9lUIpIOwQ8c+5Asriv(lD<juO}j2e@*
t_39ZNCa>13XZoQ&Sx0{#W5?vz`uiCxCa*TAXXKcyZTO!tV6wK6Isi(sJ!Sv^

delta 272
zcmeB5xs)<Ng3CYw1|}-Ss3Ld@3J^AgG&3;)D>F1QH#C~KSf4Rt;$>|{;f?<{G72a%
zGBa{AFu+Kz$%!oDljpG5OrF5vG1-7cYjP`dGix&=BQw+Fi7f7u53ndt&Sv2St2n@7
z%D8FrH<opbCX<)4#xgQ*W@hW>n;gT+!D`F^1e4oElr>pEEFb`jK$u{X2g=rl(kz=7
ziyW6=TrfFXx16zH@?+h4#*WF!di6{W8k3*s?PI(!d9nU}#sia+4eA*KCO<a#&pAU2
LqV?3|)jIM3s1rZ2

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index b7566b631ffca718d32d385d43ce4e3c28c179c3..5316a51930b96f71a18852498c20fb5d739142b5 100644
GIT binary patch
delta 196
zcmX?<{3~gK1ec+yrJ;d|sj;!iM5P#21W!T1(7?a|i8M1a0rHGYEX^h^)@PhB@v<f}
z0|Udx|Ei1v%8bm6oD2*wl6&$)=IqG=EH;xjFw0H;$<)l)Ho2Dh4dd3ySuCp<jV6n-
z#xgQ)E@tiLn=B<FG5MAz&*nUlEfS0ola+PL8D~tMty|ByVY0MdJ!8h?*?Rk#eyC55
c(cj1PLSwRwK^<eo<k<%QnGR@9o@1y60C<f!>;M1&

delta 251
zcmeyBbSQa(1ebvV3`|stQAO|+6d-H}X=Y*qR%U2qYGyHUu|DICiI+8*85x8({#Rub
zP-J9g<YZugkzA7>GG|W~V6mCJfmv?yPo`$Z=E=3pZx}aC&SF``Xfj!pHI|Wib1`c_
z-{dna9IVC+Krs2cu(Bo#hy?^-5eO4ZazWYJP?~MCu*h)<#s!ma>y$G-m>jHI&-i2V
rWgxj>a<JZhCI^klBKrH73^XTS(XV4XFge)ZKPQJ4MDMA|(mL`0=L<Ox

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 5fa5574397f1ada301c441a2d54a62c8ff798ae3..8038388674b031cf8db21a1211cb0552d864cb12 100644
GIT binary patch
delta 193
zcmcbV(3LPjg3Hj<($K)f)Y#Z$qEd`1f~TNhXkcJ~M4FkI0C`4+Mivtn>oY1$ysXX0
zu<`#wMge6;W=2j11{le`c>|LcBWoKYBQw+FK$ghKADG!D+p%;qZk>FBWeuaz<WkmH
zM#jyTS?}{sJ|!$MIZK0Qvz*8jaYl{Fo3+asB_?a@)H51PUaeEl^h0&Bj_y9jj>)fe
Y_cK;ZUaeQp$T3-4|372EWNia=01?796951J

delta 249
zcmeB5xRfwKg3CYw1|}-Ss3Ld@3J^AgG&3;)D>F1QGBB99Sf4Rt;$>|{;f?<nG72a%
zGBa{AFu+Kz%^R4s7+ISc8JU?T2eL#?{=m#O*^Z@?ans}zENd7|CYQ3tGBR(z%zB@9
zvJNW;t1$x*OkOUmtjPjm0RdP9!UU5%P_{OdX4!mLc)2)Z!Q^c1a>j(okG1O=D<&uF
r)H6A#O@5-YkMY9f#k%_$4@^$ht7i<D{8;Zl=L`*q)>D&LYsmuuB=I;T

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 87327eb93a9032b466f09fd7ee9376fc215fffb1..71c9bafd97adfdabff2ed85d0d12016877fc55fc 100644
GIT binary patch
delta 226
zcmcZ=KPi5K1ec+yrJ;d|sj;!iM5P#21W!T1(7?a|i8M1a0rHFt3@j!t)@NKX@v<f}
z0|Udx|FVn%%8bm6oD2*wl6&%cX7R~6%zl$UFq=)Dz^pa-BU37C8zUn#)8s_v$jJ&U
zf|GYL^MX|<uqZQbo$SK0fzfF4SC&{t#?8U3&v_>Y2}?|tQs>#cOn8boqsC-w?Q+Hi
zlQ(PEGwl$WY@$=g*f4ps&VELL$;G<+85t%U>(w((n7mo<Kj#f~pqqf;)Z}U{c>on=
BJ%j)N

delta 267
zcmbOfe=B~11ebvV3`|stQAO|+6d-H}X=Y*qR%U2qU|}$Eu|DI6iI+8*85x8({+DGG
zP-J9g<YZugkzAA4GmB5oVfLH+f!S>G1ZJ(tADL2Fn;99InI<PPM^08?5uCh}nHQ`=
zfkl~d(_|Nx4U8s}zp}(KGH(uMea<_14GRaWF#`}x))!XRWC5{&04xGwf=MnYTN_HV
zZT1#kF3wmm`Lk9z<BQ4J+VxBfqLbff*D;=$oUOB;F=Dc|?tVs($**<m8E;I^*89(-
KpfNc|Ukv~Y`aLlK


From ff86cd05a5ef5d164a3bb930ae3336f58e4eafc2 Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 07:38:39 +0200
Subject: [PATCH 142/234] Add hook to initialize custom interrupt controllers.

---
 riscv-rt/asm.S                             |  13 +++++++------
 riscv-rt/bin/riscv32i-unknown-none-elf.a   | Bin 7954 -> 8042 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a  | Bin 7814 -> 7902 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a  | Bin 7642 -> 7730 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a | Bin 7510 -> 7598 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a   | Bin 12810 -> 12946 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a  | Bin 12666 -> 12802 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a  | Bin 12298 -> 12418 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a | Bin 12178 -> 12298 bytes
 riscv-rt/link.x                            |   6 ++++--
 riscv-rt/src/lib.rs                        |   4 ++++
 11 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 6bf78b10..f9704090 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -113,15 +113,10 @@ _abs_start:
     // Set frame pointer
     add s0, sp, zero
 
-    // Set trap handler
-    la t0, _start_trap
-    csrw mtvec, t0
-
     jal zero, _start_rust
 
     .cfi_endproc
 
-
 /*
     Trap entry point (_start_trap)
 
@@ -130,6 +125,7 @@ _abs_start:
 */
 .section .trap, "ax"
 .global _start_trap
+.weak _start_trap
 
 _start_trap:
     addi sp, sp, -16*REGBYTES
@@ -174,9 +170,14 @@ _start_trap:
     addi sp, sp, 16*REGBYTES
     mret
 
+.section .text
+default_setup_interrupts:
+    // Set trap handler
+    la t0, _start_trap
+    csrw mtvec, t0
+    ret
 
 /* Make sure there is an abort when linking */
-.section .text
 .globl abort
 abort:
     j abort
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 5898b7db0bb47474d0c3b3a9d6c301e794ec4f28..3b9842ec6c2a6867019c450fb4fe2f4098cfdf47 100644
GIT binary patch
delta 1527
zcmZ9MUu;u#6vxlG?cIiS>#bR7*LJh)F82<jQe+HeS`vLBWI!Sq9w4b@l!--F+S{ps
z7Eu%swd0VC2NK9a0uLmTlm`-DeDQ@C;msx1#KafF(*g<c#l-XboqN~0Uvkd*obNfm
zf4P4y=O5>r$>(y}V9X649O-1)tg!g;u`%7Y^|h_9&Ml1Eiz(1!O#4w7fF#Tt0Cd)X
zTJxRU^ck4@;|@Nfi<k?~EM0#>5AX_BS_R`E#*H-q$OedD@+5%JS)}X6A<Bo(_5Xkv
zQq{nl%=B}3f(&yfj?pf23x-->m`_94Zq2VL8_}3PL*S4w65rGlq<|1%RwhGoD@gr%
zn-Y;1*7kQ)THh7NHtmmW$9|fRY+UB<-WlqOSTx(4iM`1EkCx|{kfT=bo<?z50kFV?
z@&DxjJ67fIavq$=;`1C>Reyg~{>iHR+=@I4-P>Spg`gKM6c5!3HLqCp;FZZ-77mw=
z6zj*lLapT0D}|%Sy;8MWuXr_D=-W?b)S`d;dY<>H#Y&-CuX+AziEk+vU6)FJDtVa0
zX1}C1iCv(P=)|V4MQU<LekOdCL+X5ogIU*DN}s1@G%;{ds<$}=)jQ0|2K^LGG`^AQ
z-4)e)%xPa&9L&1O9J|1d$9*>Ij3R(v*sRYr!Xk&*C1Ld}V&4gG;DBAiWn_L+xN9H3
zqd3*NWc?a`Yl;iQ(^63EY!jYUdcMPsKl!xMw~MaW$+xb>$3u-tUUS%gvWlIe^c0kS
zxWmqra7pQ<4m*BNS?NbaSM2ybGfF=yx?;!gQTM}>(9jk2Rp2RUQqK@i3->GjNI0qZ
zW8sWq|Mk-gRYccwPYA2IcD2K<uj_ScqG#0pwihG-u3yNqgmuwJIM}ltc744^^?V?@
zzCc-6AL5v>zQBjVdgJ55`T{e|akebm>uNO~db5evWGaRHy-%lY^Ijjo8}xnJ#vRm3
zyX=2YyQX?y+SHw~%_Xk)(8i37BeXZ;;y-jM<C^#R5qort>tQ}mn;vrgC3?#BKPf%v
z;%<7I{d-g%bdAvgx-#fslYV6BF8#&+2CW@(agjE&|C<gBxklKeFNd6$vnIe2pEbez
jf5jGNQy1ocBZSz3VezRJ=(iy|8R0+lgFxoU2h-y}z#G88

delta 1437
zcmZ9MT}TvB6vxk<-6_{b-6d;BcUM<eW{MtMb2CfJh#rKZAR>AQ)a=VFEq6=%+=^1m
z9<&n_)sqB8MFnf%TMzXVVL~rKLOldY6co{0Q0L5<ZCx+SxxfGa+<Wf5duR6R`s?dQ
z&BD4>YwF^ORrU3WvFhD5ITel8#pCfgv7sRmjjmqZm>3&hw)lKGI4$ACWl#p@*!Rck
zH{Mop|4j`5FKUn+-5&4#@$n~4sT=B0rc>Lksysdb<xx)5IMM@3flhM(Jc9~1c#q&c
ztpmrsW!iIvZ@o=epl>N$>8$jZ8eRz1_(~l~Q!^v_FHhAcR|4o@5PzPhXESMEw}uam
zQZ<V$MkPM+72-i-DXFy4qP+ORsQu5iMZM}8J}s!k9-k2iP^sxT<%0O3Xj{7VzXRZ>
zMI(6{pmv^a&eIAu=4pU!^K^TjUI>TtG-xn@kBX!Cxp?P_RA0wYXiKI#`ciFu$CIfn
zvoD4_H!y@ZN}B2}iyWoSJS}{Sy7Ivs*9*d3>O+Iq{lT(faUM{YO+F?z&tTjiOka`g
zvpLxb;*jezXJ@@94ql}|jXCSj5SwS&1z^tl_lN^S>;g>E<3HyhykSlYH}G`_Mnv$<
z1g;4$r%o*p?pMSu!tM07slAyu{weRqedJd+iO+1U74Bx=y*6gc9n;JHJ{iMoHD_j)
zG<ecmsb=*a@tLg-;T`OE=Gbz_>|%ev_{^3&ri=Xp;xk)&h4~n2K-geDDePxH1@cqy
zXQ7Tu!el-n9A@qpb_(?fJCl2bd2Z}zj&0X>>KqfF>%{tUY`cDx*H=kN)bOBGj&0X3
zAWIz--#I~-u(OFn!p;G@g`I^D3p)omA{?b|4Hu*4thJ6HbH6;O_(KlG^i(l`fnP!~
z)rgD2HpTj|tvAxBS!@f(^z)Q&#G!CZMez~kC-EKSC+ISJ@Gs?Gl>od#I}%gXxH)30
zVN6oogm)<J!j}<Sn>O)V#G=IF3R^wECW@`tNpTuSD2`&L!q)zHai+p5GIja`q3s4~
d{YzL<8PaEq0IpzdWz3u?19(k-w$T=x_7B2D$I$=)

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index ee7f532ee015f0bb3df82216acb39f2ae15dd274..40f667c2a2f4c4973926e80bb230cefb61002423 100644
GIT binary patch
delta 1500
zcmZ9M-%Aux6vxk*-6?H#n+0vhoz)g6X6zS9nNp@f^$-;mQ3NH4=~n)zHC@e8+fB6J
zg>n|^AqeUrsE2|LdMbMBA)<N<iuw}@dJuZ*oVhb@dEnmrIp1^6{W16MUTyo{Hft_x
zOa(Sq-?6IXrBaGj-`v#XrM0wd+Bo;9p?+Ti00E$h8$bipfC=|B0GiTZc=k}^RDSMz
zpZ4$%?LjA;`L%MM@^}yji=VLrtF>}2<_3tMa}hvj3Mr<Yq!*!?s^^Fyi3YvSOfBIV
zY@*lU%@`{F4$p_MP>huKYkEwo=~<+v1)+kmOnlFjFPbvtM+294FR=pMimark<;&=0
zWCa%JePlZt6sg#-z~dDeZ;^jz*-uuP6<fp7^@aI#Xe77tK(1>+0Wd&^=Kp+v-HZGq
z><7Ctcvr_4#m_AAFD~+D{_#_=RD(I1uS}Ue=~G=J1KG~ubarI0v-ey!Jv1~jm>s4S
z(W7)RYS3iV+!()8D&FK{m`8I`Il_T1dt85m?nhg5*HrWn59VdX$9PEiA452(I>BuD
zx^STPF~@Im$0i);=a|i$r~tx&KE#~3B`QEpoFFjDZ21A<KtIJCyTKjXC2s5TLIBg;
zj4K|(EDy2UiXGv*idXZ1OBDC>E5|m)hxx5yHx$wM5Z=+vf%?-bAna^aJSuv7i5<Uq
zLiFuQ7k1i<Ms;&2w~r^S_b*x4=~6kJqW6^8=~kQ;JzZkQ&*>LkPR%Cl_&FKTdzCKi
z_&IVuyaei7%TEEvRgxh*p}0!;f?`v6OmR}!e~I2igG%>m&nuQ%Tds;t*!6X9o?%ah
zq^xge1Ba9RK#C<CQTi$#Y`I%DVb|Bom{A@Nn|FYI#oi_c6nh6atJqsu9u=E+fDA)5
zw-mQ6G8>z>SZncZO#=Ck;A_Ix8=?T)C}i2Viw;<EYPSrJTzwbk7iiqF^&ZYCqsN@{
zh2B{%4$x1_)f@Plvt%W0eQY_vH`<xB@d2Gqy4qorW|I!Sp;t*4KhY2FAJEcTSA#G$
z);gG?qwG}GP@bLL^rY6s4*JM_mgZ~S%0d|67jHPu8@Nhq>nwe`65tW-t+O#tnY#F2
D?ufLJ

delta 1538
zcmZ9M&r4KM6vxkbZzi?;F@`bEnbAf^-ZL;7a~drZC4yR|M1_>3_S;`s&QxYU1|sd3
z3+)62wUGJ)3Wi!mZCXT&D1vC!x<!ki=m!RN&b{x=G#<G3e9rfrd*}XmcRqK_bj(>R
zn>TH4jwd#?v?S*1`x^35G};`G$N%e-$wV~TnoK0-A2wF~s0Kg)NN@vagle#0{_C*u
z@(=Z*9k^=%&=mtxbGzf?-}-;j73{&`><8?_I<tg_ny7k1dTxLSejWp0&LBN8$EeB}
zq}9G^<0(?7Z+hiM$-xpEz4z6XGFK^uM`jm&zs$OOZV2E9Nk3Q?FJ!+Lj~II;l{ZwS
z3pqg#?a9SODzDb1G+m!dyFax+-&b{_K`o^l(Bns?<5XW3Q7fIx4e&!H^Y#DYAa$2@
zXLjZkfB?^0QxF4eSQc+Bh!M6G!~osP;(>y=2u2HHFkq6_mPe_#d|x0vF?b64Q|ZBp
zbpOPeRGMCtTPCc(M#UBFnQ1+4H#_Ts=KbtKGkI>&2nX4RU0vAIhna)!2?%@oNoMOJ
zcWlC*KEWKiAu2#d0xxlvIqW8cJzY*ac#}IeVNbuqY+Vu+K-kldF;`v_6<~^6(`AKl
zm0cjCSw5!9TkbX363ptvI(E21^ErMG*r|DdzZpD|?Fzj0Z9B?(eY@6$?Jb%|M0ame
z*mi5iML()*gzc@_o;67`vy11fKcsbGdr<Qp(GTa@c58Y?m))@m+iuN}=*P7#Y#-4q
z+rUZ9@=Wl&=78`N=%bKVhi7!c5|*Q9i*Unp3PDXIcgUs&k875(u~T_=TwTp`TI(`T
zOs<(t*m3nJ@G3E-bZB4~OXt~f^<tLrgx1v#hBT{1$j8Q}HZY=D{jmEM)CR_Ghl1FV
zwL&43_Z*J-zmx%#(t&UclavWNst?kOaKNABITq*x*Zkm`Hd^GGkF+-8U=!_#IDVV2
z?j)rmF@IYHz$>~RiQyf38F7riLHZK0@flUrIQW`cx!+FxHIDJyr0X>{TJ)HM=N5h9
zpo^9`?<1$y!BOh2b=J@N0N(LdgS>#N+&EOnT*BVu=2;&v>jpiljaiNSXZ^;L+4IVj
F{R379vr+&6

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 466d6d4237c13d5f42c7e3a5a00f5a8446b8c32b..b9b3987b369962488544f25653d36bd2dbe2df87 100644
GIT binary patch
delta 1431
zcmZ9LO=uHA6vt<h-P)SwqZm!Hn_%e5ZuMYO+eWMP6UAx~QLze^rqO=d+SX*_SB3OT
z1@+MS&<YBQ7Az<zMo+!=P()C)Cq+DX@Y;ij=*2htHl}u9-~8VHy?OJ7o%yuoW&L<?
zc`TYA6Xnfo3SKlyOg3IqW2J4ZjmIV)RcH@G%o;V8tzaP*WRniYV8p@F<A-CNLu}&9
zGyW5<^RTmj;VZo6xB1~*qhlL~+s+m82<J`*R7rcGRnovExuIUFN3QZe#|STBEN^9G
z0BI|HkoNN$h{(0vnL8psaq_vGTGHc?%R~z>;|gu$tQ4`>YDpOKg+_yXU*5Ijb8yeK
z8m^ZthgsJuJ_ny&+qoaq(#n5)qqN`JWO0?7Fj%aD?%t6-`mY{iJ|?qu|M`s7FY))G
zpYOqkJseyTZ(ib`S>j(@<VV>u2fG5_-O*rMdq*<UYbMg|W@aGK-DkF^QkelW4Mm<t
zUn-L}St4yFQ)a?UB?lns32q2nEmW$uQNlTRfgHhkT{K)a0+&5oLPHcC$0=y{au-<{
zhWDO8Xqck+amufqMh=YL@&-beDEMqq@CC9m1~G5o=om#`Es9PdmyM7<EBFd=gWzk#
zYjNU5#0NO?CgM0=N8XZq>ur*D?Loc#B<X_nTH@nEuPd-_uWb?fX3_=gb-6Zw+?idE
zHOo(tE?BpJ)=r@(NEfWP5bqUwYk_q;=YY_Yqzl&VoI^ryBVDj==ZNF+49i*(aiRG+
zN)rEtpC|SUP7wzMr-{RYO=7E153#kjmsqUT?3*Uouyw0WALWF_{#t+D!6Z8nMTrlP
zz6K}lY=I417q61HlWrZLgV<`Klh`^y7qPW*H?ehq)5t6Fi{e)&s^PFUi|70yh2xX0
zR5ZENgAWdlDH?BpLB&A(STSUAUFP7Oq7^k@e1X9)rJVafRSm}`FYH!zd5SaE1pTTe
z@Afj*29v7Bf5VJw@M-vlHVm$?!DCR3b^%VHZG};^L+})B7korJ4S&$S04-whd1#Cn
l?jI6kL)dEo_s>E$qROV5u{-b}q6O#igm1(l?12qf<1fn@x$gh~

delta 1459
zcmZ9M%TE(g6vof(bU;X<AS8W392nBU5MzN-o<0H#iDJZOFrt9?1_fzR62&6E7H%L%
zBQcnulIVg&V|C%4L}OT($b#rU-~uBXqlpVW_ns-G++@!Eecw6f-npIWylMK{IN{B%
ztf{XIg=?y-!;__*WhrGCm7!2*O^igshEW@?t(tsRUeM|THNq;EgAcruKjy?Qd@PFG
zj~oCv?ttjTfzZIpCVVd*inhc)$97?8SpY&4DmrAO3xoijS^%`W_*DDucqj0Qa~m!>
z+p??F`u}KPrC#D9Rj3?lN*vQ)XeA4_1kgdIKd;k^2`#J7aag8OL#WclRfAg}tm;ga
zcdlx#UzPS&i>SGF2q(6<wu&StTmx8@Q>4rN=CLJbPrNDB26@z(pQZuKbvl%$1w_&`
zK+8IPC{1TVcbWzV^rJi1z}DQ|6|te7LFkIcdWK?ML&MQnlBLgv-J3s#%ejrd8!RVi
z@?K${qRAh}oo<gW&dxMV)r|0xX3tF=r0i9;=GJ6i6Z^+;#_frZbN20;>^!mO7W<Nu
zYknm5j<7E|>CY19kFhTwdj4(ZR>^mmH`63Cn2!qL2Ih=rdfh}<!j*T#*}RJqrS`8Z
zIatF*d!=8S;-Fo#U;5qbOAgj1W(y-)JVa}j9%o;2u#-6={Szq;+BFT*?_pnZ(5~4d
z{gdoV4t6oibBHLje7!`BIZyI1@Z%_yVvrMF$(NanBo8sGh0Zgp<_pZS*X&ENW&3KK
ze)i=$=EW3Swr|M&#U)OZ$)bT2TeiP}EYZupI>9MsbrYwV)d9{htBubxs{@>4HfXAs
zi_uVf)e$5Hd>%pn#(REKU&sM);VZu>>hO!-qWITu>9T4Ot$>-aM0rDCd!SUfFdDEN
ze{yj;5Y%Vrakk@!fT=s(0B!g)V2TwiD6&L5Hd5S(y%fvwKE)|aQ0%~O6h}}iwnQFQ
zP@KVo6g%)5#RYs`Y;9R~0(8^udT9Sqx=7NO06>2FG`f<bjqYj`e;1qH>vZx@Nt<T6
HEj9iFlY*|e

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 0d7b051285c7a79f9deecb58ca59e839042a0b7d..565d84ccdfe50f1b5aea1b3764e94a5ff880a852 100644
GIT binary patch
delta 1504
zcmZ9MO>7fK6vy9Ndjr9C;wYqEuNSbq(Jrl8n$i$RKqVkhKL7!#pjCz91d{L-$cHzf
z?Zv4nAId4wlgJU8QzfKwaPM$H;!vrVN^LoSIB@GFH&A;B@6F7{G*5anzxRJL`)0;7
z{<H6wy$jB!u3~J9r8Aw4s94mj+n(-jHEehH&OM9E+e=;^00E$z9bh};!GR?UfNB<0
z76!U%bBoU}S$F@XFVIU)tUP>0vv>jr>QC?!q_#x6T|-P*^i$$X>QAJp*%BXOPtj_k
zW%C2hVl$U8t<6lW$s3z=y;U}v%6B$zR^<T__1}{B6F6UA+IZP&Z8NIwkTBKp(Z)3m
zA<ZnVO~);9$lH?KJmpf`QrU(|Q+5Z=(^sken5CuEhikkcJwZ*WEX}4pT2A*@Pp!=X
z$bt>;{VxXCw=Vvi<G6a3s~=yNKeH~rvM&Dat+)sq`ryV}g4#fN_-v(IiH4^m*m1P0
z2qU9o!!zSixiT8fOqMTRjYg-ZXC|Wx)iOuuX(mh0GS1H2&BkXwHkjnz`Bn$Qu`bL1
zphmAVd#iIgJHVY|R`w0E`-9en<5`2u1)~ec`X%Pvb#B;%WBn?#^S!75!m&Qh?EWY!
zz?cMaVwSmJ62h@Q#@trphD~<aW=<>+z9lNayX@Gc5RUOp$32>R_>$vb{j=87$%BVk
zFP+u8aIj1B*P{0}I52YuMeozPaL`+S(cY7&?%;2h&S_mZFhBVL(aTyF4&;>BJ{5gP
zq2j=dIVSqB)`bHz=A`H&S{Dw?7}*}qKviYr(xaRbo7@__rV!+bp`0q4!;Te&;0Z^X
z)rT%?R&&QS%Us{wSK-j;>O1livUyV9pNIn<WD-S|a8m1?-1$=t4vj9a8b`IRHZZ1H
zE#kapwSfzoRpE=8)du8#b+8xNd(D4@D%Mk9a9rf4en0Qqw=?`~>5sgRhiIFdqZT)-
zD6|jpym>m}`c02{%nDHCmhg94azp%;9=f5u6#-7uKdx^-Y5^Fb_JWTQ?Jk5?XO4yn
z0p6iog%E$H2i%U+U)=sptK7b(&<pV;9p|=4*Syer-=TY6fJf<x7iK1t0CT+H950|s
W|9J&_g%98k6}I@+35WW(yz>UDZMxwA

delta 1405
zcmZ9MU2F_d6vxk**=@^iYnyDkV|J^n)65W&PIbGb1VKWmuSR?YZGD!OR(E~8u=P<9
zq|`}xl86@xiI)xW=EVa|6B6Rps|N{B!V~A*JEPV~?zzAJ|DJni?%q55Z270IJJ#&B
zj%96ruA{v@H`%<eWkzMQZNBgSlk@ppHrv^r^CurINWQiJ5CC%A02aVpuwe4*3FFl-
z+KrjSeFK0l8&J5@;}3uT{e#ZqHta6H#g*7%&f=*is%%K+28a;lIRNH0MAM*2a}W7u
z6<svPjps<I$T%*c2ayiM@`uP%bN+<Xs)$0I`@4Yx(E47vR5NJMlUNe((W+PzJ*$~b
z1F;5HrPwMo=vA!sFSo{raSQ#fZlY5)ahi&+F0J^x96*AXtgp}j&VSmk&<Obo4Y2k<
zy`w@`Ltljk1BU2kZI)iwZcG$M`$wR+Q0yNq_Kuz@6lq?aWy0by8mL=dx~S*%aA%#>
zyq7z>G{fy0;Q;sPz!whv6U?bgx=1+mPcd8Pv@aa`qs;bY?UzJ^1M>WIFd!WI*O*gR
zIB^Jv{tag9ytn|up?{RQevA``9Bchmh2RR0YhK75RzXUsJ$w<dOAoB!ON71U>vMKS
z)~sj0IXDSnw?o%#7Qb_b-JoW>_<h<Jc00@2WZo?Kyk_%$?F+m6H0Q;apOQn^4Qjf?
z@7KPt8`NwP|Dg7T-CoUA++jhp++{3kP6(d?eP&4!BYJ?pJ;2kNGs1EV9BQHCn$=`E
zPY#*u3@TLY1-@EmNc*ymb8?2gz|X>Aet=v6juvjtutLRN;McH)hqSMDz;h(jOB~Ux
zHXvuqp&oopv)aG_y|+@hwEV@gkv~q;cA^_<0phgCb}&y{ZBOMCP1p$|4>Z!)Krie>
z)ebJoB2C-PI8EQUsz|A{7tQeLZKJhmCpuOK&`pDB2Z!i(+B2pb=w;f)3HqG&@F7)a
zJWNt6=l8UW^LHw7zD18YTl6mD86Q*hGvneqYHIWr4@3a^c(ZcvE^uS1_9*{gCbux&
W@Q-kT3XP8SlS`*Un|ppS6@LI;IjqJ2

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index ef6e4e75936417b3b22a5a4260fc29fbf3ddccbe..18cf85f949fc7ca3e4871601a817f44ee46f0b02 100644
GIT binary patch
delta 1786
zcmZuxUu;uV96qP*Eq2+$E$e!F9fY!ibZxiW>1YWqyNf(9Vt7z_AgC#fc8J~Bzm|fC
z9d!^G;8s2peb9_#7zrdYQsaX@xMzIeQDaCjnGdK-7!O9{3!ZcDx$6nrdHDUl^ZmZx
zcg{UI_e^K6=Vn6<$*?o3ZSU-;&%$9F+cDMMZOOV`PN!4Vd1L3TI9VNi7V0B936alS
zgrMRg6SHq7k57{7AB*&F+@{GFMpovYavlDppVCUL>>8wa>eiGBrEV9ho_$#KM3DD1
z;R{a>!@B}^S%vxtaiYR7{_*U^Ze@se<16J|>aMxHPZYY0H<adDs`09u`VseU#k3ki
zr7@^e(rE3i9;gK=?lo#|g)HN3)t~|Vz~VCgQZo!QD}1MRug+ih&mrayZHZZ(3Q_B3
z7E1DnyWUnDZU|w|CRI;ayh47nay|6m?50xdFe6l=)M<fUV=h&Hi~FFRTaQ{gx@NuO
zLRS#^g3wo)K1?>O@%_@S<9@S0l+6tuEe;hj6S+chG;`u)AvZo=94$=X*XCo`A5d{1
zuvyWV#VkLD1Ft-1<`MG{%O6QKhksu09F?DGuX4vN+`GI^CwH90T)?2yco5L^^OEM4
zz%R0V1<#n~3XB$mUPFe(3T9aR1V38wNlT>ZTcNjCEeEyzA4_fz1?GF3lK960^R5|*
z@0a*09t9&iiuN5M?52}mNjbm?Hh9X`c4|NQ%ELn1#;EsrO$>*BiOpYiNS3E0y}1t0
z_41O_lD<#U3*Jk3gIOzW%X`a*#rF7KPDomZ=h6X*ACvUCb$G7NN_<Ju53c3Q)?Q?z
zb5aAl)T_hc`2w=hc}f5Ns+tgo=X%-4D>VF!&Jrv{gZhV3n{zpN`5YcaHT|?y<rk6<
zUOj`2?VA39HMfIoJ;tuBrjJWir*}K!CNRQ!<!V?c`PURM$Eroa@Dvr8=K>zE>M6nS
zv|C{AT*9+<jh^DG(>#orrVoiKPho-iD#OUcG<uS|(GkorJc_Sl2JNZ+9D9qhCoi5z
z`_zElaT@tVnjU0-tA_6rQGxzTM16;Z<qF~*>4r-}|1ZT*M`}YqKPdLnjHwzHJKE?Z
zmO4z|Lz^WR5${a<J`dUskCE?8(*ewPny$$xe(&t1Q-~NQy@6wf=~CNq)99ruSYnil
zNYZqX7_!M;dIa-Hlg?tvijgj}WkI~73r)5)e_t-6)D`y~X||bfaHlKn`^A2}$$i{O
GZ2ccB<@yT%

delta 1653
zcmZ`(O>7fK6rNdUO&x-;iS6AL6jD-(gOlt!F?K6T)@mz3dngrfs01h?C4u5J3Hc%6
z*Cs-RhMy+=T5;e&Bn}*MT%jU*>9JA|{HUj1f_f<uk%%Cw+!M^(oeiU?9ckZt^L^iY
zZ)SFOf9Rb$GHur9wttXw^4mK*^D~<dZh13nYRWl|qu4?rFJ>Kuyfbs#Hkz_*d6fL9
z#4Kjc{QE0k!hP<<Z)l8RQez|2d!50>`9-|oKk~EQC9RLIio_V>5ss&k4cfOHkF*{<
zh&13>T?49hC$zg9y8baf(~t8G+|>_p?lnfA>$%0{jzPeEr?aL1!D~3IH+t!Ys}bB^
zyD_4(8g9mIyoj3kGivf0vWae9M<V<a&j)kCrZJnCvJ$d*d_{2s2iEPvU#m^)ZK-&&
zLeY$0){U><FVHyCS8$BAh+}z_NJVx8e*JD=7i>ipe=c<gq^{rBtx_d^JRx-#1CRP-
z0{LW5-RSV)AzV+I>F(jNkx?~`b~Z)3)(sJz#eCA>=WuJAfq|51T~?&CGB$-jk6S5&
ze}|t_wy=K-dj&??<`wJ`_A17Gdneue=~J0S)vw8zT!?on7=;URPF<=pCbs}D-E2)M
z$Zs;HcX9#G(}p#vu;DeJ{awc<!{FbeXf$uRAP-kuNLEtx0|bacuGgy=zsD+rQo30{
z9}*`=h`%T1;>9hGF-5;~8D%WQNw3y9rRe(<y~Lx85_WnI-YG{b2j%i;Eng|x5GQGm
zg7+x;BmaSuUaixo=#MITi5L8}sD;ib3CEO#5T^#c*wkWJrxdn9#<cU(*dy383Y%2e
zlc)%GTwymT>;zTjgLF^%5axyQgrcOoLn9-eA*|hISi}B2Foe>0S3DzdMTKF!5_S}W
zLOJGhfq7rXlrc)ZtgjU|>_P`|-0xCW*su$+{Z!xjMq$Is#16pD+Pur_&hF#l2jsOD
zWA_>Zt%;YdMgEESJPmx*mXXn9Tc&ZhELM9{6npd(9=DnG4`ue38kX7$yo7AK%QGmq
zyRkpym8-&QFUCsgAp0I(wio$+WNlZgZAHJ`#ZO|+cKI}(3FvYLtxgwzg0kashB?R8
yCR(r{pf8Zkx%@4Zg{@*P=cZ=mKd!naC{3UJCA`XIV@+~ZKcTauC^E|(TVDg!<nG=8

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index 5316a51930b96f71a18852498c20fb5d739142b5..f7c71346bf730775db649c660281eb76142dac5f 100644
GIT binary patch
delta 1759
zcmZuxO>7fK6rS-<z%(JdIQH7OD68-z$8lH_qPS|2H|m8_36TP)0t%#YT1Y~i*iO=)
z)W)Ti8qyZ)LjpBIK?PM6hZe~v4jg&~2_m&OkT`-wC1@*Elnb4=JKKyx-r>DB-}k+5
z#_QRAF;p8qAKQ>Iy{LB_-M+FiO}BS*UvIA?+tt&zyQhBDO2)dF6I|qer|V~N7GoEE
zjG^XZ#q$R<wJN_-|7+H_^e@Kvj`b7I+W#RXe&7SV*7%!`aOC|4uVK#rN82x)`+0~l
zF9$`B(SYrziK~H0-it`^822}d!KXof4ZjA$jUQiI@N*rDT035}#?a9m<s9!d8wt)f
zI%ir*bWX;C>>BR0TBtQg(XVY5Hb=BU`1B}}T8~^2x2(<Mdo8vlC8so}uA~gLXm3j3
zb|{AHx)$$q$RNA4B67Mtc%siF#zn7*-B-uk!iDP*|6#W#PB^+(PyeCRm1O-=>gz&p
zvURI%*=3i<n_)dRoF6$+9xDwN^QCfO@Z{-Ierl>*C>8N;_ygPwYq%AD-EWA2KlRA|
z-K(quavc-(bA|Kp)q3x-cMI(T{YP7bGpnpINsd*twpn~0cAF7Dqi9aaezU0OFd;PO
zuq5&~xF>QAFGc<qR)q3kWNXW`)a#-y;AzCz_k~2LT#!BeiDzX`<%;ZS>O0v}*&%zv
z>o^eIy1ne)9wzQK%So2X5CI~n3^y)D?}RGjQraP)kBF1u;bi`n2a0-D(c5d_q*u3`
zSM>dgUgAy8>FvfNbF``QzC0eC<)otZaPl5f@JU6VUjrxou!7Gh`jJ=higOm#Xigar
zSNi|(aN0mMI-}^lJ3&JpPI}d+iAWLjj6P*BlhOER4&Wy5Ehc&n2a-m7R$=KvQV{zw
zDuVsQS-VNKo)p*Ch)*f3H@i(>MLZO<Dr-t5{hAV5JB@f*B2<#Hr&@w7SnoO$@rGo{
zc?J`m2A`(g`6!lza!j&ROxe>e<G3f3r^$^^;HAg~7%7YIY3xlM;#|XGS2k1)yA!jx
z-<9P9;%zmMN+)G^DxC}sNXwtFn9go^F7?kj9;B!FGaTyP%fG^6cQ&*>>M9@Oes`AN
zMR=!8yptiahTnGDzG@O}R&L$#fFp+9VxVAk@G4;0zCtH{w{m<L;f(ELDICt^d@P6y
onOwvSy6!hx+)AI6ukk3;6<XfpB0nRsD;s*p{amx#NTl2U1HlsNtN;K2

delta 1657
zcmZuxZAep57(VB2E0%><=XUR971mPc+T51Q71cKSQ~gQ%fC3F^>MFJ7$E@|KS@c~_
zULwIjNuhoOjYbsx(Vsy-qTfdSEFw^fKn$Yy+<UGbq!;e{@jTD_o^$U#_YSr$By;Mj
z@Ye0&P-JUuZDe?3Q^itMULFpGLV~ZWi(s`Svb}D2B3PdD5#1>Igq|gcMpQz_^@0p9
zWTmNj$k0mpkwgd#N~AY;FqEEa{tZuP1HDxEMN@Q>#ZCydP~A(+<3%VXcI+|Cas#?8
zKcrU_x~*||Yi*}npu%>H(!w>{tS$V^)bYsnLx_z$=d~G3JP#kOj>3(idlv8&ueaDp
z9*X23m7oKC9!BM6%uxa<IkH&)k;k+WeUgpH=0qM9cwe#y4i>4}I<6R5rtrY#(sS;^
zh|0LJ<yMUk=YZ_A>@cExudXw;D{A+1T_e|Z>bjMpM9;Hacio6^!BGN}j-)lybG!@w
zI#gG4PhW3FYzts<huyPH!R!*$mnrlz6#EqTT&8Nb1Zk4zD#j~N>{RG&sB#9;A3=W?
zZldpp*XZxTSKTWv&%SZq#irlqISb=FujSDUlRROo445FsN$|Kl+8qHgb3bBNq1mNq
zg92+F0rut|z>rI!L-5q)skq7?E<0igL4Sq;Xe_i9W?k>?{b?@Uh|o^PaWnBstntMy
zTA!fbwTKd8;!H2jIWOo_f}Z0m2y56?h;Qgv(ci?k$M(`9Xic0+lLDR;^sWEFnO>Ze
z67(koJ;&?xy@-P@3JoWP1`}rsw84;9(asC(YM!$@zW`InUKH3efjtYe$et6}wE~-E
zlWCfrQ`!af)r!_FDB0Oz=EbWE`jPF?Yr`>=*(SVt;YGDVdmxQ-GVleJeL82jZ9Hck
z8Mc;oN?^@Z*n?=-SLqN~a}~yRviaI+fi)*H_6&^qf;3k6;5$U|_v7(L?OunWRiVWn
zrMvO-RN$rG%d?+;uVXJCmR}kQQ&uPJ4ydaVy!)sGt%0+21ZDzz=m2<XqV~Mg(7%C}
znkan-qcw4Q5@yhU2X`<|2{Z=d(tH&>4#sE$%plYS?oeF%=7pwEj84NS7TId}6pBf6
mR#+R3Ic5G^8(3q^W?%YENQXDubEO9I5GKM=X&Sr2mHz+-GvUbq

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 8038388674b031cf8db21a1211cb0552d864cb12..5e2b654d2a1fd424589f14cebb8628a554172756 100644
GIT binary patch
delta 1696
zcmZuxO-xfk5Z-P3kb>CO7G8@IDqyK?rBxfN;tvNCJopnug9OQ=LJ<Wm&=&A7CHR99
zqmVJt#Dj^NXykxNJs1ya;zhl1&_tpK4tnt<nwS_by7S&HuEHE<X21F7o9TPoH`+QJ
zA9EK(yu!vS4psd<dA&w%`1R4KPFu5fZFKxjr26J6GG}#qR!2O<O>US7fngI#jqQsZ
z86x9fUeF)#kS@0*XJ@{{2YQ{h=aQx!6keKDWtdX43HDl=VAh-mTP>GelMJC&LWEaX
z4zDe>P@o*6QOGDQ)SP>(3@CIORw&Ng)xs-g>VS{7au~I{)%>}gjD+fe!nZ<o871}w
zs|uNhT3Z+@7MH+~t&|DhvT4+X^034nHO_kViG37GZEjCM*HPx_MWESH4-v%z&m4!!
z;*4b{%6~HnS&ulXD?3D1c0lLO->_LQl+L;Aq{zxHu*^#qG5@cPvm;J$`D=DYyhMv1
zPHCxhyf01K6CLqPcUns&(wQFZ=!tZquP@V+PJzkU2nnYhTAcaN>vStBlemma?ppV+
zHnH%tn?+njn85$%i-+!D#0#ichT5k@8;hb76;H!+XPBOYuTIr-M&dl+c`1wMq1+Xw
z=V1@?7a`01S(s#g1ZH$^E3Vw~nDh0ilFmB`za-)KD$tNW3RA_ED;tfwL)d*L8?nS~
zI|9rwXgRgyV}5oIr&chi4Qt#4?qg?s>%uxD{w4vkC~)M<BfBMjt;FYe9>Io9xq<So
zyzFMa9`4dEaRrXl771^V_^k`z$k!yiN#e)n<5_)|R;i##4Tl%Naeyq;Ch-#zU*O1>
zb@Dg|pHV-7N4^rzfYc_gAC?DU#;1BxQWdWp8dlR_t5!W3{cJc{x|>~0)pJ~`iry-Q
zoq#0km8)LP#9xzy+pOBd5e$BwV@$#ntM+mP!v>zCav%JzR%tIzryUUXtDYmgiowfs
zoYD!JU!_M;jUIz*EboH*{xFT@-uoLU`=A8_F{{^UbPPgQAV&AI|Dy^|1Ad<U3iz!D
zx#TnigRz2}od1eKcd(zf!lz(8?Sx<`W*saxm_MN_6r&-y8`@^-@xkZNR=OK1S7%M6
w8t$!rMrWa|CQFClQ_V<Gev#3GpMYT)2nVf$OAX`>OoU_BSNy@efr&u*A3xLGg#Z8m

delta 1624
zcmZ`(OHUI~6u!4*iY=NJ+cMKgrSdE-&}peH1cStwSfdH33l=;|@hxJtE%-{Tf{Gdw
zA;-i-H%5MdiH$LFp+*;)xL~0R0xn2k;lhY9ChAJ>nYkkuqc@rJ_`dI)Gq-bZ$5J;2
zCKX$Fb8A?QZf<UlPF40+uVg-7SXEWQ#$r*HMZ%G(2deC=Cx2Fl7IhF0QKo*rpx@vr
zEqC295dvc-lAYYEroU8tMGef++qA!sHYI4a*-8jCQ_Y&tvWHMgtgKF7=BqGc{$zSg
zVWz0f%rGdHhG_&wq&`Xu@1)aG_=BP4o@!nq3;)5FV3Xu5^q1T;gUzwgERiJ`vWMW2
zMS;5(g)YHcdy*ER2-+P{J!fnge01FKmh$F~znaUKL*B9h0yYKaN*xd=Q9zZ7;B#rO
zH^E2;k^ZV7#EUpil0ru0-J)srO^5~C429HbMBV|6NHMdk*KwBWeb4a7WpCQ8`baW0
zm`!GLsZ0)bIlE)IOzI@j^JHcun=@j>bzpU0g4-Y0UKlrg8kU_hJp;G=GF)&eo=bxI
zK93dV&%#5OOvm80E5z(~W-mjXJ4DYxH?vn@LbFfYRXgAFD(rrh$LI{aS->!y<vC6{
z&tr76@XB4~85fWR9^(!s;Fnvb*FY|-s@czfX*_XlT!XHQA3<~jg=E?Mn*1Ivtz=Lf
zHGCO(Ez4sD$b7e;Z}|s~da+NBpic>Uj#~&8v=p9K3|aE+{Ppl%`US0lqqI-Jw+s5@
zKXBBGeG-CxP|$NcroD^Us81-^FBBL!4j2G?o$Sd8>{=e<&PQM?V@CznC9tO;&De~<
zmJ4haJJVx$66p}kFeP3AW8vw*<!8?j{9^2|mg@#lT-EG30U_357?zn$L((sMPHLQP
zjE{&FX`JObAh5<1{2>l%Qw|BNF$LMf*xz$RV2#em9)*hf5N$1V*6*Y2e`q=ox6ZED
zwF)c-;&eN^fHFjaeja6lerJL=`?%5+?2;Q^1{K>EUhOx*QgD<i(9^Jk4#IRp+^V{D
z{To<ph|^lw(74s~qXv2#+i3#sHRes%YN5R88N1{2O?kQodO{QHX8A|MJ9-h8LqThT
P54a9hYMgdKk6QN|giGDA

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 71c9bafd97adfdabff2ed85d0d12016877fc55fc..0fbb1165ddbc8204cbee6d1fbba851438f44c114 100644
GIT binary patch
delta 1626
zcmZuwO>7fK6rQoyA&CiI$8pvsh^z<%$0j&`!Yx#CgbL+UA|ezapc{uIKw?N@uhW#a
za^)6Etx6C+sUR+)T#Cd2B%e5;-YU3p;m|{`NL*Sd2u|V6?yNIPc+$T2=KH?)-t6q`
z4XZkSJ=WZ3dbYgd)Xue)X}Y=V_YDm>vi^bof#th>3A2Ye#>o#m*)WT<7`y3X3>6<M
zUO(1X`GMbAezoLVd5=8b);Ra?<F`VITl^TGti9w%II?~tP~qI~L(YE!rWVE{e+%;d
zFDdV8dq50tV$Aaa%5g}`qN>gCA-vH}bAN3#P!90h_+5+C+JnFPc^E;x6EmS0ZUoyo
z$Dcu?gR?Ep9@m`MH)8>I8wWyZyb89%Y}iU|o`x(G^mg0|4ak+?hV?3%^;kS9t8^!>
zxju9>bix--;Gw4BaQIY5j!2#QueW{l1`B%Bf5eR)#~t0q{hgG$b25G-^_NL+vQ6vT
zvSpXYrPgq4a%wtP%G*|P$}Y`Y=P%k*g+giGE~45xrWZ;@n^{FWSFkO+kekPUt!BWW
ze!qw#3=E3SNJor*npihYW)53NS^ZRd3A^mni%yqBJ^vOfyA6C5iN$|ZDkfweqxc=J
zk?tq_5lNGOPW}ouwWay@$dLaTXB~gDtqWVDo8#imJ^M{2VTxCgjT*d)v1r$>G551F
zx`gagPfYQ10g#Dc)mEZ^H<ph|=?;R<2u_-Zchj0aR^6r*{r)=2n1>6!Ix?^54=8$x
zH!xAKzqY!4wxRr)+@9FWq@wk3Aw8|&ql$j~Be>983VuS-=QiTg&R)h9!cqz*K7xw@
zYNIoXeoE1MxX@3av)hO-D(q&Ni<9~qM~Pih*fxbNqD-u<u-g>2Bs%lFxNrOd{vqW>
zMJaBYumn995ZZ0T=bW|c1S)JNJ@d#?hdHd0U%(tG3l8VHPh>7C7R0Rhw8DB*#6g^O
zrqG{TH*bny&x`)?nL5Xq*IBT$NGH-fQ?nAIoa?CdWSZ`^y4oeY?#b{G`ppa+OeSPj
zNhTsAve_LODd3tG#j|9r*^Id0UmX7@7x@d!roQ0kP)lW+Sk$H7;dLs*?;*7(%im#^
z{1e>YQ|4EZ>V3?Y@Upk;YfK=&_ex7+i(4Xo^9ok?rka@C-CYc(Grkd$rMo`>BF*Oo

delta 1606
zcmZuxOK1~O6n%FlNlpDE{e(&UHMD9%(q<A<n^wgZ5n3tu1x2(bwf<9WZDXyvNNu%#
z5Ny4m(uJ)RswnsiqPS5(MBL~?P;gPCq6-(g5kwdI?#!F|5Z~h7bI(2ZzB}_~-kH?-
z<bXFnwx}i+ty~n3R}PkLnfEvH`(x2)RI*i7l{{J)jSh}R{nvxcSio(af$Er#c^Qlt
z0UP|;9eMmi<LM#*_CR3_dli;bHYjmeTNk$hyC}HMfpyWgZ@<6eC0GYrb6=nV@>C~d
zpaMqJ+4g<_Rl%p~CQPXgyrrI2?gKX3YVo+O9TwtuTN6NTy*+D>T{gF#v@{!Ib~ZZ6
zn84!4@QSS{_bLCZif3lbRqbpH(=Htpoa)eF41c+j9CHaicU4Zto87~{0;7+ex&LXb
zVYr|k@8x^(j?IQ$1zTn{aD|(X@b8+#-^X2-N7YR~YpJ0#2a~nSg>JRbr3_u3EHQAa
z&~=+0Zxj~bo5Bt5Oh<D&OLk_OJ2J_RgPj>%T;zAK3SQGkPc}#6=#bRSCa{<LZv0xL
z!!ax=)_jL0&0c|La^H)qi*@M5EVsw;Hn&G`oZA!V@{q0dl&!oV^t4yMz~n4GE^!2h
zL`*Xr6`0%*HhRipeG+3GES<+miC-Wv@uzUuQ#QXvyjuRvu_cmn4H0~iOXWU$-cQM{
z71B~pB`7DB#Z&Vti{yTzq_6%DPkOn}W=Y>H=>_j#R8XC(FG)MH%fxsz%T`Hi@g!}M
z_!W{q`5&J2a-RlCzfIB$ew8tc+^9(^Xpssmo;FBHyhC7m<_z9mp!p6;S?m9yY!{C6
z>;WlD=TD2W9q0;ZzD^@Hjof)J|57zyTFP3r^ElUvZM;^_`h}7nW*-jo?0&(J6E~aT
z_u(s^ZIiOr5mV=O{2kDsjdq9as0TIQ4oT@3n0DET$)E<is2l9Ya~$u%Ye5}qa&Lp{
zfnPJ>P{NriG%LKA4kchY|3Ni;6bcITGZb{vbwcYphQo>cZlMn<*c$GF5u6Cu!!`_;
zC!7z9P2menmnZT@RU^U=4h^4_mqHItl-I&DEUU<Z8?RP828Jz>tTGV5kCFcA@1~i>
e^uzYxAwBGTZQgk7G~Uz`&UXPb{}OM8O8x-m``e8G

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index a2d48244..89ed07b8 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -22,6 +22,8 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler);
    then the function this points to will be called before the RAM is initialized. */
 PROVIDE(__pre_init = default_pre_init);
 
+PROVIDE(_setup_interrupts = default_setup_interrupts);
+
 /* # Multi-processing hook function
    fn _mp_hook() -> bool;
 
@@ -46,8 +48,8 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     . = ALIGN(4);
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
+    (*(.trap));
+    (*(.trap.rust));
 
     *(.text .text.*);
   } > REGION_TEXT
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 90eb68dc..b85a715e 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -370,6 +370,8 @@ pub unsafe extern "C" fn start_rust() -> ! {
         // This symbol will be provided by the user via `#[pre_init]`
         fn __pre_init();
 
+        fn _setup_interrupts();
+
         fn _mp_hook() -> bool;
     }
 
@@ -382,6 +384,8 @@ pub unsafe extern "C" fn start_rust() -> ! {
 
     // TODO: Enable FPU when available
 
+    _setup_interrupts();
+
     main();
 }
 

From f09f4549ea1c4e58a2fb5dcdd6efa4cfc287472c Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:19:02 +0200
Subject: [PATCH 143/234] Make default_setup_interrupts global

---
 riscv-rt/asm.S                             |   2 ++
 riscv-rt/bin/riscv32i-unknown-none-elf.a   | Bin 8042 -> 8070 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a  | Bin 7902 -> 7930 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a  | Bin 7730 -> 7758 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a | Bin 7598 -> 7626 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a   | Bin 12946 -> 12974 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a  | Bin 12802 -> 12830 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a  | Bin 12418 -> 12446 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a | Bin 12298 -> 12326 bytes
 9 files changed, 2 insertions(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index f9704090..997162bf 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -171,6 +171,8 @@ _start_trap:
     mret
 
 .section .text
+.global default_setup_interrupts
+
 default_setup_interrupts:
     // Set trap handler
     la t0, _start_trap
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 3b9842ec6c2a6867019c450fb4fe2f4098cfdf47..520d90a7a188049855f1e6ad808ab3a37fd10fa8 100644
GIT binary patch
delta 915
zcmZ9JJ5L)y5XWcX01G+xodnp}AWj&aJ7S9hq#%$|Q4sL~QrKr8yfLxO%Oo)k?;xS9
z3knKK6j1~n1qGh~D3EB7DAVyNnAus&#w*S3@Bg3KxqZBj?2euc4Gku2J<_cJU|<~9
zMk-%$a|LiSS^Tm{6>{#1ybDCGmcJO{%DXlCTjXDVn-}ok3d_RPj~G0fAS7QtOq9kd
z2F@llLH9ci@Uc!0t2#DK5b(J!KT)UCb$YQz+t8APjT*y5K6s}EK+4VJ^<n$R6Sn*x
z*p&ByP9N8We#`S<M<o1%C0)~i?m*qFeOV5EO760Cf>Zb>^C?b|y((8$ouL)o`(uVW
z^-eC(s3b3u!@pz#v-B7^{$W(I*T~UBnKnboeaZpcV3;L^@IbuH{EU-z#7r+>9m@+d
zCNkcG`DBQ1-g*0aV`+x-;|&0g%bY^)ovgBxVV)*`s>+V8Ss;I!ePTz~WXYdppV-kg
z&1i{D_Dg;eMHY0IVvD(rc#Szsyw2Q3yuqv*Wtr956=qr+`(EX^_En!8`_w0v2fj8E
zah<S{MFBrJ`Y>Xv3Khq-??X$>v9As=&#X4Fz^o3i$gF<6#H<dm%xr^KjuZ{CBZEC(
F-vA-+VR`@n

delta 952
zcmZ9LK}#D!6vyA_MuSAN3rb>Aa5b_41rfC(2=<zTw5ML`A#PHwnrdPaHQLtIgSM%*
zD0}Il#~wTgM%IG|PvX%-p_hCEi=U$J&6_1Q12gmc|K`nPhus{$c$_(zdOk5`sy5#N
z0Ik^9{GKkA?P3}1OddxL>2lF7z-9HNCN8|XHqst2uo~Q4sMqTb-3ns}({EC;1z^;D
z=zQhazQ9?B08IXu0a8u*wX9>QgMhiF^`)k~-INcWWE0x^;q-~niPLtbr0zE|J8GU5
zV(vp%CCFuwZ|+_=())>%hSNABK0JU?b!*{i=QFDloT9tTKX8hDX|TWRC#tye#J)d6
zj(p{MV&9)5M;-RWzONz2j@ZAU;4fSu$JGL{?|&g1RUEKgW7qeH0PeBt`x2p!lX1+P
zBL42)=?Rhb{_1};@y@&H*=lu`czw17z)~+WjXdy{J+YN#ULe2FU`y5H$S<-dwp2}?
z{4#rDOVzZY5<Bdj5QPsM=pBfU%-zIW%u(VB^D|=gRmg)1?B(8dX4;!5HaMxgJg3B-
z&PkMk-vx!FS}>8t1`gN;u_rbqN=_;tL?u?(%M0X~<wLw@mKRuMmOo7YK5X&=d1e#5
NT5LxXhwgCS+&|@KVmkl;

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 40f667c2a2f4c4973926e80bb230cefb61002423..0b43c5ff1339105b9d2949f6010f44ed84821010 100644
GIT binary patch
delta 966
zcmZ9KO-mb56o${$sG+Un1eC;R%h1SVBYrLvT5WOFg%IdQP-vX^*{X>q@w@E^YHQVk
zFuz1*-TxrC_cwIy%J<xJhlx3G?mX{%?!7bT-g%gMoVuBuoEULTEWRM31oE;mi?zB}
zt&>-(U=&fTSH10E+REOR|Fx>ya4<2}5td)xsZ<IpFOU*#lnx4=1^-iI;AvAEy?&;N
zhMV+zXv=suDVk}j7n<~9liqC54t0#uL4#p~|2)%*sOXhyrqQ9<5hs|l4ucO?uOsu)
z*YW&ugM3bz@4<g7tuBIO*E|206h5>6LwFvK?C+SPwO?TM8J{`wzk$={+n6K249@(-
zfMAaNDmcrRg_vg%752b=robHetKgKmpCj;~j{$Lpv`?6bZjh-fjpQ=_4f^ezDuo~I
z`-EBzyL<Lq{WYo2wh+0Va1s1=DQ34Myu$u+%&wWU!TyT)%&wVJVSinGX4lMVhouh1
z_g}H#4iJ2y>R2OnGjqp?3{vfDq<&`e7wC;D;_J2B!n`)O6La49dLKSr1n-lpksKR~
zyeT+fRmXrBK<0KeYR(%!2}^wyUpK&ajL;vkA*>rP|F3@WmiW2>zI%j2VKRG^Q0Kwv
Gn}sKC#9C$m

delta 898
zcmZ9KTT2^J5Xa{<Nfl$w2Gm>>**0MVqLRc50rA}jK@fatr0Hs{cN3FnVzgZaFNwAi
zIUm4}AZ6dB_!auzeuX~wsWWFzXqtiD`ThSh=j^%cpShoN&CK*v+SKvB2LL?y?6;m=
zscaX^V6W!!%_3JW+6DO5c=Cuxcix-s@&&OQ<S&23t^1!va1>RYEEPUT%IvE}$8H&z
z4e-Ite;Q!ELocK5)1CnWvK{r!4t?CAFWa;UU9aK3%`k{__G(G*Z(<>7-WQ@W+gI)8
zw$N9Z3=BrYpICY^O){!gjW=XGFq^t&YY9{MGxJ+aQN4ZQ)~I*LLv`5<gd#WGx!qQ!
z0}ng$J63PGT5PKxArIZk-+@r7!POe3u`}iiOvX8L6I1XDvqgL-Ge%6TxhuvGuh?*t
z0~L>>k8a@wfTgb`hy3OPk0Z9$nAgc)|Hqc@*&+WU`^1*+$&<guKCz{HUZN#v(HKrI
zzQl=Q{1uQ-nfr+=%wggx^Dwc#Uo}yIeKq!gna0NG%rJ-(+E??GlnpdbtPGA)Boew{
zB8x+1LmX3#4jh9xp?&%<1YH@1+Q1I8TEs51+Q1&O`Y>H9hT1@$*#tKpt$D?jd>G08
E1&%3PF8}}l

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index b9b3987b369962488544f25653d36bd2dbe2df87..53c1428e8c7b2840df5980a067a71dbb3290ace1 100644
GIT binary patch
delta 857
zcmZ9JJ5K^Z6oqGSMWY0kgk%9VA!49Ih>4O&p|QY13llnmu=v6U4*^9BSsrRZMKX<r
zg@uKMg}D9%Yg=0j3k!dQbN3EmWs}+aopaC3?%jQjeZ;!a=u+4xuFM1>MB=MsUg=6z
zEmw(}E%G~xbhWIOSjg_}6{aNG(>v0)Rj*IV7A?ki_Ai-?5@%oVD)Z$Z(qZ9)EfY!>
zhx%(nIx(a(Cha3*5prTO;DJ~FG$kahW-DT(&_>wD;`Th7w|k<PQ*H+N1%dEI+%*)y
zeIJf@HrcOz*`r~%%ZvL0`HmNFgRM9ePXnEMUiy2VI4dny;@wN^KAXBPoV{)K;7}rM
z?7o@0kDQ%N^xuK6k=KE5*^k3dQ@Tw~N>tTzuG$FAvM)u^wlTG8AtaDOj&q((4>%w)
zo8V{A2M&nL7Wg~p0|!LL$}L(&-v)e!3}1+zBWo@YrzqUOW#nn#3bJv~5wfxQ7#a5Z
z#jgbp3g0*<j~O_}Ul?#u_&#pYBEb>nAXLH-aIlCx&I{c|HYV6ZHeO;M*%;se*?4dc
R*%;tZPk34qt+UUW<R3I9Rnq_f

delta 906
zcmZ9K&ubGw6vyAB+Zc?*4HWXTu)4Al4?)y|U@m&G(iZXHsglh`ZT(SgOi~kbS&gx!
zx5!>{=uxBxLEH6D@a$jVy#@aP-<$W=gdLcf&-XKLW;2`pT|2IgZ!X=qW=U(D1%Ns1
zucPjEx?Z~rUUM5q4sN&Ywcu#KY^d+ySL07|K8w{5oTLlkB%Mh34=GABVIHnT0cR6?
zEtc<zCvAd)`?2*$vHU8Q-_2wT&Rl>`GlCunuGj3yO{%L`t<SAuu#(xbxGcBJGmX~;
z4V?4+;53s{!ytA3mj9j?#^mLB6XfCt_QcWN1LTr;;>aH&=RV?qjX3h(kn;nw0K}31
zfm|Gs1-L^YTKI`vk_F<(e?iU;alrNqdsg1VGVxwun6|2im(6uUHN(+DZ_a;Al>pTQ
zfFm#YHu6Q6J+V_~zDvF_Wk+h($b0OG9jSRh{t0_xM{1I&)DC<99EG<W=zmf@<^|$5
zbDp@vTqf=^>w{i0>%CjdwAYp|gt#JJpF^KDHaf@N2LFGk$byANwX}vyIN5KeToIq5
nny2jb1vZ%VkJx0^7kI|3AN-tIU*H9^1!2E1Fq9wsU0nYMxb#=z

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 565d84ccdfe50f1b5aea1b3764e94a5ff880a852..dd554a6b187c8feb26ef433e5e818cf8ff3cee32 100644
GIT binary patch
delta 924
zcmZ9K*-FDu5QgX2xS+PSSZJ*Z!AN>16+wl1qh5HU;CAKKrfzlVVp~_xxFcQ(!Iw}F
zB#+>oPv8THPvM0#XHIDCz?^*lKXXnpN#2s5$*0lLk%X=y-3kC2=3{N9$`z|r0V`9$
zl|`yjvWm`&KlYw~_K9~_(|($qm$tAQX!{lR81D8W2#pZ(1YU!fMx9Qe4k#}O0*34A
zlXZHrPN!?M4$XtGUt`b>&;Mxwkg_smHP*m%LU%s=Ip@{irE_28uG&AOklsr4*qIGP
z#Fdi`ByF1u^W>i}FX1J2S!HkU8d}}TC-(eZ<j6HH7{s2RM~<G73qb7oCFIx*xd0O+
zyuuN3w<-{O{uXlR3Kxuf%+RewFp2M-jSfSsx(^-8ny}pO&SRgQ;rc)WfVsjvj@(C2
zjX`X#GEb48s<NqiX2?&oPi(55Ir7)pCpJ}26I!CezTHmZkOh4>LDOJ_F~xyIh!WHE
z7(JMxED_{E^cpeb-aTg8Yp6ehIIetoPL6x%93v0>O-aO6K}Qw^Trm1EjiN-!apkw5
mB{tZX18g$OhuC7418g(P8)up206WY&xL?sTO<Xt&y~}^499Iwk

delta 851
zcmZ9J$w~u35QeLhxL`C31T%>Wqmc;+iYo~5;z<O>1-z&jC+=%v61Q9?YK(YO8hirJ
zism5%AH=f<AHb@vj)oNU^!NW&-P6_mnRrP&jE{{Dn>yB80KkpoxH^)#yq(R1ol4`E
zMKYhYGw^o*<QA_L)AQBX5X5Sb2i`~}<aN26C6YP<&;Wf^fpY-IM4g^S?bBWW1kBat
zSL^gqoxZHmCNy=!ZH+-cgruFy=}rb_2F=GzRDQG_Hgj3HEFXOBQR9N82d5E6b*lbr
zS@I=@ifk?7Wau9*BS){;C$6qqL+-ee-@b6<hO_%MS-M)IAWeTbQsQj3CVPh5QIhkR
zz2<Bgr=af0BEFMFe@v`Zp8YExk$MlEyPXX#9dH3y`nD#Kdy?!ETXZUnDe~79Dz<dZ
zEcrJ3#FnmEAb*p6VoTRFq9sn*cUno%(J|=4#koQV5mS2@1`d%^2%W@vX0_1)vs!z|
zOlxEMsfpv-SNqT<V$eRZG&p}Et`jCYBBN~R#VL03&vEV3^NTI^RRi11>JU53s)1c*
Y_2WHe)d0OJh6$A)qu>#aOn0sP0vHWc9smFU

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 18cf85f949fc7ca3e4871601a817f44ee46f0b02..39bb3894171e238f34ecb4154f67cef0b287c972 100644
GIT binary patch
delta 912
zcmZXSJ4_T&6o&7`T?m9^dCczRvKa6Yvp_MJkg$n`<x**5LP3EmEGoh-`+)TUt_TJ4
z5aJ(e=<JMS3KK1C?TnR)4R+dXVq>iEoS8f94W8tj^WXW-BXeh7<=*D@)9JC10b{q@
zgb)$(E!(Hcm29aZvUds;gTqv%lwCxx(|eR(kH{nMcjR50_aU~~q&uloh^XlBb0a8B
zc4hQ=|3OszXaHYb!pE*^@)qe1>OE_NLf~s>{M@x5C&&Fd`QMHkrf$;Yc~k$8>IX#2
z*|B0H;4QC%dHCCX5u?rql8%lwiWSK{WTV~q?)1r3{Bc~l&F3hSr#N<$tl?ltAs_G2
zFB*;F(C8k@&u|b|atrU{F2$b|cc2okTtkN9E~<WflW_I6HQ}?-e4EcvPbj@^(O*XM
zoxeoCQgR<-DkG=8n)=o%?|Ks#>do>VGAUQjSbfE&;BbY~H1<+T=PX*a=nOs)owewy
zMRTYVy>HPqi_W5dQ0d1OZ8us{euA4sS1jsSw2B&0{%)c58Nt1ec(PpNJC{WqQ)MYE
zqs+I>mLe}AHl%dfKL>%IvRx*x;5tnx<AmZ83RJo5vmm66=8h%arROXfZs8Yx;BTS7
e?bO08Oc!{*&Yv<N!pTevo;&=dS#ILwD*ge}JcUL8

delta 1024
zcmZ8gJ#Q015Z!fRON4~;#dg*Qkub<Y{wU5#fCLE%i6%sp(3>Ne1QZ~)4~$S8E8rCQ
z0Ai*@NKhbAC7}BOE@-H5K|zCv=;-KZVaDE#M;U47y?t+H_C9w@uSz>J=gv;1bleyc
zLJZ)#Z&tDDdlg@JHy>c`ZHj)yTNa--nuBsLI2QgmByDJ0C*f-}8T_;sLrxBxg$Rpi
z7yGFI#nD-L9y&*rya?^lnsX1$C{`Yh%ka)l;B{Qr=s_c<<bvM$8rL<pU?1H#w1ad!
z)+#$N9dBCwp$h2^{0hh5Z+u*?LM-9RZQ9%9H2Q^N5cU!ZRuk!oO{TupJc+o*^beXJ
zN8EyMICTpK#$5RvrZ7K+dCV^Wy7}{%>us~%FPhUsddBo0Om8y%x8^qDOQv68dJC?p
zS$QjXt-c?Ti$V3&pNPBz^BH%f#5&5*$tb55>Pe>&ZZo$A|In>7cY(QeaI<P+jk$N3
zYxFay@vaCIvubWwS4zYc)@42u((6o*Yfk!OrYE7DRTsvY`-Hg>rk9y+P6>gPQ;jq_
zRp!#0rO4o_bXhN@G^ZQ(H7B4t3Yzn<%X-P^guK3>YiQ0RA>e(^&Qfnp>jX2JQ!myW
vL=^UO$}v|+6P6A<AyQ!Fm1E8&m;PN71-O(~BW5zW%fZ!rCn7iC#3cL&wC8(L

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index f7c71346bf730775db649c660281eb76142dac5f..25ea48e9aef0e7076124499dd186f078ae4b6327 100644
GIT binary patch
delta 912
zcmZ9K&ref95XX0+g-8r7zSp;`VA80uw3s|O(S$z$<3VCV;=#mPC?Ft|{=h1~K@zc5
zOENL>q#jH>8uCmydi3DIc=D!4kNp#LW_KUmbdveb%zkEO(|tWCyek}Mv*S0C#vb%B
z#v<r-+jEs_zFcMbnIft#a@BHv4eHLtlhsx?KMC$fzVro|*in}pz)8lUEUsc(1biQu
zl$X>&l)Y^Om0f|+3$>wX%;PxQX=%pbPCU^)q2tg^)yG+XN8@eNchAH}rvC}{C0TDr
zH)DsI_rB5lV9~h@ADu&JI5O657MM2SXT*V9?l9km1=r^ds-r}9V9FJI7h)L!zuiIk
zqCLoFOg@Nl4`K<y>yS$LsCQ9c!gJJpI7NL0f0YW)mknzJeFw7Z=m(JVgnXuIEgwuy
zZ~hvZp5Vvu$(!V}LCgDfjxPk?lC2*85KdFRESO#jr7m4u!!Qf~QbNw@1En>K7Qi17
za^9lb7M+6}(nX8zTXY_pNH;8c-sBwPCVWM@Wl`6nHE1EF?-tsyNoe*dZRTtA=DY+`
zX(7vD8%BC<vJvzW>>{nGS__?$T}7|L=d|DzDB_-V_=BB~71NS6IZdq7U2@5y;Vtxo
jm(?x!Z#%Q_7NRS(U#^}p#=^}+i^2QMj~;#m#WDB~A8>%4

delta 1024
zcmZ8gOKTHR6uvi!0sA1CPLi9ELW2}dhQcJis8CwaMR8*{?(3A;7uq(-XrvfJA1-S8
z3a48i;KF5*ap%$>kVO}+#l7_>cusO}bLfG4zVCkDIcM&?K9;x3$CG#O+{)>AIv|9I
z;#xCnz83h^K==#mn0uS~pz3dkZ+riu@-*CxeIJk(c!@EXPG-Z$iRFmnVzUreM6!$h
zRD_N-EAPR~ppsMIjnthNXeP1pay$UbO5-`6X!PNHM9C$+3pBpd*oHY<$q%%H6WeZA
z9QbPQCi+7a(qs4?vtcncD&N9R%9H!Fx5#Ps3q=gZ(hB~j#!K&+x}bR$af|7znqNa~
z!NasCTTsJ%0ADa~!x`p7h-N6?&UpSl>oxNyP}^bpiRSe1cA5TJa|`i^={K0(hM$>P
zSq=x)ud8x7{F6J6%N01g=?y<)9Tk|#E2kdmN!Jk;nOlc-bQ{cFVr~OI<yC2mx#k&A
zk<sZ)yekf!ym~aG=SajiniH7Mg!Bf}Q<{_hn(0~a3hMqSb2phAXL^O{<|+|r7F2T_
zof>oL%~IrXRlBU0a+=c(2bvR59R<yK*=4<CbV6QV)HO8cl@O42tpfGdwN5apIrU=A
uMI>R)RgO6!O?ZCc36X;)y5_p%(!Xn>2&b+ZHj~NS2!FVpxZHzQ3H}2Qv33Oj

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 5e2b654d2a1fd424589f14cebb8628a554172756..8ae43741706f2cb3a0d17cb9c7927784fa55bf8f 100644
GIT binary patch
delta 920
zcmZXQ&ubGw6vt;ul1dPgvPmb4T^dEw=%HKi&>jTAO9e#{58|bhNt@bgnykAUZB;C`
z)mkqK?=JoarR>3rcaObz@*<uDFFAUw@9htLwGZYy-<i+6_hx3xd@%3lZqLrt(`Xfi
z5IG!g`OraV{7{&7A2nI%&^Mk~>MWZ<H`GBV9C&)Q7j}Gq;Dy1#+RdCih(710i%=}r
zqjRN|5oZib3XvD(c>X7fENm9ez{O$>zKwa#HQXrU$^XNleK?!9@^0pw%jASSQT1we
zB7f_zYh}*qqN|Hh)Z?*^%eX^fkDP!XIjb~%W2P>&X$Q&E;kvZ}mn_>lo=VSnLzjbJ
z)`VP#(TXc~;>!}*fT5-2Q+U@@@S;+)w^;JW)You+2KyByx8VzBZ^LiYS1?s|<#V`;
z`Wkj){Zw`B9aiCM>gkJj;i#(Q9;oqoxe)2`pQmIynx7mN<RZ*ATwAleJ0r=WfztwP
zHk93B^d6%c_K_M!HKQ%~j&zC9MMe#jrj$Kk^mOVa&X3^=(kF~o81<o#G+=as(U2<3
zhxDtm3x{}ejh&?bq-f&k!V%J5yiSC6DbC~QgNqe<Fhuo0H<kS;W{J$Do-#b@Wp^0O
jy3m7{<1Y6Z&AJd>q5AeJqgiF552DEnhXwf(hA#X88EJ^x

delta 960
zcmY*XOHUL*5bj>r(V*atGtev{*^QEYcyM+V2!w<S2jJo!2nWJp7*?YM71&)Ps06}8
z9tR$&cqJxYxNXe*0B&A6=z%*2j{F3yn(ZdFm2`d8-}hB@Po__Tjo@gYulGe-$4rY5
z;tsBlX8F}xP^pPvb^&u^<JT&|qWHb{DlY5cMf`aS9M~4PiLS8i(RxfigF{=%0@SS(
z{IPds0Hw!D_QM+HG0MqF9G(yoS9459o_A4RiJaSLNQ-;THrySP3d4?lyp)8Jv+OiG
z6mIvRc-H~T?UpO>)b->x?QK%NFmoKvTm=ViPjQp6KXu)S_>J+Wy6!^Uf=isb1x~vs
zzrzUTRj6X#fnQPn+wK+V`X>JA!baRRB;pw3_u*y7sPx0H9ar~dIV`8HE%_QIGG6Np
z>zIJEj7m<$8q^bnfT>e(jjGSoS*H4s%Bo_Ssc)ES_zZHq%Ysr?jX%^*iTIgyncqnK
zGUHuc6JKR~C)BfQu$!r$m})WpJ>$(OF}TU9wH{RHjhdi8MUlhxA*vcFt!w(=1zi)6
zkAmhbMpYvjo{;+s+Cy`egn%D8J5Rk8%@YjhntIW58wohisie6fO?Z2&;q!(YRL!}h
Z&M~zBUS74D$)wJQL-}({Zoq>A{0IJCaDo5;

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 0fbb1165ddbc8204cbee6d1fbba851438f44c114..d9c6927e7c8df929972010a46a182e9ac234aec6 100644
GIT binary patch
delta 852
zcmZ9Jy-yoK5XE=Fn1})!o71uof`tNDN^x|tBBV$(q;pNf-9dnafNhKkCW(X+J_2rt
z^eQSu10}Mq3k5Zm8+uAg{|PYTTPqunwDV@>_jdQRSMx9ZKe^o7>5K`#PY4mCRkN43
zRSC)!5iAxdM~zo02POPX4c7~I-Lf9$V(<FGTK{pE9-y5<^oV3j|0RVt16Ly-Xpkh@
z8KXj=o^ZO|NJnN`J}LS;jI+j<H|iVzI{7l9x5F(&HR8P|M3O?{EH#e%R24TVo&Mjf
zs6EC-ERAydrL5vK?aBl0N15zeW_}-zAzI(iB;PNL4J!S;HI34msfS7TksoyBKK3Xd
z;+pagJWxJD!r}a$@&SsD(!Z?}CQZ%nd4h9iPA-Ix&f^QY7&cxt<8leN6Rz~ooKSkf
z+Be@7HRB{c#wL~aEb3V_K%S^?(Itz1#2(SWqH$A8(rsK5{c6$n|7N;_2cl(*@>_8*
z-9lnY=}N1Ql6~?QdQqkMf3~B&_caYRP^7&!%@`YhdI9G|i)O--H8pDi4WcD8Vab`A
uPu|4Sl#(UBT`t4TD!pPTOUBfE%PPFAlAriA`5C8FuZ36HMqK{Hj*Dl3VtXb4

delta 984
zcmZuwK~ED=5PsX1hCm^0cbCVK3f0hM1BXR}hV&2UT|E#E+pUoxsHLSb2q7duK^kKu
zlX%dBH$57&M-x5hNe;x5i6;+6k0c(raB-&lUK|LM?0hrdH#6_;zPE2G?aK4%t5a8s
z$|^lVh$KD_^%E>N!$wnt)f)OZ37U;?Nxa|tnl#=;w^HREBM0Bc?dWNLJK>CDqYzyp
z+rj^C68zj-CqyEP>RG!6^{kES-cWcOM)J~_RoT44#|m4pf$BbG@Fj2V*B$ttUolS)
zm6-0q#V!+`nFaW3TJX^<7%gHhkhaRoQz{-rT!UWA@7rQ(6^<;~x1g9I#BEr#d}AA4
zq2GZ6^y_efeitTe^0T&oxy2^DP;n0N3FBSHx8Z|*-3X%Oz@KjTQOZQe!@tt-(#^o{
z(kPVOjB_&)ms3~3rp!R#%ApyiR+t(j;OFo_7%-VmLE9b0Uqa%pCJ{AHi&Yt)R<VKj
zi18UXa;2kBozxYkS}-yu9s0avq&7QI><aM7mG}7M`%Kj{X`>GqucwV7N7q%G<~<~M
zeNh!8;BZWCP}h=T2&kHju-1uUH>qM;z0UY)71Nx?IXunb_53a7grNT{wn3<Q(kZHp
gmYG*Efd{WWS>l_}_mEV*3F=ymK6{60V-vuKf0^KN`Tzg`


From d1e0564fcd306ca4138b77267a66257a2bc1d7e9 Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:20:19 +0200
Subject: [PATCH 144/234] Update asm.S

Co-authored-by: Vadim Kaushan <admin@disasm.info>
---
 riscv-rt/asm.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 997162bf..a073774a 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -173,6 +173,7 @@ _start_trap:
 .section .text
 .global default_setup_interrupts
 
+.global default_setup_interrupts
 default_setup_interrupts:
     // Set trap handler
     la t0, _start_trap

From 67f67f0f846613e8303206d4f36a04991c9232f9 Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:21:23 +0200
Subject: [PATCH 145/234] Remove duplicated .global from
 default_setup_interrupts

---
 riscv-rt/asm.S | 1 -
 1 file changed, 1 deletion(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index a073774a..997162bf 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -173,7 +173,6 @@ _start_trap:
 .section .text
 .global default_setup_interrupts
 
-.global default_setup_interrupts
 default_setup_interrupts:
     // Set trap handler
     la t0, _start_trap

From 9275ca97b55cb888ec9abe0ebfce7de669cd691b Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:27:04 +0200
Subject: [PATCH 146/234] Add doc to PROVIDE.

---
 riscv-rt/link.x | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 89ed07b8..3698db0f 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -22,6 +22,7 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler);
    then the function this points to will be called before the RAM is initialized. */
 PROVIDE(__pre_init = default_pre_init);
 
+/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);
 
 /* # Multi-processing hook function

From 3047813439db173f46849d54da4e97762de1294e Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:29:25 +0200
Subject: [PATCH 147/234] Document .weak usage.

---
 riscv-rt/asm.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 997162bf..7165ddf0 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -125,6 +125,7 @@ _abs_start:
 */
 .section .trap, "ax"
 .global _start_trap
+/* Make it .weak so PAC/HAL can provide their own if needed. */
 .weak _start_trap
 
 _start_trap:

From 73ba258ce919dd6b5e636ee88bdaadc12a35bf1e Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:29:38 +0200
Subject: [PATCH 148/234] Regenerate BLOBs

---
 riscv-rt/bin/riscv32i-unknown-none-elf.a   | Bin 8070 -> 8070 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a  | Bin 7930 -> 7930 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a  | Bin 7758 -> 7758 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a | Bin 7626 -> 7626 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a   | Bin 12974 -> 12974 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a  | Bin 12830 -> 12830 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a  | Bin 12446 -> 12446 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a | Bin 12326 -> 12326 bytes
 8 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 520d90a7a188049855f1e6ad808ab3a37fd10fa8..928edbec266d815647485337dbecd0a354ee5136 100644
GIT binary patch
delta 20
ccmZp(Z?oU<j+wD}@_XhNjGH#!U|A;x0AIHWCjbBd

delta 20
ccmZp(Z?oU<j+wD(@_XhNj2k!KU|A;x0AHmEB>(^b

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 0b43c5ff1339105b9d2949f6010f44ed84821010..8c48759c538d74f62365c355a8e3d27ed9031b57 100644
GIT binary patch
delta 20
ccmexm`^$Di95Z9{<ap*6jGH!luxye70AODTUjP6A

delta 20
ccmexm`^$Di95Z9n<ap*6j2kz5uxye70ANiBT>t<8

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 53c1428e8c7b2840df5980a067a71dbb3290ace1..541bc2912f643ebd6ca75aee3cbca1107a8be45e 100644
GIT binary patch
delta 20
ccmX?SbIxYN9%jbo$$Ob!FmBqsjAex+0Axf76aWAK

delta 20
ccmX?SbIxYN9%ja-$$Ob!FmBwujAex+0Aw-=5&!@I

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index dd554a6b187c8feb26ef433e5e818cf8ff3cee32..f09206c4c66ed8d025489e9d44571041a6f78c7f 100644
GIT binary patch
delta 38
ucmX?Qead=+88d4$BO^1@WJl)6Ni2esXEO6n_F?v$#3IkQX|n>$DoFs@#|p>*

delta 38
ucmX?Qead=+88d4WBO^1@WJl)6Ni2esXEO6n_F?v$#3IkQakB!;DoFs@qYB0V

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 39bb3894171e238f34ecb4154f67cef0b287c972..a9d856484e0d78ebeb18b733ed4316bfde4ba44c 100644
GIT binary patch
delta 20
ccmZ3Nx-NBt0t;jFWJQ)YjGH#|u`bXB08{D*X#fBK

delta 20
ccmZ3Nx-NBt0t;i)WJQ)Yj2k!eu`bXB08`ipX8-^I

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index 25ea48e9aef0e7076124499dd186f078ae4b6327..84cac63eb1476816e8719600881b6f43f2921e4c 100644
GIT binary patch
delta 20
ccmbQ2GB0IA4>M!)<X+}CjGH!Bu`JOA09}v>i~s-t

delta 20
ccmbQ2GB0IA4>M!a<X+}Cj2kysu`JOA09}3viU0rr

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 8ae43741706f2cb3a0d17cb9c7927784fa55bf8f..dbd50b2a7cd6f48c7cd1796013d23aed76d69307 100644
GIT binary patch
delta 31
ncmbQ2I4^O-D`wVaMn-0)$%!nHlUUd$`>}K~ZrXf<<(M`AtKJH^

delta 31
ncmbQ2I4^O-D`wUvMn-0)$%!nHlUUd$`>}K~Zrpr><(M`AtHBDl

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index d9c6927e7c8df929972010a46a182e9ac234aec6..f5dbd9b001d5121aac0818683b0e756c982d0f8a 100644
GIT binary patch
delta 25
hcmZ3Muq<Ii8Z%Qf<K#f5q{*k4I~g}^4q>^Z4FG>L377x?

delta 25
hcmZ3Muq<Ii8Z%Q9<K#f5q{*k4I~g}_4q>^Z4FG=}36=l=


From 4f09eda5c1086237b4aa3d23913a923e10ae334e Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 10:51:47 +0200
Subject: [PATCH 149/234] Update CHANGELOG.md

---
 riscv-rt/CHANGELOG.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 517c5092..fe1cff9a 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add support to initialize custom interrupt controllers.
+
 ## [v0.7.0] - 2020-03-10
 
 ### Added

From ed6c4aec350745395aec4fead46aee13f07b6f6a Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 11:41:00 +0200
Subject: [PATCH 150/234] Release v0.7.1

---
 riscv-rt/CHANGELOG.md | 9 +++++++--
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index fe1cff9a..3c440942 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,10 +7,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.1] - 2020-06-02
+
 ### Added
 
 - Add support to initialize custom interrupt controllers.
 
+### Changed
+ - Exception handler may return now
+
 ## [v0.7.0] - 2020-03-10
 
 ### Added
@@ -31,5 +36,5 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...HEAD
-[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...HEAD
+[v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 1daf8799..e46c9dcc 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.7.0"
+version = "0.7.1"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

From f1ef3b4ba2bbc9a031588e59974a858eb23502e7 Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 11:47:42 +0200
Subject: [PATCH 151/234] Update CHANGELOG.md

Co-authored-by: Vadim Kaushan <admin@disasm.info>
---
 riscv-rt/CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 3c440942..4545907d 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -38,3 +38,4 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 [Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...HEAD
 [v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
+[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0

From 13744d9152c1d80e47af02eae7354e440e0db282 Mon Sep 17 00:00:00 2001
From: Karol Harasim <karol.harasim@gmail.com>
Date: Tue, 2 Jun 2020 11:47:53 +0200
Subject: [PATCH 152/234] Fix format.

Co-authored-by: Vadim Kaushan <admin@disasm.info>
---
 riscv-rt/CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 4545907d..26ea86f0 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add support to initialize custom interrupt controllers.
 
 ### Changed
+
  - Exception handler may return now
 
 ## [v0.7.0] - 2020-03-10

From 2880a75b23aa0847a855c11db3b0c8586efb5305 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 15 Jul 2020 04:16:13 +0300
Subject: [PATCH 153/234] Preserve .eh_frame and .eh_frame_hdr

---
 riscv-rt/link.x | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 3698db0f..73553cfb 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -111,11 +111,8 @@ SECTIONS
     KEEP(*(.got .got.*));
   }
 
-  /* Discard .eh_frame, we are not doing unwind on panic so it is not needed */
-  /DISCARD/ :
-  {
-    *(.eh_frame);
-  }
+  .eh_frame (INFO) : { KEEP(*(.eh_frame)) }
+  .eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
 }
 
 /* Do not exceed this mark in the error messages above                                    | */

From 48d45c3f60c348178f0a8f1f2b9049c8fed50b95 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Wed, 15 Jul 2020 04:25:15 +0300
Subject: [PATCH 154/234] Add change log entry

---
 riscv-rt/CHANGELOG.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 26ea86f0..848ab0b2 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Preserve `.eh_frame` and `.eh_frame_hdr` sections
+
 ## [v0.7.1] - 2020-06-02
 
 ### Added

From a9a3fa45657b42a732eeb99b21bea3dd4a438a39 Mon Sep 17 00:00:00 2001
From: Richard Meadows <962920+richardeoin@users.noreply.github.com>
Date: Wed, 15 Jul 2020 22:53:29 +0200
Subject: [PATCH 155/234] Update link.x

Similar to #38, riscv compilers may also generate 'small ro data' `.srodata` sections.

This doesn't appear to be well documented, but see [this blog post](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain) for small amount of context.
---
 riscv-rt/CHANGELOG.md | 1 +
 riscv-rt/link.x       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 848ab0b2..c7538c83 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Preserve `.eh_frame` and `.eh_frame_hdr` sections
+- Place `.srodata` and `.srodata.*` sections in `.rodata`
 
 ## [v0.7.1] - 2020-06-02
 
diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 73553cfb..d319d097 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -57,6 +57,7 @@ SECTIONS
 
   .rodata : ALIGN(4)
   {
+    *(.srodata .srodata.*);
     *(.rodata .rodata.*);
 
     /* 4-byte align the end (VMA) of this section.

From 712433d6b88c2ad229d1d86bb28f3fb4783bf3df Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 16 Jul 2020 00:11:22 +0300
Subject: [PATCH 156/234] Release v0.7.2

---
 riscv-rt/CHANGELOG.md | 5 ++++-
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index c7538c83..4b7ba5ed 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.2] - 2020-07-16
+
 ### Changed
 
 - Preserve `.eh_frame` and `.eh_frame_hdr` sections
@@ -42,6 +44,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...HEAD
+[v0.7.2]: https://github.com/rust-embedded/riscv/compare/v0.7.1...v0.7.2
 [v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index e46c9dcc..f261161d 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.7.1"
+version = "0.7.2"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

From 47416ae5f3226f6c768022f224f4ac9523e16c23 Mon Sep 17 00:00:00 2001
From: luojia65 <me@luojia.cc>
Date: Sat, 18 Jul 2020 22:13:26 +0800
Subject: [PATCH 157/234] Update riscv dependency to version 0.6

---
 riscv-rt/CHANGELOG.md | 7 ++++++-
 riscv-rt/Cargo.toml   | 2 +-
 riscv-rt/README.md    | 2 +-
 riscv-rt/src/lib.rs   | 2 +-
 4 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 4b7ba5ed..9d441243 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update `riscv` to version 0.6
+- Update Minimum Supported Rust Version to 1.42.0
+
 ## [v0.7.2] - 2020-07-16
 
 ### Changed
@@ -22,7 +27,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
- - Exception handler may return now
+- Exception handler may return now
 
 ## [v0.7.0] - 2020-03-10
 
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index f261161d..7d93350d 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "1.0.0"
-riscv = "0.5.5"
+riscv = "0.6"
 riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
 [features]
diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index af56b274..b5d6852e 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -12,7 +12,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.38.0 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index b85a715e..eda4f6ed 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -2,7 +2,7 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.38 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.42 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
 //!
 //! # Features

From 4e372a8f547fc4dbd85f7ff32b670e288a6ea1ed Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 18 Jul 2020 17:32:16 +0300
Subject: [PATCH 158/234] Release v0.8.0

---
 riscv-rt/CHANGELOG.md | 5 ++++-
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 9d441243..a62fb7ae 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.8.0] - 2020-07-18
+
 ### Changed
 
 - Update `riscv` to version 0.6
@@ -49,7 +51,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...HEAD
+[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.2...v0.8.0
 [v0.7.2]: https://github.com/rust-embedded/riscv/compare/v0.7.1...v0.7.2
 [v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 7d93350d..b6929c22 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.7.2"
+version = "0.8.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

From ed55f39e00b6f223806311ed8c0a5df7f9229b1f Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 2 Aug 2020 03:47:49 +0300
Subject: [PATCH 159/234] Update dependencies of riscv-rt-macros

---
 riscv-rt/macros/Cargo.toml |  9 +++++----
 riscv-rt/macros/src/lib.rs | 36 +++++++++++++++++++-----------------
 2 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index 7adbab68..511e681a 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -16,13 +16,14 @@ version = "0.1.6"
 proc-macro = true
 
 [dependencies]
-quote = "0.6.8"
-proc-macro2 = "0.4.20"
+quote = "1.0"
+proc-macro2 = "1.0"
 
 [dependencies.syn]
+version = "1.0"
 features = ["extra-traits", "full"]
-version = "0.15.13"
 
 [dependencies.rand]
-version = "0.5.5"
+version = "0.7.3"
 default-features = false
+features = ["small_rng"]
diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 91ef9117..375d10c9 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -58,14 +58,15 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
 
     // check the function signature
-    let valid_signature = f.constness.is_none()
+    let valid_signature = f.sig.constness.is_none()
+        && f.sig.asyncness.is_none()
         && f.vis == Visibility::Inherited
-        && f.abi.is_none()
-        && f.decl.inputs.is_empty()
-        && f.decl.generics.params.is_empty()
-        && f.decl.generics.where_clause.is_none()
-        && f.decl.variadic.is_none()
-        && match f.decl.output {
+        && f.sig.abi.is_none()
+        && f.sig.inputs.is_empty()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
             ReturnType::Default => false,
             ReturnType::Type(_, ref ty) => match **ty {
                 Type::Never(_) => true,
@@ -90,7 +91,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
 
     // XXX should we blacklist other attributes?
     let attrs = f.attrs;
-    let unsafety = f.unsafety;
+    let unsafety = f.sig.unsafety;
     let hash = random_ident();
     let stmts = f.block.stmts;
 
@@ -133,15 +134,16 @@ pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
 
     // check the function signature
-    let valid_signature = f.constness.is_none()
+    let valid_signature = f.sig.constness.is_none()
+        && f.sig.asyncness.is_none()
         && f.vis == Visibility::Inherited
-        && f.unsafety.is_some()
-        && f.abi.is_none()
-        && f.decl.inputs.is_empty()
-        && f.decl.generics.params.is_empty()
-        && f.decl.generics.where_clause.is_none()
-        && f.decl.variadic.is_none()
-        && match f.decl.output {
+        && f.sig.unsafety.is_some()
+        && f.sig.abi.is_none()
+        && f.sig.inputs.is_empty()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
             ReturnType::Default => true,
             ReturnType::Type(_, ref ty) => match **ty {
                 Type::Tuple(ref tuple) => tuple.elems.is_empty(),
@@ -166,7 +168,7 @@ pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
 
     // XXX should we blacklist other attributes?
     let attrs = f.attrs;
-    let ident = f.ident;
+    let ident = f.sig.ident;
     let block = f.block;
 
     quote!(

From ad9bed1d2cdcd26223f7519ed3737dfb0a72738d Mon Sep 17 00:00:00 2001
From: hasheddan <georgedanielmangum@gmail.com>
Date: Sat, 6 Mar 2021 12:58:58 -0600
Subject: [PATCH 160/234] Fix link to RISC-V team in wg repo

Fixes link to properly direct to heading in wg repo README.md.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
---
 riscv-rt/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index b5d6852e..276c17d0 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -38,4 +38,4 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [CoC]: CODE_OF_CONDUCT.md
-[team]: https://github.com/rust-embedded/wg#the-riscv-team
+[team]: https://github.com/rust-embedded/wg#the-risc-v-team

From 2042f3b645cbaecfc64840c52ea27ca8c00e50ee Mon Sep 17 00:00:00 2001
From: Jake Merdich <jake@merdich.com>
Date: Sat, 26 Jun 2021 13:24:50 -0400
Subject: [PATCH 161/234] [NFC] Fix typo 'suppoted' -> 'supported'

Interested in using this crate and saw this typo when browsing the docs.
---
 riscv-rt/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index eda4f6ed..29c35d7e 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -187,7 +187,7 @@
 //!
 //! ### `_max_hart_id`
 //!
-//! This symbol defines the maximum hart id suppoted. All harts with id
+//! This symbol defines the maximum hart id supported. All harts with id
 //! greater than `_max_hart_id` will be redirected to `abort()`.
 //!
 //! This symbol is supposed to be redefined in platform support crates for

From 2f131cd1e13a9e5da5caf249d3220ce106546eae Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Sun, 18 Jul 2021 19:17:43 -0700
Subject: [PATCH 162/234] switch to Github Actions for CI

---
 riscv-rt/.github/bors.toml              |  6 +++-
 riscv-rt/.github/workflows/ci.yaml      | 40 +++++++++++++++++++++
 riscv-rt/.github/workflows/rustfmt.yaml | 24 +++++++++++++
 riscv-rt/.travis.yml                    | 48 -------------------------
 riscv-rt/ci/install.sh                  | 18 ----------
 riscv-rt/ci/script.sh                   | 24 -------------
 riscv-rt/macros/src/lib.rs              |  4 +--
 7 files changed, 70 insertions(+), 94 deletions(-)
 create mode 100644 riscv-rt/.github/workflows/ci.yaml
 create mode 100644 riscv-rt/.github/workflows/rustfmt.yaml
 delete mode 100644 riscv-rt/.travis.yml
 delete mode 100755 riscv-rt/ci/install.sh
 delete mode 100755 riscv-rt/ci/script.sh

diff --git a/riscv-rt/.github/bors.toml b/riscv-rt/.github/bors.toml
index ca42be0a..cce15496 100644
--- a/riscv-rt/.github/bors.toml
+++ b/riscv-rt/.github/bors.toml
@@ -1,4 +1,8 @@
 block_labels = ["needs-decision"]
 delete_merged_branches = true
 required_approvals = 1
-status = ["continuous-integration/travis-ci/push"]
+status = [
+    "ci-linux (stable)",
+    "ci-linux (1.42.0)",
+    "Rustfmt"
+]
diff --git a/riscv-rt/.github/workflows/ci.yaml b/riscv-rt/.github/workflows/ci.yaml
new file mode 100644
index 00000000..c04f7c3d
--- /dev/null
+++ b/riscv-rt/.github/workflows/ci.yaml
@@ -0,0 +1,40 @@
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Continuous integration
+
+jobs:
+  ci-linux:
+    runs-on: ubuntu-20.04
+    continue-on-error: ${{ matrix.experimental || false }}
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.42.0
+        rust: [nightly, stable, 1.42.0]
+
+        include:
+          # Nightly is only for reference and allowed to fail
+          - rust: nightly
+            experimental: true
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: ${{ matrix.rust }}
+          override: true
+      - name: Install all Rust targets for ${{ matrix.rust }}
+        run: rustup target install --toolchain=${{ matrix.rust }} riscv32imac-unknown-none-elf riscv64imac-unknown-none-elf riscv64gc-unknown-none-elf
+      - name: Install riscv gcc
+        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
+      - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
+        run: TARGET=riscv32imac-unknown-none-elf cargo check
+      - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
+        run: TARGET=riscv64imac-unknown-none-elf cargo check
+      - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
+        run: TARGET=riscv64gc-unknown-none-elf cargo check
+      - name: Check blobs
+        run: ./check-blobs.sh
diff --git a/riscv-rt/.github/workflows/rustfmt.yaml b/riscv-rt/.github/workflows/rustfmt.yaml
new file mode 100644
index 00000000..07273842
--- /dev/null
+++ b/riscv-rt/.github/workflows/rustfmt.yaml
@@ -0,0 +1,24 @@
+
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Code formatting check
+
+jobs:
+  fmt:
+    name: Rustfmt
+    runs-on: ubuntu-20.04
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+          components: rustfmt
+      - uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check
\ No newline at end of file
diff --git a/riscv-rt/.travis.yml b/riscv-rt/.travis.yml
deleted file mode 100644
index 0cd5a417..00000000
--- a/riscv-rt/.travis.yml
+++ /dev/null
@@ -1,48 +0,0 @@
-language: rust
-
-rust:
-- nightly
-- stable
-- 1.38.0 # MSRV
-
-env:
-- TARGET=x86_64-unknown-linux-gnu
-- TARGET=riscv32i-unknown-none-elf
-- TARGET=riscv32imac-unknown-none-elf
-- TARGET=riscv64imac-unknown-none-elf
-
-if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-matrix:
-  allow_failures:
-    - rust: nightly
-  include:
-    - env: CHECK_BLOBS=1
-      rust:
-      language: bash
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-    - env: RUSTFMT=1
-      rust: stable
-      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
-
-
-install:
-  - ci/install.sh
-
-script:
-  - ci/script.sh
-
-cache:
-  cargo: true
-  directories:
-    - gcc
-
-branches:
-  only:
-    - master
-    - staging
-    - trying
-
-notifications:
-  email:
-    on_success: never
diff --git a/riscv-rt/ci/install.sh b/riscv-rt/ci/install.sh
deleted file mode 100755
index 2378704d..00000000
--- a/riscv-rt/ci/install.sh
+++ /dev/null
@@ -1,18 +0,0 @@
-#!/usr/bin/env bash
-
-set -euxo pipefail
-
-if [ -n "${TARGET:-}" ]; then
-    rustup target add $TARGET
-fi
-
-if [ -n "${CHECK_BLOBS:-}" ]; then
-    if [ ! -d gcc/bin ]; then
-        mkdir -p gcc
-        curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
-    fi
-fi
-
-if [ -n "${RUSTFMT:-}" ]; then
-    rustup component add rustfmt
-fi
diff --git a/riscv-rt/ci/script.sh b/riscv-rt/ci/script.sh
deleted file mode 100755
index e35612e4..00000000
--- a/riscv-rt/ci/script.sh
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/usr/bin/env bash
-
-set -euxo pipefail
-
-if [ -n "${TARGET:-}" ]; then
-    cargo check --target $TARGET
-
-    if [[ $TARGET == riscv* ]]; then
-        cargo check --target $TARGET --examples
-    fi
-
-    if [ $TRAVIS_RUST_VERSION = nightly ]; then
-        cargo check --target $TARGET --features inline-asm
-    fi
-fi
-
-if [ -n "${CHECK_BLOBS:-}" ]; then
-    PATH="$PATH:$PWD/gcc/bin"
-    ./check-blobs.sh
-fi
-
-if [ -n "${RUSTFMT:-}" ]; then
-    cargo fmt -- --check
-fi
diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 375d10c9..96fdd2cd 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -14,9 +14,7 @@ use rand::Rng;
 use rand::SeedableRng;
 use std::sync::atomic::{AtomicUsize, Ordering};
 use std::time::{SystemTime, UNIX_EPOCH};
-use syn::{
-    parse, spanned::Spanned, Ident, ItemFn, ReturnType, Type, Visibility,
-};
+use syn::{parse, spanned::Spanned, Ident, ItemFn, ReturnType, Type, Visibility};
 
 static CALL_COUNT: AtomicUsize = AtomicUsize::new(0);
 

From 9a190215cadaf2bba2f34657ad9c8caa7deb8477 Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Tue, 20 Jul 2021 09:27:34 -0700
Subject: [PATCH 163/234] use --target for CI checks

---
 riscv-rt/.github/workflows/ci.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/.github/workflows/ci.yaml b/riscv-rt/.github/workflows/ci.yaml
index c04f7c3d..7d68c697 100644
--- a/riscv-rt/.github/workflows/ci.yaml
+++ b/riscv-rt/.github/workflows/ci.yaml
@@ -31,10 +31,10 @@ jobs:
       - name: Install riscv gcc
         run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
       - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
-        run: TARGET=riscv32imac-unknown-none-elf cargo check
+        run: cargo check --target riscv32imac-unknown-none-elf
       - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
-        run: TARGET=riscv64imac-unknown-none-elf cargo check
+        run: cargo check --target riscv64imac-unknown-none-elf
       - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
-        run: TARGET=riscv64gc-unknown-none-elf cargo check
+        run: cargo check --target riscv64gc-unknown-none-elf
       - name: Check blobs
         run: ./check-blobs.sh

From 27b0ed55e04b387cc4228fbd5ee368456390656d Mon Sep 17 00:00:00 2001
From: smsxgli <smsxgli@gmail.com>
Date: Sat, 18 Sep 2021 21:19:57 +0800
Subject: [PATCH 164/234] update to riscv 0.7

---
 riscv-rt/Cargo.toml                          |   2 +-
 riscv-rt/assemble.ps1                        |  19 +++++++++++----
 riscv-rt/assemble.sh                         |  23 ++++++++++++++++---
 riscv-rt/bin/riscv32i-unknown-none-elf.a     | Bin 8070 -> 8194 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a    | Bin 7930 -> 8054 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a    | Bin 0 -> 8198 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a   | Bin 0 -> 8058 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a   | Bin 0 -> 8202 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a  | Bin 0 -> 8066 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a    | Bin 7758 -> 7882 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a   | Bin 7626 -> 7750 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a   | Bin 0 -> 7886 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a  | Bin 0 -> 7758 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a  | Bin 0 -> 7894 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a | Bin 0 -> 7762 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a     | Bin 12974 -> 13102 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a    | Bin 12830 -> 12966 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a    | Bin 0 -> 13110 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a   | Bin 0 -> 12966 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a   | Bin 0 -> 13110 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a  | Bin 0 -> 12974 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a    | Bin 12446 -> 12598 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a   | Bin 12326 -> 12470 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a   | Bin 0 -> 12598 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a  | Bin 0 -> 12478 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a  | Bin 0 -> 12606 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a | Bin 0 -> 12486 bytes
 riscv-rt/build.rs                            |   2 +-
 28 files changed, 37 insertions(+), 9 deletions(-)
 create mode 100644 riscv-rt/bin/riscv32if-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32ifc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32ifd-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32imf-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32imfc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32imfd-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64if-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64ifc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64ifd-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64imf-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64imfc-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64imfd-unknown-none-elf.a
 create mode 100644 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index b6929c22..cc928a81 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,7 +10,7 @@ license = "ISC"
 
 [dependencies]
 r0 = "1.0.0"
-riscv = "0.6"
+riscv = "0.7"
 riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
 [features]
diff --git a/riscv-rt/assemble.ps1 b/riscv-rt/assemble.ps1
index 389014a7..c5e67f67 100644
--- a/riscv-rt/assemble.ps1
+++ b/riscv-rt/assemble.ps1
@@ -1,15 +1,26 @@
+New-Item -Force -Name bin -Type Directory
+
 # remove existing blobs because otherwise this will append object files to the old blobs
 Remove-Item -Force bin/*.a
 
 $crate = "riscv-rt"
-$extension_sets = @("i", "im", "ic", "imc")
+
+$extension_sets = @("i", "im", "ic", "imc", "if", "ifc", "imf", "imfc", "ifd", "ifdc", "imfd", "imfdc")
+
 $pwd = Get-Location
 
-foreach ($ext in $extension_sets) {
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c -mabi=ilp32 -march=rv32$ext asm.S -o bin/$crate.o
+foreach ($ext in $extension_sets)
+{
+    $abi = ""
+    if ($ext.contains("d"))
+        {$abi = "d"}
+    elseif ($ext.contains("f"))
+        {$abi = "f"}
+
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=ilp32$abi" "-march=rv32$ext" asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
 
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c -mabi=lp64 -march=rv64$ext asm.S -o bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=lp64$abi" "-march=rv64$ext" asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
 }
 
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index 997d9ae8..b8d85d67 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -7,12 +7,29 @@ crate=riscv-rt
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
-for ext in i ic im imc
+exts=('i' 'ic' 'im' 'imc' 'if' 'ifc' 'imf' 'imfc' 'ifd' 'ifdc' 'imfd' 'imfdc')
+
+for ext in ${exts[@]}
 do
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32 -march=rv32${ext} asm.S -o bin/$crate.o
+    case $ext in
+
+        *'d'*)
+            abi='d'
+            ;;
+        
+        *'f'*)
+            abi='f'
+            ;;
+        
+        *)
+            abi=''
+            ;;
+    esac
+
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf.a bin/$crate.o
 
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64 -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
 done
 
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 8c48759c538d74f62365c355a8e3d27ed9031b57..1d0ee0af60adcdebbd7929d870cd235b9c41e54f 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 541bc2912f643ebd6ca75aee3cbca1107a8be45e..629a2d45051736a070ca7dfb870f647a5de47cc6 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index f09206c4c66ed8d025489e9d44571041a6f78c7f..a39c08062527220b9376086ccdfee313e3b16f13 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index a9d856484e0d78ebeb18b733ed4316bfde4ba44c..9f4ca5d2fa8c87d28f797e470cedafa61aa011b3 100644
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diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
new file mode 100644
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diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index f5dbd9b001d5121aac0818683b0e756c982d0f8a..b2763d0bf7849d656e2c1e61d2a4e3169eb74bb4 100644
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diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
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HcmV?d00001

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index dff0f3e3..9801b190 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -14,7 +14,7 @@ fn main() {
 
     if target.starts_with("riscv") {
         let mut target = Target::from_target_str(&target);
-        target.retain_extensions("imc");
+        target.retain_extensions("imfdc");
 
         let target = target.to_string();
 

From daeaf182e242107b7f4e564258e3535b042f9e76 Mon Sep 17 00:00:00 2001
From: Scott Mabin <scott@mabez.dev>
Date: Fri, 5 Nov 2021 15:34:09 +0100
Subject: [PATCH 165/234] Trap handler override improvments

* Add ability to override trap handling mechanism
  * Previously, `_start_trap` was marked as weak, which when compiled
    into a static archive, that information is ignored.
  * Now by default we `PROVIDE` the default trap handler, if another one
    has not been specified from another crate.
* Mark the fields of `Vector` public, for use outside of `riscv-rt`
---
 riscv-rt/asm.S                               |   6 ++----
 riscv-rt/bin/riscv32i-unknown-none-elf.a     | Bin 8194 -> 8226 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a    | Bin 8054 -> 8082 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a    | Bin 8198 -> 8230 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a   | Bin 8058 -> 8086 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a   | Bin 8202 -> 8234 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a  | Bin 8066 -> 8094 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a    | Bin 7882 -> 7914 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a   | Bin 7750 -> 7778 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a   | Bin 7886 -> 7918 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a  | Bin 7758 -> 7786 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a  | Bin 7894 -> 7926 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a | Bin 7762 -> 7790 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a     | Bin 13102 -> 13142 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a    | Bin 12966 -> 12998 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a    | Bin 13110 -> 13150 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a   | Bin 12966 -> 12998 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a   | Bin 13110 -> 13150 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a  | Bin 12974 -> 13006 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a    | Bin 12598 -> 12638 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a   | Bin 12470 -> 12502 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a   | Bin 12598 -> 12638 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a  | Bin 12478 -> 12510 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a  | Bin 12606 -> 12646 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a | Bin 12486 -> 12518 bytes
 riscv-rt/link.x                              |   6 ++++++
 riscv-rt/src/lib.rs                          |   5 +++--
 27 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 7165ddf0..910d3593 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -124,11 +124,9 @@ _abs_start:
     restores caller saved registers and then returns.
 */
 .section .trap, "ax"
-.global _start_trap
-/* Make it .weak so PAC/HAL can provide their own if needed. */
-.weak _start_trap
+.global default_start_trap
 
-_start_trap:
+default_start_trap:
     addi sp, sp, -16*REGBYTES
 
     STORE ra, 0*REGBYTES(sp)
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index f09da16d9a0e81ba0695e7f87871898c402da25a..50197c5abaee32ad321f672f4c368cb818d6b4f0 100644
GIT binary patch
delta 362
zcmZp2SmZE4BE-<l*v#16#L&`QLBT))1dvGu1#=6qAdpDlVqjok0pdx>IKH?fv8aS0
zF)1HNrlh7Nmgba9OjR{yD9S8OF4HY4(aYBdn}BSQsevI-%m{3gp@D&!iHU-Og@KX5
z#C;l!E*qbVGcz_${?Gh^al_;nEE^cjC(mY8-n@s^iqlwtft{fqXgv%F02vct93U;g
zz{pUH!e^K)$)C#(b=c%Kej8>6@rjcJ#5UjJui#-4;GY~KGmp_{@@E-;#*oR*vi^(-
zlPAlT14(YVa>f;to8`0_WhSqeQ)av}`Ldikqr&9ha{i1ilfC7Gf$aJ6%B(4T3=AtL
TAD35_$dF=SxPxRlBa{sQsCiHp

delta 352
zcmZ4F(Bv>d!q-3n0U&H-QbEBSt{{Pnfq{Vqh`W$+d~r!)Q3*q0Qa+HJn4@Y^lv$iy
zrdw2^m#+^t8Ll75LpIvX!~`sFZfR*Y@t6jq&c^rR%&g6fjLb}v1z92|UtkfOoXNsF
zS%$?A$d+f^H2DL|24*uo!^sO-l{X(_wcu1%U|?sc06GQ+1b~cA7zaoTFfdLw<j<YF
zl;4I)yl=9CfY|0={1rS*Klmn>$joCjnJg^p&uB9_8Ay6e-Yi=VB(>$r87E9$ET_#V
zH~GArGUK($pXJmUIVMZX`!niH&Xx~m6qvkUUYRw7kAY#)<md9r5&=>S40n($WrVT;
DA}LG2

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 1d0ee0af60adcdebbd7929d870cd235b9c41e54f..0b7f5925c69bab4e5769700df2dbb80e67a6bad9 100644
GIT binary patch
delta 374
zcmexnH_3j2M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^RP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BCd{<`eg7
zGH%)Uyq$@$adJNM3&stTBUm;tnos6tRotw{YQt$Pz`)K>540Ty1b~bQFb<FwU|?h@
zM&UC|?&Zs6hq`O>FFqS)2JwlTE%^I*7#k)Zm!8kKXL7oXKjV?f+kxbT$?US_K(Zc4
zN=*JPtIa4gSy@h*)dlElg~^3H!jt3V1Q;hw&X-eXOqo0#NN$<DUrwEM0#IHVEdNhV
dfOQL4wXnQ0>lI!GhLvD(KY0Ph8<XSZ#Q`vnSRnua

delta 368
zcmbPa|IKcKgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(7D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+`@F?QBB4L8{fAxu{JX@GBZtXWR9Hdz#=&LCNuBk
z9%ervTb^;#<OG%t%w~FqlLc8785uSkvf6SgD=@G#Q~+HA0|G!sCyWE61sE77FXYRe
zEXr@gB;Gf90>9YiEdB}}#+=EIrROuQnA|Mm&$waoWgxj{va)PBkem%9Stbk1X*0@A
zwwF_8beo(kr_NY2xf@7kOx_G67fiklB&SSfmRD!p0Spd-$@=ojtS5LG7#2+qmsgfJ
OBFVsT2gwbLP&NRmdQbEK

diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf.a b/riscv-rt/bin/riscv32if-unknown-none-elf.a
index f8e099f2c357e6167cc4fe172e45212309d84cd0..18ec3f29d7fdb4c7e0ee197ec18013bc76df0a13 100644
GIT binary patch
delta 353
zcmZp3SmrQ6BE-<l*v#16#L&`QLBT))1dvGu1#=6qAdpDlVqjok0pdx>IKH?fv8aS0
zF)1HNrlh7Nmgba9OjR{yD9S8OF4HY4(aYBdn}BSQsevI-%m{3gp@D&!iHU-Og@KXD
z#C;l!9vh#FGcz_${?Gh^al_;nEE^cjC(mY8-n@s^j?-9xft{fqXgv%F02vct93U;g
zz{pUH!e^K)%b&{*b=c%Cej8>6@rj#H@b~dBiSSR3keSCAF!{TTKV!sXcUgbNl*!X&
z%Yh`nTsh;K$?bC5j53oq%PF&70s32UG9$0><acrcj4G4=%lR{UO!k)#W>lEGSYDYm
VgO7n>C0PERyZ}><)Z_~?VgTInQV9S6

delta 330
zcmZ4H(B?2f!q-3n0U&H-QbEBSt{{Pnfq{Vqh`W$+d~r!)Q3*q0Qa+HJn4@Y^lv$iy
zrdw2^m#+^t8Ll75LpIvX!~`sFVPIe|@t6jq!N&LE%&g6fjLb}v1z92|UtkfOoXNsF
zS%$?A$d+f^H2DL|24*uo!^sO-l{X(_wc%7&U|?sc06GQ+1b~cA7zaoTFfdLw<<FhG
zlHZ0&yl?Xh{yrY2KYWubWacqiOcs~*XLOjH4kUdhZ<j3xlKOJxj8i5rm(ymHn|xVL
vnep1>?{eylJd@?+{TU4==gS8(3QRsMugn_3$H1^?@@sizrVy#gA7sP;)YeP}

diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf.a
index 0a5234ec67ec749fe8671ae62cf11c3f3559fa91..4e8484b9ef864e020d817152ee877ee5c90dd704 100644
GIT binary patch
delta 373
zcmexmH_d*6M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^RP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BCd{78Cbs
zGVa*;yq$@$adJNM3&stTBUm;tnos6tRotw{>cD9%z`)K>540Ty1b~bQFb<FwU|?h@
zM&UC|p2(NW4t3Y$e|$E~4B`_v+wk}CFt$uSEj^#{z~pQhf5sD&cLT{QleuNffn+m~
zl$rcnRvSpF%PBLuO!k&jXPh#*7)Yi}o(&{-Og;=GCro}Vr_Q<q7$ypn#pRV*Z}2iO
Vtek8wuPkv#l7Zn4l0z7wYydxgRLcMW

delta 345
zcmbPc|I2QIgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(7D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+`??)QBB4r8{fAxu{JX@GBZtXWR9Hdz#=&LCNuBk
z9%ervTb^;#<OG%t%w~FqlLc8785uSkvO01qD=@G#Q~+HA0|G!sCyWE61sE77FXhXf
zEXi-fB;L0<g1?W4v0(CZ>G_OnCb!G@Gj5rD9Y`LStS(y)B<BN3j>+P3+Kh6Oo#m7n
z-6p5YsWUcA?gx??leYuOC6n(1$tjcB<<(jD0E0qcva!4}>lt1KhDDR3<&_yvOs<y~
F2LPdePiO!D

diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
index a5924f786de4cb17130be74ac60911a9021528c1..41068e68c51645dd67672ecc67df34f9dd95dab9 100644
GIT binary patch
delta 358
zcmeBjSmiK5BE-<l*v#16#L&`QLBT))1dvGu1#=6qAdpDlVqjok0pdx>IKH?fv8aS0
zF)1HNrlh7Nmgba9OjR{yD9S8OF4HY4(aYBdn}BSQsevI-%m{3gp@D&!iHU-Og@KX9
z#C;l!J{zBlGcz_${?Gh^al_;nEE^cjC(mY8-n@s^iPKnsft{fqXgv%F02vct93U;g
zz{pUH!e^MQ$e+s&b=c%Sej8>6@rj$y@b~dBN=%NHna>z9`L~QeW6Wf4S%1ci$+Kn4
zfuyipIneHIIc-Ln$=l_W8Lv#fEvL??F_~H3pV4P>uzWD1!sO-h%B(qj3=AtLpO;sb
PD3D@cxPxRdBa{sQu8L1T

delta 347
zcmZ4G(B&{e!q-3n0U&H-QbEBSt{{Pnfq{Vqh`W$+d~r!)Q3*q0Qa+HJn4@Y^lv$iy
zrdw2^m#+^t8Ll75LpIvX!~`sFVPIe~@t6jq$;S8M%&g6fjLb}v1z92|UtkfOoXNsF
zS%$?A$d+f^H2DL|24*uo!^sO-l{X(_b>LK1U|?sc06GQ+1b~cA7zaoTFfdNG<j<YF
zmfwa+yl?Xx{yrW?hRM}3^BHX>OUwE*x=hXnk^z%<%a#L4W4Ut18IxDbX*0@AzAmTC
xcy01;Idw*X$;$Hnj3$$d<%5Cj<MPU^F?<XRizdI9SC)v7Vqmy~WFI4x4FImsO056@

diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
index 8c424ff8e070718e5326536638f018127ccc20b9..223b16942f02ec543c7b2db11439df241a76a5bf 100644
GIT binary patch
delta 377
zcmZp&pJzWoBE-<l*v#16#L&`0LBT))1dvGu1#_S{1SD`VFfgzH@g!s%UtE${RKk#$
zln*3RQqvMkb4n(rs+uqqWfmuw=@ymf<?Dm>BU@x@U<ed50^4M0U|?oq0<y?r;$BV0
z0~?>WGch(!&S!qXxM6Yx%LYdC$=s}poAp>dIE@7u*cs}9w!?q`kTC(q0n!2tj10vn
ze1^$0`EuEz?wZWTZ^O(WK5=pbzu4v|{t6z(p2?S`=QEy|TrA_ycwzEkAbDr9uxvSy
z>;{r5lbPkT8D%Ex%PBLuOb(V)XPh&+8c3#0UJN7;Og;@HCrth<r_Oo+7%mEv<>i%G
ZAMi3TteosFuPpIIl7Zn4l4BU5YygB7REPio

delta 353
zcmbPd-(){Q!q-3n0U&H-QbEBSt{{Pnfq{Vqh`W$+d~r!)Q3*q0Qa+HJn4@Z3lv$iy
zrdw2^m#+^t8Ll75LpIvX!~`sFZecd@s3zl@jqlr;SeqFcnVBXxGDl8!U=f^rlbLsN
z53?VTEzh`VastZ+W-~p*$%3qkj0~F%Sv@(G6&TnVDuAwm0RbSR6UG730t}3k*Yf2~
zR^+!~67Sobz~9HiSTXs%^nAuGllx`-8TU-S4<t`a)|V{@lFNalz+`zjZAQ7t-g3%}
zZj<xn)EPS_PY042llKG3HIttM$tjch<<(h_0E0qcvbDT2>lI!GhDDPbd4wmI$qTSv
LkYr%E1L6Sy)S*%U

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 629a2d45051736a070ca7dfb870f647a5de47cc6..94f45690c9278c5a78181d3a0ff8d64774a0eac3 100644
GIT binary patch
delta 381
zcmX?Q`^t8LM2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^ZP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BD3C<^~oM
z_h~TkNNs%ago&|n@>%8=j2k9zW7))LJ~^9Jd2<izISyk126l#Gp#3l)0A#elI6zu}
zfsr8{h0id#mM@VV>axlA_-vRN#Je`j@c-jx%$O`KJ)d#O<lWN#j8i6a%lI=cm>exr
z&Zsf@GLS5o>@BO!C^NZSR+)7P(BF!a8+n8UmjMk21%d<Ak{6Q?%lb3%NKO`!3j#Vf
fT~3+x1TO=_T##Z>L7*aLs6r5BAj!aR2P6XkS+Y{$

delta 345
zcmaE5d&+i#gs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O&;D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|0sc;xP@TFOnNSJYiyOW@Kb$njFXyJoy7N&*b&Y
zY?JL+>KQjp-p8_u*-X!Hav`ho=4q^FIFuC_*cozwE`b37Afpz>0n!2tjFYGGB~Jd!
zXTv1kzS)NVA2(ybWNYd9j6IWYOZzj{OxBk1XY80<EmO`YF!?i(jF_A)tIa4kdAh7J
z<Fd)SWz`ukOnxlu&-6uNvWZ*}<ATZUa>}ebco`U`O<pgjEFmGuz;Fl2LPjVX0Mctt
A`v3p{

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index a39c08062527220b9376086ccdfee313e3b16f13..f90bcc31d1add4d7055b65acea8e903a286a1a87 100644
GIT binary patch
delta 375
zcmX?R^T=j`M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^RP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BD3Crsfm(
zYBIKLd>+rl+Q`Vr%rrTWIdZZ9i{Rvy%)FChnEilkdBzQs4OliXnooYrqPUrj^#X^n
z00TQiG0;UYAOK{vz&Jo!fPs-A9fi*@`6q88JJhX{qxfu?8N|Cb&*1yV&G=yQbgB7_
zGLy}v{h4_9CwEBuF-lCnE?v&JV6wkVIpd4T$7QsE(w}9Nfuy*sI%C3Qdmw2uIUPv0
oOzsDg8I!lms<Tc22GoYhk7bov9e5cS=1%68Q)XN-Szk^Z0PqM_>i_@%

delta 354
zcmaE4bIfLfgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(7D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|+d9QBB5zjql@`7@H^iGrwTmG}(e>1GAZ);pCSr
zii`}KIax1qC@V0qGvokmh5-Q}qZY;i(gF;OlX>|PCztZsFp0NM{=g@;`4ry^ZpJf{
zH%rZD<d_^R?a%asZ}JjpKSq|xpQXzgdnRYglrvtL{8&btQEoE7tTL+{(02-x8F_>!
zd&vqg`b>_NRcCaV+zccOCa;!NXUzf1Yk=in$qKMe0rD11{twh=!pp!g4J>XY2NaiJ
JV7LR~0RZO_P(uI!

diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf.a b/riscv-rt/bin/riscv32imf-unknown-none-elf.a
index aa1c333627174f4bf8c91e68353c6284d2e44785..2127d91edbb1f25b3d853910ee278d49a08d6171 100644
GIT binary patch
delta 360
zcmX?S`_6WPM2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^ZP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BD3C=7vTS
z_h~Q*NNs%ago&|n@>%8=j2k9zW7))LJ~^9Jd2<izB@SZ&26l#Gp#3l)0A#elI6zu}
zfsr8{h0id#kuQ-Q>axj?_-vRN#Je^t@c-jx%$Y1NJ)d#K<o(kAj58+l%lI=cnH(=u
z&Zsl_I*=@x>@Ta$C^NZQRv9QhUsj#*&E(^<{!9XrlO^PWfKJPnQ)WHG%fK*q@?<$>
P2@^>MhC4_$GeX$_ff7+!

delta 345
zcmaE7d(L)(gs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O&;D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|0sa;xP@TACenCJYiyOW@Kb$njFXyJoy7N&*b&Y
zY?JL+>KQjp-p8_u*-X!Hav`ho=4q@KIFuC_*cozwE`b37Afpz>0n!2tjFV^bB~E7K
zw_y@*-|WEukDD=Mvc2?t#tD<}OZzi6OxBn2XY83=FH_DaGWk1@jG3G-tIa4kdA6)F
z<Fd*7Wz`w4Onxrw&-6oLvV~j_<ATZEa>}fGco`U`P2Mc0EFmMwz;Fl2LPjVX0FiS}
AbN~PV

diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf.a
index c03b50320a91a9fef6e05f7a24c63224ef0ef754..0c157001829fe37ced38ec582a53f985dacb5e18 100644
GIT binary patch
delta 393
zcmX?S^U7v|M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^RP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6BD3CrWO<T
zYBKh0d>+rl+Q`Vr%rrTWIdZZ9i{Rvy%)FChnEilkdBzQs4OliXnooYrqPUrj^#+Hr
z00TQiG0;UYAOK{vz&Jo!fPs-A9fi*@nUOD%9qQJ}NqjcU4B}mz7x4Y#W_&SuzSMk1
zmC5$f{){4%`+=mw<onX)j4LLG%ak*In0#JFn^9)+Zy9AEDKD$em@(NMNZL%!2a-LL
qr-McI%c`@^0EW|s$**OVSv`0e80JnEmQ$A4Ai=<J2gxCfP&NPnV^;D2

delta 344
zcmaE5bIxXhgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(7D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|+F1QBB5*jql@`7@H^iGrwTmG}(e>1GAZ);pCSr
zii`}KIazOVC@V0qGvokmh5-Q}qZY;i(gF;OlSTOwC)e`XFp0Ns-oy8goAJuz-BR-z
z1tv#J`!h03UJWF9CjXW$XPh#*Sf-ru&g9oJ+Kh6O#buR&q_wO%W60!WAn7o<8%S16
s-V7vjCf}A-XPpD|_JYama>}eWybKJ}ChN;7OU#jAV7P;1KO>Y40M$)Oe*gdg

diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf.a
index 34d9847bdce7029f4f8e15ab5122d84c613ca421..54fb2a4de8a00a0323f1b95c6b1119d44ccde33b 100644
GIT binary patch
delta 339
zcmca+`^|QOM2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)TO$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJ1Za`Dk-@}$
z8jKPfpFd?{Y@B?S`32*K$=g^qF`7@#W>wzY!+MLuSb%|@p%`dA3<v-jEiev{7GPjx
zNJrr_Ozz}MWQRIz@+&?YW(M)D%^LjwxEV_(t4q%Z+HqXkpK-xtaT$NcHIvh2${9^2
z-v^R4lfz}T8D%Cn%PKQ2nY>(9o$<@$^RoVo5|icSf`Ph<<&;^k@G>yWojhAknbBtQ
HemQXfLNro`

delta 324
zcmexnd(C!&gs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O&;D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|1H!;xP?IhK=u^GO;!@GBPtw4rB?Q{DGNg@_J^r
z$#yLDjGHF!W7))Pre`?0kX3o}G}ap&$_fnZ3^_oDz<>adQ48Y$X#obt$qV@sCv)=K
zFp0Ns_Tc}=%@{M;U3xy_jLFZX{TVwZo6Gn!PMO>;Q_d(e`9F|MnOrWb%_ui{v8*!V
tvdPC~)fw+helP3K$S~PnE|_t_<jHc%tVehm7^Y3$EvL+=GWouoH~_yHO~L>G

diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
index 2cfabd7645e191284b77642d787dd2f3b16b95c2..e474cce63ef867be5ceef72b35e57f6456dfe5d0 100644
GIT binary patch
delta 397
zcmca)^Uh|1M2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)HK$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJ1Za_|#l*du
zj1x9Kk7r_SWMpJ!njFX+Iaz>3aPmrK-pMh{en7T7<A%uwEE^cjCqHIU+|0&$hr?Ka
zft{fk=pq;p05V!&93U;gz{rq}!e^Mw%9qFvb?f9bJ{x8R@vg}a_{28v;(Ni(_-68A
zsrif=lbxmg86_r929he1A4``ru9+MyQ_lEh@?{xqMw!X~Wt4%WvaC8|&SY;OX*0PP
vNKTkM8%SnMJ}j%wItLh58z#S(Rc7_!Wnh>)SzJz8Vv7U=!yP2YFhbb?-IrMl

delta 344
zcmaE7bIE3cgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(7D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV+|+F1QBB60jql@`7@H^iGrwTmG}(e>1GAZ);pCSr
zii`}KIa%*=C@V0qGvokmh5-Q}qZY;i(gF;OlO_2QCpYrhFp0NsKEU^noAJiv{ZjK8
zMJC5f`!ljkUJoP%CjXZ%XPhy)T&A4y!Q}Tc+Kh6OrDc_Yq`j;<W5nciAn7o<A4t|r
s-VP*lCf}D;XI%jF_JYaWa>}d@ybKJ}CL7BsODvFJV7P;1KO>Y400|IE{{R30

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 9f4ca5d2fa8c87d28f797e470cedafa61aa011b3..079f0968204f15c6a182657facb5e2039d9e6c85 100644
GIT binary patch
delta 347
zcmZ3Nb}em!M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLnBLL
zvx)olnK*PdesExBY@BS!@`iE4WI5JLjOLR+vl?$!VSC3bD!{-Fv>p|7Pp%ghXPh(H
zUPPR+9>ks;CQ`u;b<E^*A`WZ};y@i!HVcayOE4x(cGvyScw@4=UOnT5$;W}@i^=Z#
z`<Wy(CvzC=V_Y%$xPd#P%;bJu@yTk23XD3F-3{#-XH0H4tY>^Mncb+J@yFzTBXiCb
V!VpJnoqQh1)6j<S?f~`40|0GcSvUXy

delta 340
zcmcbXwk~aggs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$ujWa4psrWe{9e>gBRH8W0TWD%KsfW>2S0t?&Z
zIV_!wn<lHVUSc-WGo1XB)p)ZW+Z$d{1qODYD^Nkp<oUwltW$x40uvvKOfDBGpZrzC
zfmIwRFmduiR^iQlq6!j>4wLhB|1<8GoUd2UxMA{pAbDbPzW#ou9~zSl4E8a0Onz_R
zKDo?DVzQs10;AsKd_#N2iplE@>lqJB);DTrd@y;tkvZoCVTjf1Cik<8PUbOIV&s^t
HZ>$ag7;IMm

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index 7b563c6b74b80e6a6210005129a38ac4e2259e39..5cf2c97606c7686ccbe5680d56c89e2f886f0a9b 100644
GIT binary patch
delta 384
zcmZ3MdMtH<M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLnCub
zqlx?V87nrvU(3YUIC(Df8^#TjyI8I<nomw<)!jUe^$V}400TSFc2v+knO|63at=^X
zfPoQJ3dpMm$xc2eT)_@?-DEcr2Q~(ApwyJfA6bPr&l6FQV7xGSzs`R~kIDOW>nHEi
z<CyHGSHT!DdB5I%#*WGL`uiCrCfgghPyWXyHhGSL662i7`wi@wIJ71i+A*G(Y;S1K
w7%;is(4OfB%j5%wcAN^V5Lf(|%x+}PDIpBuZJqp|O>}aMkrLyK$@NC+0F5YLxBvhE

delta 370
zcmX?>x-4~qgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8%1(V&ZXq#)OUE*D^6RGfpmKN}8O{%rlvTg=ew?
zOCjT?$&*;FF`MZbPR?Z2Wd&N!z_58L>sMY;1qOC751DA0%r7j?Iu$4+F!7<t<mbZW
zlT$?;SjB+?6DNOU72dp0L_vaa$K?Au{}~M?-`A~Y)R-KvS3fyUk7M#Py&a4NljrO2
zXJnWhZ{W@-H~BxC=;S>HN{sU+-#4&l`k*;k!O)KJ!sK{Edq#`N^9}8p7+5DiFtp>;
ffH;fc!DMwKb50Inh>O;N_173FF*Zz|Z=?<Yv}{|Z

diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
index f9e4aa47cc2442bf7b788f0af4ad6fb0e38887e0..87f299b58914c794798dea0906928dad30881da7 100644
GIT binary patch
delta 362
zcmdm%b}wy$M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLnBKQ
zlZpHFnFMq;esExBY@BS!@`iE4WI5JLjOLR+vl?$!Vf)4_D!{-Fv>p|7Po6I<E;$D%
zD8RsoDh1@#gJdViiBzydoj3WKhyxpgI8bWJ<VH5(&3d8=5{wy>{dNB{KA7yUSI>B3
z@_8WnVY0veeny4K{094h&Ny%2KDm!wY_g7_5~I#!e?xo51(W*?>lt56<~M3*{4sgD
bkvZoEVTk2hC-<|9PJUyg#Aq;?-&h?0(~(*Q

delta 342
zcmcbYwk>Ufgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$uzXyS2wrVrX1e>gBRH8W0TWD%KsfW>2S0t?&Z
zIV_!wn<lHVUSc-WGo1XB)p)ZW+ZSF@1qODYD^Nkp<bGjs#;KG2MZ_o9iBwGfE8@T^
z4pcI6@<LYO&0(Sn5{w>`%XR-V9++INSI@X(@^>J4VRE_teny7L<_7y2Crtis;La#F
zdB3js<S;`8M!m`9hW3mNleZhzGoF}iZq&~BVDf$=bIuvU5R2DM{tx5{XhV2+fcoSC
D0OnWJ

diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf.a
index f118261ae10dd12fc2d640626093d7183bfa61b5..57101ee2852707838d13007487c2046c54cf8d69 100644
GIT binary patch
delta 384
zcmZ3MdMtH<M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLnCub
zqlx?V87nrvU(3YUIC(Df8^#TjyI8I<nomw<)!jUe^$V}400TSFc2v+knO|63at=^X
zfPoQJ3dpMm$xc2eT)_@?-DEcr2Q~(ApwyJfA6bPr&l6FQV7xGSzs`R~kIDOW>nHEi
z<CyHGSHT!DdB5I%#*WGL`uiCrCfgghPyWXyHhGSL662i7`wi@wIJ71i+A*G(Y;S1K
w7%;is(4OfB%j5%wcAN^V5Lf(|%x+}PDIpBuZJqp|O>}aMkrLyK$@NC+0F5YLxBvhE

delta 370
zcmX?>x-4~qgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8%1(V&ZXq#)OUE*D^6RGfpmKN}8O{%rlvTg=ew?
zOCjT?$&*;FF`MZbPR?Z2Wd&N!z_58L>sMY;1qOC751DA0%r7j?Iu$4+F!7<t<mbZW
zlT$?;SjB+?6DNOU72dp0L_vaa$K?Au{}~M?-`A~Y)R-KvS3fyUk7M#Py&a4NljrO2
zXJnWhZ{W@-H~BxC=;S>HN{sU+-#4&l`k*;k!O)KJ!sK{Edq#`N^9}8p7+5DiFtp>;
ffH;fc!DMwKb50Inh>O;N_173FF*Zz|Z=?<Yv}{|Z

diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
index 666f812ba1df511b8400bbd82ccf7c45e970e7a6..a25a69d6b38d616c1d4b2bb9d1fbbef4daae877c 100644
GIT binary patch
delta 362
zcmdm%b}wy$M2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)NM$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJL_xvO$kN1Q
z;(mQ50iBH>9GDp!CmXW7VcalTj`b3w`Q*>6#+y~xzVV6*Ft7uyM+M!J=L?HV&H)Mv
zFfgJ@0eSTx*~xJt73@&wO}-}Lz{VgBl$tWRkxh8Bo~VKZW5#5E-T#aaCj0BvGv1hd
z9!P$e?61F{QDHK_!G54K&KtN-?qe65tYfIes59B$(4KL@<bK0?#ut<MjoKN1OrCCJ
a&bdJtV)@p|{p_NX-xw(|8cgOlRtEsp+*$_!

delta 342
zcmcbYwk>Ufgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$uzXyS2wrVrX1e>gBRH8W0TWD%KsfW>2S0t?&Z
zIV_!wn<lHVUSc-WGo1XB)p)ZW+ZSF@1qODYD^Nkp<bGjs#;KG2MZ_o9iBwGfE8@T^
z4pcI6@<LYO&0(Sn5{w>`%XR-V9++INSI@X(@^>J4VRE_teny7L<_7y2Crtis;La#F
zdB3js<S;`8M!m`9hW3mNleZhzGoF}iZq&~BVDf$=bIuvU5R2DM{tx5{XhV2+fcoSC
D0OnWJ

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
index 551290601d766e72dd728ade2b786873945eb604..c1e05fc555f74d31e44f6b59d2a66be59246119e 100644
GIT binary patch
delta 382
zcmZ3NdM<T>M2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)NM$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJL_xvO$il#2
z;(mR`hK=vnGBGwzp3D4(al_;;mTQdWlapC>H&0{z!z(Jlzz(z>6?9MjFC@-5XYzhw
zamIQOd-65m3U;VlCi{svurY`ObxhejS;Sa^@y6uiI{z61CLh<WXY`otu2;{PF!{LN
ze#Qxt+x7P|Dol1aaA%a6%&#jxd6|I%(A47w_Dlj=lQ|6S7*9-gH?(JrnA~n?&-nus
t5<s8}R4PB&$WVkA#M58}kqit!Ci5Gab1Dc!cv~m?19=OyAiO&u9RL(xU!ed1

delta 380
zcmX??x-NBsgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8%1}Y~pc!#*B^M*D^6RGfpmKN}8O{%rlvTg=ew?
zOCjT?$&*;FF`MZbPR?Z2Wd&N!z_58L>t9|`1qOC751DA0{9j0%aq8s#!s3(P30F+c
z6>(q{2P&Ajd9#SI1ml6p&vpJYT1<YfThC}PIbE-w(PQ#+z5R?8lb7r7XXKciZs5)+
zH(6g-eDW~^1;%-kpBvaS{m`7OVQ9yAVRE{mJ)^_q<%ag03=n59=mM3>PYyB^;RU(D
d04n-mvc8cyr+_fTUF#<219=@<5Z)b-4gi-!S+@WH

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index e7e7490912dff323b1ded4cbf400b02e6078c182..587320f69d86f75a7c283cdcb2a3fb7040479cb5 100644
GIT binary patch
delta 356
zcmdm%bT4UwM2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLn9Mo
zqlx?VnFO>pe&AweZDeF*W|~~c5;<9bg>7;iODE%o$uC%LFq%(3%xb*(3#%Wmr~m^y
z&?%^(e)4)DamERg^M%D3i$UzkZNfS1P=`(aB<#Y*AP&^gJ2{X|c(I>|IAh0Tf9?NF
z3?h>Qbm|ySOg^tu&-h@nzwUlUg~|MS`+=68*K?m7$1XNmM_-BY&t!jnd&UKm`}OM?
lUrgpVXlD$VJl(*Y^M(+_6)Pvlvx`oCW1z%nFqz*_9RM<TTvGr5

delta 337
zcmcbYv@L0Zgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$EVVB&ForVpAMe{eA~H8V~wV9A|a$Wq6+Y4Qh_
z8_Z^UhLcaS8gKr`>ccClz`zc)9TikeJ})HB+6fdCnD|g+@^azq$&w;2tl~g{uE`Iz
zgcp~Ih%;tPF4z9g^gwuWg-#vgipk$~>KPAAF4x`9$S~PlZ$ION$=~(d8RaJb*A|}~
yrmw*GZ*sZ5J!8Y<?fUhMCnlR4v@=>v-fv*ec|Zta_oB)Ffjj|C2=5M1pF9AogI8Pt

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index b2763d0bf7849d656e2c1e61d2a4e3169eb74bb4..fb5d641717a8692250fbc6714cf61ded14ea22e3 100644
GIT binary patch
delta 372
zcmdm%cr9^)M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLn9+g
zvx)ol89O$<Z)aj^WSpGHlr;Gkb0_15$tf&%7|ka;v+8axWA)(`6<}ZoIsp~bPu3R_
zXPhwkJ&-I0u_v<$=deQ^G`UFFg^fWRsH1oCLl)u1=Y++X7=$NZ(E7(%G5Nf9{p52x
z9FxOzDi|XspV!&XIAe0Z?tVs%$^Lroj53q`*+eI=(NkiqnS5T)o>5{lzrH==ipl;!
pGGTH*ki0SZyuLjr11rQm0h7fI%sB&uAiR}e-8lwIKpp)C>HwuPUibh2

delta 350
zcmcbXxGiylgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$Q#XyS2w#)6IC+nE@fC)YE-Vcax1hvg2lnV#Wf
zPgY%4pnVJsn@d@Jc|{c%*ugwxqGGbXkT_%K<o812ljVeSCQlT0VHF1|=$d?yRe13`
zVR5DxLX$se{bNj+{9e1BQDbtxPCcW;<o7!J85<_A*WJ%3Fgah(ol$P`eKyg_XY`a9
z>n6X~vu9+Otgmm+xM6ZWko1_m9!Nfz{9fOllLO)&28+q&2Iia&LJ+4c0_*NEP-2`g
IdA)%;08yP*)c^nh

diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf.a b/riscv-rt/bin/riscv64imf-unknown-none-elf.a
index 93335899af944d1cf29b46fa445f201089934505..a9ebfeda6dc9c259906bb08890082cf290732875 100644
GIT binary patch
delta 356
zcmdm%bT4UwM2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLn9Mo
zqlx?VnFO>pe&AweZDeF*W|~~c5;<9bg>7;iODE%o$uC%LFq%(3%xb*(3#%Wmr~m^y
z&?%^(e)4)DamERg^M%D3i$UzkZNfS1P=`(aB<#Y*AP&^gJ2{X|c(I>|IAh0Tf9?NF
z3?h>Qbm|ySOg^tu&-h@nzwUlUg~|MS`+=68*K?m7$1XNmM_-BY&t!jnd&UKm`}OM?
lUrgpVXlD$VJl(*Y^M(+_6)Pvlvx`oCW1z%nFqz*_9RM<TTvGr5

delta 337
zcmcbYv@L0Zgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$EVVB&ForVpAMe{eA~H8V~wV9A|a$Wq6+Y4Qh_
z8_Z^UhLcaS8gKr`>ccClz`zc)9TikeJ})HB+6fdCnD|g+@^azq$&w;2tl~g{uE`Iz
zgcp~Ih%;tPF4z9g^gwuWg-#vgipk$~>KPAAF4x`9$S~PlZ$ION$=~(d8RaJb*A|}~
yrmw*GZ*sZ5J!8Y<?fUhMCnlR4v@=>v-fv*ec|Zta_oB)Ffjj|C2=5M1pF9AogI8Pt

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf.a
index 2c75f544ddb0c7300f4d2ed5e35df1c002848305..680159a2076f2ccec2d9ff6072b185a9a6111863 100644
GIT binary patch
delta 394
zcmdm&crS5+M2Ml8v6->CiJ_&rf`Wkp2q2RR3g#AIK_HR9#lXP80>qP$aeQ$}Vo?c0
zVp2YkOi4{kEX^sIn5t^VP?TAmT&7!8qL;4^HUZfpQv*Ywm=V|}Ljwad6B7jmLnC7Y
zlZpHF87FLf-_FF;$T&HXDQWU8=1#^9lT%pkFq%(xX4TzX#u~yaD!{-FbOI`<pX@Ir
z&N=}oC@{HEN0_k~#GlM3oWl-v)Z{8*7d8fQpn~4X4_Sm4UlSH*;t-yEL+c-7!{qDQ
z^^6{q!*%Kz6DD8R+0VFO@^sz(j0Tg#_1qa{Cd=!HPu`}dz*sZ+x}H6w!enuMd&U)$
z!+~VR<mvkMoHszB0tC81mGYCF^hG9rU}53pV1<YVOqMq==Zp}7@K#Qa2l6&(KzMgR
FIsoQOU?Knj

delta 373
zcmcbYxG!;ngs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$QbVB&Fo#)^&K+nE@fC)YE-Vcax1hvg2lnV#Wf
zPgY%4pnVJsn@d?kc|{c%*ugwxqGGbYkT`26P)K0nLy^hq!r7B&3cIk10|mM!Cu#{V
z{w6HW^g(Fy53PTU8I!+j*E1SSF4w7N^qBlzXFp@d<n6lq86_r{>$x+^O}5t&pL|VE
zfw6A#cRhPXj>+cw_KX`QmjlUw$=mhqIUj%m00?w}D&;39>5EJ*&|={ffH;xCVzRw~
WIj4sZM9ref^+4VX4G8ZJNCyCO*jMTR

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
index f9d11c3b73af89725cbc60f97cc39d0a960d86c8..d4f5169cd1c008f19a22a88d0e0a4ec3891589fd 100644
GIT binary patch
delta 366
zcmdm&^ekzDM2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)NM$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJL_xvO$i&28
z;(mQ539XGExR_ZR85x<GCKs|qP8MKcn;gf|$+%(i3zi#<=93Sz8gKr>8pbOsz`zc4
z3M#0dd|pVLbplXOU^1hwFk>-@Ke<mhhaKv;$-jhM*cilt3VJ6W)Dm7CCL+!_VRE?k
ze<lu*$q_nrj29+f*QsZGF*#g!KcmKEalQSFJ0@S(b7z#9JYQFSvYoyJ<Dbdl`u2<~
pCQsL|XZ$c(+@PH?VDfwebIu1s5Vx$Hd>_cO(1h^rOrEbJ4*;-nUfTcw

delta 330
zcmaEsv@dCbgs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$EVV&ZXqrXQLce{eA~H8V~wV9A|a$Wq6+Y4Qh_
z8_Z^UhLcaS8gKr`8p128z`zc)9Tike-Y+E1*g3ggSbXw2;hf2eA}*}rKqXz1A8H9N
zt`iYwESOxc{h#TD@Z<)aI>rr?|LfE<o|s&(yPuI`vc2AZ#u=0U>$x+^O}@`2IypvP
viSgg$dVPDwj>-G=>lrUhwl`>Jw3vL{z?}1h5X9m|V3jh4N{kYd?G4od-^f;G

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
index b991498b3b9e1e7e2609cc8ef5721e52f5e3e160..8141df3e22cfa412f1f8d7f556a78eca90035e8b 100644
GIT binary patch
delta 372
zcmX?>_$+aPM2Ml8v6->CiJ_&1f`Wkp2q2RR3g$p@2uR>!U|?VY;z`IjzPKc@sDvRg
zDIZ9tq^2d7=9ElKRW)NM$}CPU(=95|%hw0%N4Ch+zz`^A1h&c0z`)GJL_xvO$k@<m
z;(mR`85`fXGch$XPEKS>ntY47lX1i36qY-T=98USbvKu>#_);?Ft7uifC}m-+Y5;^
zPMG{3NEU<Glf{H{*r5)Z+$8M6#vl&V(L4Dei}2!m!s1K<!jm6p{bTHyd|$hM@;x1n
z$!R(jj2V;f>+EM-F?qi3enyMQ@p|rzGLz%kL?`djQ(~-{d|%I=QDd^azCBPyJdiAy
pJReBjn0#N~o>PDo;+}xX>IUYV2|^IwO0e!410}{Cljj?#0|1SyVNU=6

delta 349
zcmaEscr0;(gs*`D0zlZvq=JGuTtNaC0|NsK5O*Qt_~Mepq7sJ0q<kPbF-O(3D6=@Z
zOt+{+FJB*QGF(59hitT&i3wQV(8$QbV&ZXq#)ggG+nE@fC)YE-Vcax1hvg2lnV#Wf
zPgY%4pnVJsn@d?^c|{c%*ugwxqGGbWkT_%K<o`nAll6piCNC6rVHF1|=$ibHRe13~
zVR5D(LX))rF&0ezuU*e*F}Yr+o-ttZf1Uk|6DIH1-Os2nxn9qmQEu{kHqps<^pqIu
zCjZy7XB3!huW!$|VRAi?jF`M1NIsbSU*Dcn0^%G7i^=W==9~dS5SJ_h>z-qv#JFJc
Hegky?nJ8F1

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index d319d097..e3b5ff4b 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -34,6 +34,12 @@ PROVIDE(_setup_interrupts = default_setup_interrupts);
 */
 PROVIDE(_mp_hook = default_mp_hook);
 
+/* # Start trap function override
+  By default uses the riscv crates default trap handler
+  but by providing the `_start_trap` symbol external crates can override.
+*/
+PROVIDE(_start_trap = default_start_trap);
+
 SECTIONS
 {
   .text.dummy (NOLOAD) :
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 29c35d7e..63da950d 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -392,6 +392,7 @@ pub unsafe extern "C" fn start_rust() -> ! {
 /// Registers saved in trap handler
 #[allow(missing_docs)]
 #[repr(C)]
+#[derive(Debug)]
 pub struct TrapFrame {
     pub ra: usize,
     pub t0: usize,
@@ -496,8 +497,8 @@ extern "C" {
 
 #[doc(hidden)]
 pub union Vector {
-    handler: unsafe extern "C" fn(),
-    reserved: usize,
+    pub handler: unsafe extern "C" fn(),
+    pub reserved: usize,
 }
 
 #[doc(hidden)]

From f1f3b63cde1a2961f93088493ee71fcb3897b1ea Mon Sep 17 00:00:00 2001
From: parkero <7399144+parkero@users.noreply.github.com>
Date: Tue, 25 Jan 2022 10:40:22 -0700
Subject: [PATCH 166/234] Update CHANGELOG.md

---
 riscv-rt/CHANGELOG.md | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index a62fb7ae..ff2ccf0d 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Enable float support for targets with extension sets F and D
+- Add ability to override trap handling mechanism
+
+### Changed
+
+- Update `riscv` to version 0.7
+- Update `quote` to version 1.0
+- Update `proc-macro2` to version 1.0
+- Update `rand` to version to version 0.7.3
+
 ## [v0.8.0] - 2020-07-18
 
 ### Changed

From 6aadc508528b4133185c00bde201dced388e1ea7 Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Tue, 25 Jan 2022 16:26:53 -0800
Subject: [PATCH 167/234] release v0.8.1

---
 riscv-rt/CHANGELOG.md | 5 ++++-
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index ff2ccf0d..02775149 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.8.1] - 2022-01-25
+
 ### Added
 
 - Enable float support for targets with extension sets F and D
@@ -63,7 +65,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1..HEAD
+[v0.8.1]: https://github.com/rust-embedded/riscv/compare/v0.8.0...v0.8.1
 [v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.2...v0.8.0
 [v0.7.2]: https://github.com/rust-embedded/riscv/compare/v0.7.1...v0.7.2
 [v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index cc928a81..a9cb9176 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.8.0"
+version = "0.8.1"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

From 3c681802de9a7fe3a270cae53718823752aff284 Mon Sep 17 00:00:00 2001
From: Taiki Endo <te316e89@gmail.com>
Date: Sat, 23 Apr 2022 09:48:27 +0900
Subject: [PATCH 168/234] Update riscv to 0.8 and remove inline-asm feature

This also updates MSRV to 1.59.
---
 riscv-rt/.github/bors.toml         | 2 +-
 riscv-rt/.github/workflows/ci.yaml | 4 ++--
 riscv-rt/CHANGELOG.md              | 9 +++++++++
 riscv-rt/Cargo.toml                | 6 ++----
 riscv-rt/README.md                 | 2 +-
 riscv-rt/src/lib.rs                | 2 +-
 6 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/riscv-rt/.github/bors.toml b/riscv-rt/.github/bors.toml
index cce15496..b50b7c62 100644
--- a/riscv-rt/.github/bors.toml
+++ b/riscv-rt/.github/bors.toml
@@ -3,6 +3,6 @@ delete_merged_branches = true
 required_approvals = 1
 status = [
     "ci-linux (stable)",
-    "ci-linux (1.42.0)",
+    "ci-linux (1.59.0)",
     "Rustfmt"
 ]
diff --git a/riscv-rt/.github/workflows/ci.yaml b/riscv-rt/.github/workflows/ci.yaml
index 7d68c697..94d99f49 100644
--- a/riscv-rt/.github/workflows/ci.yaml
+++ b/riscv-rt/.github/workflows/ci.yaml
@@ -11,8 +11,8 @@ jobs:
     continue-on-error: ${{ matrix.experimental || false }}
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.42.0
-        rust: [nightly, stable, 1.42.0]
+        # All generated code should be running on stable now, MSRV is 1.59.0
+        rust: [nightly, stable, 1.59.0]
 
         include:
           # Nightly is only for reference and allowed to fail
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 02775149..f04a2c8f 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update `riscv` to version 0.8
+- Update Minimum Supported Rust Version to 1.59
+
+### Removed
+
+- Remove `inline-asm` feature which is now always enabled
+
 ## [v0.8.1] - 2022-01-25
 
 ### Added
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index a9cb9176..5bcda5f6 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,7 @@
 [package]
 name = "riscv-rt"
 version = "0.8.1"
+rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
@@ -10,12 +11,9 @@ license = "ISC"
 
 [dependencies]
 r0 = "1.0.0"
-riscv = "0.7"
+riscv = "0.8"
 riscv-rt-macros = { path = "macros", version = "0.1.6" }
 
-[features]
-inline-asm = ["riscv/inline-asm"]
-
 [dev-dependencies]
 panic-halt = "0.2.0"
 
diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index 276c17d0..bf5837b0 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -12,7 +12,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.42.0 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 63da950d..50b86cd1 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -2,7 +2,7 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.42 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
 //!
 //! # Features

From ab70e9fab80b32df1159e90af1c84438f6fc293b Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 23 Apr 2022 13:05:46 +0300
Subject: [PATCH 169/234] Fix links in changelog

---
 riscv-rt/CHANGELOG.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index f04a2c8f..10f01308 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -75,8 +75,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 
 [Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1..HEAD
-[v0.8.1]: https://github.com/rust-embedded/riscv/compare/v0.8.0...v0.8.1
-[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.2...v0.8.0
-[v0.7.2]: https://github.com/rust-embedded/riscv/compare/v0.7.1...v0.7.2
-[v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
-[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0
+[v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
+[v0.8.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...v0.8.0
+[v0.7.2]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...v0.7.2
+[v0.7.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...v0.7.1
+[v0.7.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.6.1...v0.7.0

From 5fcb5ef8558cf867a7d5203309491bf0615654f0 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 23 Apr 2022 13:10:00 +0300
Subject: [PATCH 170/234] Update copyright years

---
 riscv-rt/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index bf5837b0..6db52456 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -17,7 +17,7 @@ compile with older versions but that may change in any new patch release.
 
 ## License
 
-Copyright 2018 [RISC-V team][team]
+Copyright 2018-2022 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice

From 5c8b061a716fd108350ea5698f977b679c55cebf Mon Sep 17 00:00:00 2001
From: Scott Mabin <scott@mabez.dev>
Date: Fri, 10 Jun 2022 15:41:29 +0100
Subject: [PATCH 171/234] Don't use a random hash ident, instead use the crate
 prefixed symbol.

---
 riscv-rt/CHANGELOG.md      |  1 +
 riscv-rt/macros/Cargo.toml |  5 -----
 riscv-rt/macros/src/lib.rs | 45 ++------------------------------------
 3 files changed, 3 insertions(+), 48 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 10f01308..f8e6b3c6 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Update `riscv` to version 0.8
 - Update Minimum Supported Rust Version to 1.59
+- The main symbol is no longer randomly generated in the `#[entry]` macro, instead it uses `__risc_v_rt__main`.
 
 ### Removed
 
diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index 511e681a..ceaaf6c5 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -22,8 +22,3 @@ proc-macro2 = "1.0"
 [dependencies.syn]
 version = "1.0"
 features = ["extra-traits", "full"]
-
-[dependencies.rand]
-version = "0.7.3"
-default-features = false
-features = ["small_rng"]
diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 96fdd2cd..5767d2b1 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -1,7 +1,6 @@
 #![deny(warnings)]
 
 extern crate proc_macro;
-extern crate rand;
 #[macro_use]
 extern crate quote;
 extern crate core;
@@ -10,13 +9,7 @@ extern crate proc_macro2;
 extern crate syn;
 
 use proc_macro2::Span;
-use rand::Rng;
-use rand::SeedableRng;
-use std::sync::atomic::{AtomicUsize, Ordering};
-use std::time::{SystemTime, UNIX_EPOCH};
-use syn::{parse, spanned::Spanned, Ident, ItemFn, ReturnType, Type, Visibility};
-
-static CALL_COUNT: AtomicUsize = AtomicUsize::new(0);
+use syn::{parse, spanned::Spanned, ItemFn, ReturnType, Type, Visibility};
 
 use proc_macro::TokenStream;
 
@@ -90,13 +83,12 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     // XXX should we blacklist other attributes?
     let attrs = f.attrs;
     let unsafety = f.sig.unsafety;
-    let hash = random_ident();
     let stmts = f.block.stmts;
 
     quote!(
         #[export_name = "main"]
         #(#attrs)*
-        pub #unsafety fn #hash() -> ! {
+        pub #unsafety fn __risc_v_rt__main() -> ! {
             #(#stmts)*
         }
     )
@@ -176,36 +168,3 @@ pub fn pre_init(args: TokenStream, input: TokenStream) -> TokenStream {
     )
     .into()
 }
-
-// Creates a random identifier
-fn random_ident() -> Ident {
-    let secs = SystemTime::now()
-        .duration_since(UNIX_EPOCH)
-        .unwrap()
-        .as_secs();
-
-    let count: u64 = CALL_COUNT.fetch_add(1, Ordering::SeqCst) as u64;
-    let mut seed: [u8; 16] = [0; 16];
-
-    for (i, v) in seed.iter_mut().take(8).enumerate() {
-        *v = ((secs >> (i * 8)) & 0xFF) as u8
-    }
-
-    for (i, v) in seed.iter_mut().skip(8).enumerate() {
-        *v = ((count >> (i * 8)) & 0xFF) as u8
-    }
-
-    let mut rng = rand::rngs::SmallRng::from_seed(seed);
-    Ident::new(
-        &(0..16)
-            .map(|i| {
-                if i == 0 || rng.gen() {
-                    ('a' as u8 + rng.gen::<u8>() % 25) as char
-                } else {
-                    ('0' as u8 + rng.gen::<u8>() % 10) as char
-                }
-            })
-            .collect::<String>(),
-        Span::call_site(),
-    )
-}

From 63a9486699164d08ade5e2417c1031e630512333 Mon Sep 17 00:00:00 2001
From: Simon Sapin <simon.sapin@exyr.org>
Date: Thu, 23 Jun 2022 06:26:07 +0200
Subject: [PATCH 172/234] Use std::fs::write in build.rs

---
 riscv-rt/build.rs | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 9801b190..470479cf 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -4,7 +4,6 @@ extern crate riscv_target;
 use riscv_target::Target;
 use std::env;
 use std::fs;
-use std::io::Write;
 use std::path::PathBuf;
 
 fn main() {
@@ -29,10 +28,7 @@ fn main() {
     }
 
     // Put the linker script somewhere the linker can find it
-    fs::File::create(out_dir.join("link.x"))
-        .unwrap()
-        .write_all(include_bytes!("link.x"))
-        .unwrap();
+    fs::write(out_dir.join("link.x"), include_bytes!("link.x")).unwrap();
     println!("cargo:rustc-link-search={}", out_dir.display());
 
     println!("cargo:rerun-if-changed=build.rs");

From 89c97b4937e7346902c06cdc344cbbc7ab4ff6e6 Mon Sep 17 00:00:00 2001
From: Simon Sapin <simon.sapin@exyr.org>
Date: Thu, 23 Jun 2022 06:26:22 +0200
Subject: [PATCH 173/234] cargo:rerun-if-changed=build.rs is redundant

https://doc.rust-lang.org/cargo/reference/build-scripts.html#cargorerun-if-changedpath
---
 riscv-rt/build.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 470479cf..4f9bf75c 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -30,7 +30,5 @@ fn main() {
     // Put the linker script somewhere the linker can find it
     fs::write(out_dir.join("link.x"), include_bytes!("link.x")).unwrap();
     println!("cargo:rustc-link-search={}", out_dir.display());
-
-    println!("cargo:rerun-if-changed=build.rs");
     println!("cargo:rerun-if-changed=link.x");
 }

From 3c50674beae2fd735afd833b6b7d4960c4afe113 Mon Sep 17 00:00:00 2001
From: Simon Sapin <simon.sapin@exyr.org>
Date: Thu, 23 Jun 2022 06:27:35 +0200
Subject: [PATCH 174/234] Printing cargo:rustc-link-search=$OUT_DIR twice is
 redundant

---
 riscv-rt/build.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 4f9bf75c..66c30e12 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -24,7 +24,6 @@ fn main() {
         .unwrap();
 
         println!("cargo:rustc-link-lib=static={}", name);
-        println!("cargo:rustc-link-search={}", out_dir.display());
     }
 
     // Put the linker script somewhere the linker can find it

From 17e0aa2453d1ac2ec9a2d61b0320caf690b141f1 Mon Sep 17 00:00:00 2001
From: Simon Sapin <simon.sapin@exyr.org>
Date: Thu, 23 Jun 2022 06:30:40 +0200
Subject: [PATCH 175/234] Rerun the build script if the bin/{}.a archive has
 changed

---
 riscv-rt/build.rs | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 66c30e12..2c307900 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -14,15 +14,10 @@ fn main() {
     if target.starts_with("riscv") {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imfdc");
+        let archive = format!("bin/{}.a", target.to_string());
 
-        let target = target.to_string();
-
-        fs::copy(
-            format!("bin/{}.a", target),
-            out_dir.join(format!("lib{}.a", name)),
-        )
-        .unwrap();
-
+        fs::copy(&archive, out_dir.join(format!("lib{}.a", name))).unwrap();
+        println!("cargo:rerun-if-changed={}", archive);
         println!("cargo:rustc-link-lib=static={}", name);
     }
 

From 57219ef1a0a93b50d2d7487ec644aa88dc260ce9 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sat, 25 Jun 2022 10:23:05 +0300
Subject: [PATCH 176/234] Pass a0..a2 to main()

---
 riscv-rt/Cargo.toml                          |   2 +-
 riscv-rt/asm.S                               |  18 +++----
 riscv-rt/bin/riscv32i-unknown-none-elf.a     | Bin 8226 -> 7958 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a    | Bin 8082 -> 7826 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a    | Bin 8230 -> 7962 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a   | Bin 8086 -> 7830 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a   | Bin 8234 -> 7966 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a  | Bin 8094 -> 7838 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a    | Bin 7914 -> 7638 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a   | Bin 7778 -> 7514 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a   | Bin 7918 -> 7642 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a  | Bin 7786 -> 7522 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a  | Bin 7926 -> 7650 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a | Bin 7790 -> 7526 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a     | Bin 13142 -> 12766 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a    | Bin 12998 -> 12622 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a    | Bin 13150 -> 12766 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a   | Bin 12998 -> 12630 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a   | Bin 13150 -> 12774 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a  | Bin 13006 -> 12638 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a    | Bin 12638 -> 12254 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a   | Bin 12502 -> 12134 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a   | Bin 12638 -> 12262 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a  | Bin 12510 -> 12142 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a  | Bin 12646 -> 12270 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a | Bin 12518 -> 12142 bytes
 riscv-rt/macros/Cargo.toml                   |   2 +-
 riscv-rt/macros/src/lib.rs                   |  52 ++++++++++++++++---
 riscv-rt/src/lib.rs                          |   6 +--
 29 files changed, 57 insertions(+), 23 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 5bcda5f6..167d7c65 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -12,7 +12,7 @@ license = "ISC"
 [dependencies]
 r0 = "1.0.0"
 riscv = "0.8"
-riscv-rt-macros = { path = "macros", version = "0.1.6" }
+riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]
 panic-halt = "0.2.0"
diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 910d3593..5dff38ac 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -58,9 +58,7 @@ _abs_start:
     li  x7, 0
     li  x8, 0
     li  x9, 0
-    li  x10,0
-    li  x11,0
-    li  x12,0
+    // a0..a2 (x10..x12) skipped
     li  x13,0
     li  x14,0
     li  x15,0
@@ -87,23 +85,23 @@ _abs_start:
     .option pop
 
     // Check hart id
-    csrr a2, mhartid
+    csrr t2, mhartid
     lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    bgtu a2, t0, abort
+    bgtu t2, t0, abort
 
     // Allocate stacks
     la sp, _stack_start
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)
 #ifdef __riscv_mul
-    mul t0, a2, t0
+    mul t0, t2, t0
 #else
-    beqz a2, 2f  // Jump if single-hart
-    mv t1, a2
-    mv t2, t0
+    beqz t2, 2f  // Jump if single-hart
+    mv t1, t2
+    mv t3, t0
 1:
-    add t0, t0, t2
+    add t0, t0, t3
     addi t1, t1, -1
     bnez t1, 1b
 2:
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 50197c5abaee32ad321f672f4c368cb818d6b4f0..4749033ad768efb6016211199dd2718e23a5f47c 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf.a b/riscv-rt/bin/riscv32if-unknown-none-elf.a
index 18ec3f29d7fdb4c7e0ee197ec18013bc76df0a13..e39ab3aceb344039fc850153a077f98c3dc93f59 100644
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diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
index 41068e68c51645dd67672ecc67df34f9dd95dab9..46718e187d0f40eb8ae3c6be7bd2fb9daa2913fa 100644
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diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 94f45690c9278c5a78181d3a0ff8d64774a0eac3..25875f9eaeb0ed836696dc165fac95e07d447f50 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index f90bcc31d1add4d7055b65acea8e903a286a1a87..05296d7c7a9bec2130f36d78c5b889e8006cdacf 100644
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diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf.a b/riscv-rt/bin/riscv32imf-unknown-none-elf.a
index 2127d91edbb1f25b3d853910ee278d49a08d6171..dd9247233e086898d1be7d7fd9ec545a5e8ce6ad 100644
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diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf.a
index 0c157001829fe37ced38ec582a53f985dacb5e18..03365572871041a7bb3eb5a47861d88a030de11c 100644
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diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
index e474cce63ef867be5ceef72b35e57f6456dfe5d0..389bac4efb2c6637a6414d138a6d1831ced5ee95 100644
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diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 079f0968204f15c6a182657facb5e2039d9e6c85..37636b4654071f15d2edad5493092459e9af65b0 100644
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diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
index 87f299b58914c794798dea0906928dad30881da7..b72035b7e8d1fbc43aff68d28dc261e0592ce249 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf.a
index 57101ee2852707838d13007487c2046c54cf8d69..03855db5a063485e39b9818327fc617104434dce 100644
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diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
index a25a69d6b38d616c1d4b2bb9d1fbbef4daae877c..9bfdab632f1daabdcf74cb3d4c3464e8ac587058 100644
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diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
index c1e05fc555f74d31e44f6b59d2a66be59246119e..3aaae7a6b13fc2c92003917de3141912b59785b9 100644
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diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 587320f69d86f75a7c283cdcb2a3fb7040479cb5..9674cd52e55bf53278de3439bc6ee82985151aec 100644
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index a9ebfeda6dc9c259906bb08890082cf290732875..c8a6c4505d6be4f552c5002be18ec9527847ffae 100644
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diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf.a
index 680159a2076f2ccec2d9ff6072b185a9a6111863..131ca27c95c4f81dd7e66c708b6bea51d5886355 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
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diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index ceaaf6c5..8c2d9c13 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -10,7 +10,7 @@ keywords = ["riscv", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "riscv-rt-macros"
 repository = "https://github.com/rust-embedded/riscv-rt"
-version = "0.1.6"
+version = "0.2.0"
 
 [lib]
 proc-macro = true
diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 5767d2b1..3c79864b 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -9,7 +9,7 @@ extern crate proc_macro2;
 extern crate syn;
 
 use proc_macro2::Span;
-use syn::{parse, spanned::Spanned, ItemFn, ReturnType, Type, Visibility};
+use syn::{parse, spanned::Spanned, FnArg, ItemFn, PathArguments, ReturnType, Type, Visibility};
 
 use proc_macro::TokenStream;
 
@@ -48,27 +48,49 @@ use proc_macro::TokenStream;
 pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
 
+    // check the function arguments
+    if f.sig.inputs.len() > 3 {
+        return parse::Error::new(
+            f.sig.inputs.last().unwrap().span(),
+            "`#[entry]` function has too many arguments",
+        )
+        .to_compile_error()
+        .into();
+    }
+    for arg in &f.sig.inputs {
+        match arg {
+            FnArg::Receiver(_) => {
+                return parse::Error::new(arg.span(), "invalid argument")
+                    .to_compile_error()
+                    .into();
+            }
+            FnArg::Typed(t) => {
+                if !is_simple_type(&t.ty, "usize") {
+                    return parse::Error::new(t.ty.span(), "argument type must be usize")
+                        .to_compile_error()
+                        .into();
+                }
+            }
+        }
+    }
+
     // check the function signature
     let valid_signature = f.sig.constness.is_none()
         && f.sig.asyncness.is_none()
         && f.vis == Visibility::Inherited
         && f.sig.abi.is_none()
-        && f.sig.inputs.is_empty()
         && f.sig.generics.params.is_empty()
         && f.sig.generics.where_clause.is_none()
         && f.sig.variadic.is_none()
         && match f.sig.output {
             ReturnType::Default => false,
-            ReturnType::Type(_, ref ty) => match **ty {
-                Type::Never(_) => true,
-                _ => false,
-            },
+            ReturnType::Type(_, ref ty) => matches!(**ty, Type::Never(_)),
         };
 
     if !valid_signature {
         return parse::Error::new(
             f.span(),
-            "`#[entry]` function must have signature `[unsafe] fn() -> !`",
+            "`#[entry]` function must have signature `[unsafe] fn([arg0: usize, ...]) -> !`",
         )
         .to_compile_error()
         .into();
@@ -83,18 +105,32 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     // XXX should we blacklist other attributes?
     let attrs = f.attrs;
     let unsafety = f.sig.unsafety;
+    let args = f.sig.inputs;
     let stmts = f.block.stmts;
 
     quote!(
         #[export_name = "main"]
         #(#attrs)*
-        pub #unsafety fn __risc_v_rt__main() -> ! {
+        pub #unsafety fn __risc_v_rt__main(#args) -> ! {
             #(#stmts)*
         }
     )
     .into()
 }
 
+#[allow(unused)]
+fn is_simple_type(ty: &Type, name: &str) -> bool {
+    if let Type::Path(p) = ty {
+        if p.qself.is_none() && p.path.leading_colon.is_none() && p.path.segments.len() == 1 {
+            let segment = p.path.segments.first().unwrap();
+            if segment.ident == name && segment.arguments == PathArguments::None {
+                return true;
+            }
+        }
+    }
+    false
+}
+
 /// Attribute to mark which function will be called at the beginning of the reset handler.
 ///
 /// **IMPORTANT**: This attribute can appear at most *once* in the dependency graph. Also, if you
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 50b86cd1..f1c564a2 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -361,11 +361,11 @@ extern "C" {
 /// never returns.
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
-pub unsafe extern "C" fn start_rust() -> ! {
+pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
     #[rustfmt::skip]
     extern "Rust" {
         // This symbol will be provided by the user via `#[entry]`
-        fn main() -> !;
+        fn main(a0: usize, a1: usize, a2: usize) -> !;
 
         // This symbol will be provided by the user via `#[pre_init]`
         fn __pre_init();
@@ -386,7 +386,7 @@ pub unsafe extern "C" fn start_rust() -> ! {
 
     _setup_interrupts();
 
-    main();
+    main(a0, a1, a2);
 }
 
 /// Registers saved in trap handler

From 61aaa6cc54fc87bb7b4c3a13eace6d62724b5636 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 30 Jun 2022 08:01:37 +0300
Subject: [PATCH 177/234] Add missing changelog entries

---
 riscv-rt/CHANGELOG.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index f8e6b3c6..b72ad219 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,9 +7,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Pass `a0..a2` register values to the `#[entry]` function.
+
 ### Changed
 
 - Update `riscv` to version 0.8
+- Update `riscv-rt-macros` to 0.2.0
 - Update Minimum Supported Rust Version to 1.59
 - The main symbol is no longer randomly generated in the `#[entry]` macro, instead it uses `__risc_v_rt__main`.
 

From 55b830dc3e0dc3efe912084a39a04d8b12c659ae Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Fri, 1 Jul 2022 07:41:55 +0300
Subject: [PATCH 178/234] Release v0.9.0

---
 riscv-rt/CHANGELOG.md | 5 ++++-
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index b72ad219..3378cf72 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.9.0] - 2022-07-01
+
 ### Added
 
 - Pass `a0..a2` register values to the `#[entry]` function.
@@ -80,7 +82,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1..HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.0..HEAD
+[v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0
 [v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
 [v0.8.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...v0.8.0
 [v0.7.2]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...v0.7.2
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 167d7c65..416b2046 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.8.1"
+version = "0.9.0"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]

From 01097fdd30a93db19f3ccc7b1c47b686a113673a Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Sun, 3 Jul 2022 12:04:55 +0300
Subject: [PATCH 179/234] Convert default_setup_interrupts into a Rust function

---
 riscv-rt/Cargo.toml                          |   1 +
 riscv-rt/asm.S                               |  10 +---------
 riscv-rt/bin/riscv32i-unknown-none-elf.a     | Bin 7958 -> 7712 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a    | Bin 7826 -> 7588 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a    | Bin 7962 -> 7716 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a   | Bin 7830 -> 7592 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a   | Bin 7966 -> 7720 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a  | Bin 7838 -> 7600 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a    | Bin 7638 -> 7400 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a   | Bin 7514 -> 7276 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a   | Bin 7642 -> 7404 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a  | Bin 7522 -> 7284 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a  | Bin 7650 -> 7412 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a | Bin 7526 -> 7288 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a     | Bin 12766 -> 12376 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a    | Bin 12622 -> 12248 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a    | Bin 12766 -> 12376 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a   | Bin 12630 -> 12256 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a   | Bin 12774 -> 12384 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a  | Bin 12638 -> 12264 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a    | Bin 12254 -> 11856 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a   | Bin 12134 -> 11752 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a   | Bin 12262 -> 11864 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a  | Bin 12142 -> 11760 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a  | Bin 12270 -> 11872 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a | Bin 12142 -> 11760 bytes
 riscv-rt/src/lib.rs                          |  19 +++++++++++++------
 27 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 416b2046..8fd31470 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -8,6 +8,7 @@ categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
+edition = "2018"
 
 [dependencies]
 r0 = "1.0.0"
diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 5dff38ac..956b459d 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -167,16 +167,8 @@ default_start_trap:
     addi sp, sp, 16*REGBYTES
     mret
 
-.section .text
-.global default_setup_interrupts
-
-default_setup_interrupts:
-    // Set trap handler
-    la t0, _start_trap
-    csrw mtvec, t0
-    ret
-
 /* Make sure there is an abort when linking */
+.section .text.abort
 .globl abort
 abort:
     j abort
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 4749033ad768efb6016211199dd2718e23a5f47c..8894afe85e9b8e719cf590cbffc3d1d16192c62c 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 96efa732787d6be0e93bce89631209ea5056ec06..f110f40c17b2ebc5657fac29d28926baff046ca1 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf.a b/riscv-rt/bin/riscv32if-unknown-none-elf.a
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diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf.a
index 183d20eb74840dc42179df763cf2f334f3d05028..e863bd41d8613cc8d60d735cbffe64227c76db42 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
index 46718e187d0f40eb8ae3c6be7bd2fb9daa2913fa..8fa49cec31b1711cba0e0d7b6244865cd369ee0d 100644
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diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
index de75f1571976ca64ac75739be65327f8265d059a..8c98e12cdfdd28b7516bf5873add32c367d2dc5a 100644
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diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 25875f9eaeb0ed836696dc165fac95e07d447f50..b460f2c1bb6c5f8cd789264791fe6ba52ddfa56b 100644
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diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 05296d7c7a9bec2130f36d78c5b889e8006cdacf..374f06b5eb4143392b6d136d7c951ead1c899e0f 100644
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diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf.a b/riscv-rt/bin/riscv32imf-unknown-none-elf.a
index dd9247233e086898d1be7d7fd9ec545a5e8ce6ad..929902b898ec39b611e0dc06ef38ace045c460c9 100644
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diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf.a
index 03365572871041a7bb3eb5a47861d88a030de11c..13d1f2171ccb6fab0a1f353d6202d6bde4388480 100644
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diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf.a
index 8d83c2efc301a8d708111cc9b6411bf0f4abf031..96d34eecae575ac210d9be086e37e018e152d610 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
index 389bac4efb2c6637a6414d138a6d1831ced5ee95..2403fb0e916edcabd750069b6ddef6bb6fbe284b 100644
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ABme*a

literal 7526
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diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 37636b4654071f15d2edad5493092459e9af65b0..e6cee106cb761b6b392b7fea4c7344d8abd6a0fe 100644
GIT binary patch
delta 2616
zcmZ{m|4UtE9LJyI{o=jm@P75EvphN1z3Rn#?&k6eMwb|Av`Uyi2+ekNu8bVYx+7bb
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delta 2894
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gv~Sb(L|e5V7yfJc^`hG3wrYj{s6Ses_v1DH03{EwBLDyZ

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index e2256f6f4878530113cc90c5d82e0113d179b2b5..375ecb0e3c71df739e8dd9da96029d5e69b3c029 100644
GIT binary patch
delta 2614
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T?mp{knb!Tj#5Jt-i)8-?rw5^2

delta 2881
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zkK=0b0ueNzly5A>+W}pPeey@xNJOCEv*PQD3CeZIBqN9Dv{#FBo#U)iFcgYIFHz+O
z(>p+4nucGKI^0f%Y}be}R>;9dGIHWW99LUmIf@1pbEdQjl`Gstj#l6cjGB^LFxeXE
zxq*Xf(W5ct)x+MDKb?@u=(mx>6Ig&yDgc|US-){;keqX3heD6-d(f5IS2yP|2=O)j
TbizWaxvs#Ad}}Zb@%n!ND^qQd

diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
index b72035b7e8d1fbc43aff68d28dc261e0592ce249..216a89d3fac5a709b18d11af05a94ef5fa86a636 100644
GIT binary patch
delta 2616
zcmZ{m-)kII6vyXge`GhNWPfIoG@3C@-Q8r#&bG1HLc}1&M64QU9s)KtNw*p?C82IH
z)@XuB>LNupo`8aZ78QJnPpME!!Gfg(^r4DK9%`F^K%$7yC+j(PzGEkAy=3m^+;i^v
z-aGflZ0?-g8mqJx3I`9{hiuE@KQ7+dvU&>I$<<h$VHiGsO762VVy%3fu-x>#ZFBD7
z!js&Y?L$31%mWAPm7BJi&TtZ!8h-l4;JU?Vru}MN{Y5{i&A>GKUfKApW~8R(Yeltz
zr#4;;JgcZZpP)*xo8GGp`uv7L)3r&aU#R@Fr`F_F6TG{~(bGC=A=&|^!7ONlJzxRs
z1N*@v;2?Mu90G^I5%4%T1{T3da0;9OOW-Ux2QGk1U>UpsR=`ieHSiMnCAbb=2CsnE
z!0X@*a1;CiyaoOYZh^PKZTc|~5BQ8AcIg5Ax<}9mf%RYnOn^;771a9{G%R>Kz%-Zz
zZLkL{fPG*;cmx~-kAg$sFgOAp2gkr7I0;UHGhhjv1?Rv8a0x7f7r+YED}?oO={L5~
zV^uTcoOaLYcjHD?Kc_AIot>!v_r5rh2g?7SDfcUiyr>bB5mc1^h$ZP<tVPwaa&oWF
zi0LcrtvH8^pMHzVjdaJWNPe^5Sod~i`%&HY(+e@_y(#nc`HTipr>oHfZ3q0^PGGdg
zs%*m;W>17i`!zP;lXXkQNBP_=$1`*%zJ^bYlVmbxJ^4I0U7EOln+_&(`9*jHtFR?{
z4z^$ob_;WfD4A1B^c~md=})fTp?!@x^#L8z^<ragd>Q=(*I-AObFc-sV2l4<*n-=z
zWkt)d1%t4~|Dmi{K&)kon*(Zm<7IOotR^<Tuy%s#BvEQ#^Qe4lxwP|B)Rt3?(*2a#
z%(qh)#r0X(f_mCXo6pIdq)7BFZ8=o}w)oF@{IXtB#Q&zYoT`<+P46D-4No*e)17AC
z&F$dGX;0Mkr`b2<@mtiEF`LCJMY80l!!2ogiK8}}vIH}3h*_Zdj5%I_M>M=q_pK%C
z6#59<nTY>YkKckV{?|PIG&OYYp2O>&Xn~&YH0gY2k#;(>b){3YrS9>G=`$rtblp^Y
z>26mWZ3QAx_n^9&kJE{)srq^2P5LMsQ7O8(tDV=Ge`hU~rM9e@3B{evd$K27<RXY>
zNE%$+m+Ip@Gi;&PD$QrxRIgSrlDm6~f*hM_g#oQ_847-_@QhYydWeE#S1XLrcteuE
zR#%`gQ9}#a$J8+qN!k$E#P-NE>gfCKu5b(1s9g_P)I;9e&tWbV2l};H`9DLRl_4K7
zj6P_@v_@IH{6EeR_2yD)Q7e|8aHM|sC^kGq@e{h3GsBml*UEZk81G|z1>Ngf_j9c~
zn{oubGnMaZ_2OKm6Sf(S1f1SB-RBMZMk|EUj&IO`epk7n)e1N0E-Umyp-tYDCT#tc
iO^(4E+T)1Gv3Q@J&v%6<@sVGn`FwA92xI*s+5Z6V!g{Cx

delta 2894
zcmaKu?`xY?6vyvvnzY@Lk)}`fG^}%RD@mHQOQK!Ppt1-X?Qlw!4q8}kyEfa(>XxRd
z)>&PV2~}5@dPE0yIKdYa#z3mj7n3PED6&CcOxO#R{Q*k1H!@JcbDrm$?pcf;xc77J
zIp>~xpZnu^o;yRojue|ZQ|+ma_Eb2W42wAHaQLaTW#npTgHo!R%LmS~&>Mb!G<$S-
zYP>KwnJrA^2FFeovibZ}t}v-oer$5&m9~6g*Qtb+Ce^XKqcmD7ndG7Nq}$oUdPh4e
zsV8=KEL=_|R^vPdOBI)lC|rkBqxzT)^j4LcEWVgLHmlSr%cmCBuIN8#QLpIS(pXhr
zm2p*Tm#$N)RJ&QH@2j77Tk%VORzIuhB~P3(9*=g@d5>w=F1M<t1y7J$*F7e;8l_c%
zO|XZ-W-tb}f=RF)OoN?Z2HXdBg9pJLuovtD4}(MCD0mzk2XkNnoCasWS@0}42c83q
z;016Iyaav@UID)Xm%(e`x8M)p3V0J-1#g3Qz@Ndpl;T~fv3AO;T{ZSjF>9@u8s!E3
zpaC|5O<)*o24i3=m;~FwG}sAdz<pphco6IXd%-^NFgOH`g2%yeFb5XEX>bOd1<!(W
z;5o1;)LPccrLj61tD}|QigK&Fi2l%`R)*Efx(j^XEw8=ayuwz@dPc+Ai;a)mn*WdI
z`A{Jcpi3T)%db4vh<=`l?5U6H-9eX2)d}gZdPAaktiAPS$gTYL{a&w4ODoONeo{Am
zT5oP~tJ~{Qwz9*HRVy+MZK`k7evH)s1}PDco8J}a;+5i+2@LQvuLW8{i`>_*bXi8F
z&X8_cYWeT?-NOzt)AKw|!*fqQG+LUxLPZ+6oVGN(D%s29OKVWiVRMpktK@#YLQly!
zL%%d6XwmReqv7?v;fPwK`-Vx~Ml-bry)<n!>v!m)k<f3_Ew10Czpc70n9y@H5Hv$)
z9DP@z%Uot@p1tomyxq`chV%4OuuBguZQa~er$?8v+txffONSym4h+i6oMk(gVN0{C
zl0CxBA%{Kdh(F@A(?Y~Nbi&~sad=C1$>!{J$`OCm5nr-P{0Lo)n4wo4UN3Yx3Da~d
zV)|Zlcnx|yYEo^~>zi^|o9MfUNtYvD{W9-`sZY`XM_uD6*&mS@my<Nl*5BAFEs<s}
z6Z8#Rn_^y?i+OdPevg_V{*10m8k+RUOLpI}bswK7nuwWnfpd;ItTFnGt(?zy!eLF*
z3p~<tY_vL`9UrDGEp61_a-G8NY8|Ffe493CPkh^fE!;&8X2#J~)RhL?Fb(@=rYuq|
z+NDR8Wfi-NQh^34#GC6{5w&g!bs)yWbV?uHk4O7cY^pSajA6$<kn}7v1Npp{&)^xh
zNl1D2G)?S`?(bwzrR-@*$5MI@Y1VKl&wh|?S}x^=o0vzTicZHL+uy~GN{M@rxKAz%
zi!}M?<X?#g*k&cx8M@yZZR_K9rF@s8>|iO{u<~uB8?8I_5t?X=x@XvK=b5E1+oJt)
zx+~>L%aLNaXT!>~iS_aamU}NxnnYX)tCZRmb$=pWSq^<qMmz8kw=0bnYq9$|XDtg-
zKH62u$EAvf6DB>_74H9nTa_{{BV#xFMPyy&jFx9yW}8c?9ODtm(L`czuxS4vs#%}y
ilsE0$bR)5|&W{8CwS2v3Q*wKq!awSdmgW8UhJOG$X|N>#

diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf.a
index 03855db5a063485e39b9818327fc617104434dce..352517453fc6ee3f8297f7e73682f76881a2b1dd 100644
GIT binary patch
delta 2855
zcma);T}&KR6vyxEE;q0)vb*dDyO4HTkzrwB2SnV~YM~lwOw~qf14gtEs!eU(irCbY
zDk^PAZJNbHqEV6(Uwkl4O^A*0$wZ?*nwSvdi#74VHyVBM(R1ehr%cu*@r1d*JLl`p
zoOACE8`HO5tag;k_w8|qUEAhAmf&dHLuF6N!?CDRD$LiMe=U#O%O9k6`QZbu%dvaP
z_p>w4hlhrkgKpVf{-M<NMK?#WNP-cW@R(OQMLVonYbPyR7sA%s3+pYR@lfcxwSGRb
zY*`^1ZAep87wIjn!x5#ZqSID{PU~!YL^XO@wg&A@BdSfj*t?b;(A(f{uoLV8yTKl?
z2=;?6I0z1b!(bWQ3+@9S21mdH;G^JU;6d<l@DTVUco=*dJOUmC$H8OZ40r-O1<rx<
z-~zY^E`gW9E8tbI3a)@3fveyecdxY}thg_pW{V-Yx3u&ztd)kf5sZQ{@NO^;CczY#
z0ZqTP%H!VjTdN(ow?Wf)txUhQGJV#n2)pUCR;JHdnLcYZ1iR_8R;JHdnLcY}`mB}d
zvsNSUH+|O1^jRy@XRS=1wK9Fy>JaM1`&uIDQZY{Rx{-JC8Zw#AH!81w{&@)4y*RF@
z=XWPw{7olf=mbvE|B95elt5g<^vX)mJIOTtmB?FBIicaOO41VvIg|0N<LJ$@IFshd
zBFfvFe1flg-YYfU_rUv#JTGT$k?b^>NYUYj2;ZmVzCElmHE~KEVNF~`=-K30Sn78z
zIY}GwIK^7?bhLG~5DbuKIu}rIH9TqK@lE<XRcd|@8o~3lKb38sfhNyfq`T53YmpvI
zm+042jLxPzt@HE=-$m0g+DLcOUZ&1;K6DXLf<?@wLi3mls+f!Z0_K8M+L_5VcR|A)
zP?x1D4ShVjNbhIHtf}>%Gh<D3(uu8i*?(yI*ojfbX$wt;C~jwRlOYo;DW=TS8#O)E
zoz3x9@WkTrEarkZZ93VvQ_zTY7IT4=NJR9ndowe1U@m(3I{3mz-V@Qkg1NxoCh~}<
z0(#`nt4>y){;xrG(`F%?kg!(+)^57NuY?bb5(cd<{l?ZZ{3Y{if!H#&6tV-s2Ra_G
z`Y$Xiz7){gR4Ht&DAp4Jt4r4k*=B!5v7V&A3l(~~rx=|(er~RRYPvEzM^}2j&$Y8r
zs^eG6&oaWz&eEmccy1Rw<ii;h<G~+BiWQ?dhfTckz0d3RUIT2Zzgnf}OcdD~;cJAi
zpj4CQ?jH$dkpm=tvYv=vq<uWEm;DxP7M<rFU~9eXOW16F7RfHvsLejMO?KC!h2D((
zhaiO*J+RF(Yju{9C2E%$r{7!Bd^!g4veO|tqf?T)@0o2<e}&XPVi(C9MCp<KUTcLm
z`<&64ZQ>U0Wdlpqz^kjA%i2eJLmr9Sf0HWxj<tllpXf%vGa)}!^{N{0GD&X-a<|mU
z{UPh*O<nl;u&GpXtj}aEDwd*jv)`Whl#TV)QnLA2g6|<)ruIF)W}U1h2O=m{+AKK}
zU$UxR_A0U;M2J*Z3SOK2JJxZL&cN*szM+b{KmDhqW@&6Tl->3&ee3o%-Im{07VqB{
RiVf^;`UNX)c%NbJ{J#uqVdnq<

delta 2639
zcmai$U1(fI6vxkG@7<eiH|6eE@2>q?YO-J1&F+>pO-r;<#6(H7mMD2>$fj*dYf}?8
z+b>LQQc{g=s)<KbFb@eTSkMxP1%2{KD1vBTiZ5b=#V5tQ2=$@VGc#w+x=|dM`OTa;
z=gi#s-?_VY25ujk-P)cn<Xa2*Xfzj<rMitqceg1cHN_18U{HO#y3X}RpF1*ibnw)0
zd0=d)d}?&y_{-&?Qt8xac?_U*eC+V)OsU*5l2vK)t&g-;R?FvdwA7xq0?kmrwLqQx
zuEMUu+_h|?D@BV?aZ&A%9cm*GhWF|K@M0Z|%^t{IoDd6ht0nOO4~z3+bopn|R~Ni4
zgiCk;Dy>QV<wuP<fxnn3Tr%Cl#0RFMTbBt23U_FW3H54`wZ^TwCWPfY`PFhO+oQ~#
z%tmI6nP8@vX=V#E$K1s%Fk6{z%)QKZ=3~qb<`c{(nNKmhn9ne~na?u!GY>F(nJ+T?
zm__Ch<}v0lv&<Z4PB5pK)6C1v8RnbJS>`*;_nGs|1za>k!cy9))@4DRnzOWqG<Ng2
zp1FbPWo}~HOg}To+|1NkTksH%wbmAF=dsq@0<F0PT5Aim#ulX6Pit&}*4P5Au>}R5
z*BV=(HMT%&Y=PF;0<EzHT4M{e#ujLeEzlZUpf$EYYivQc%#U}Q{b;-0E&=*H1n6@R
zpwGdC1>T2#2Lz~d`TJ(5S$*Pkw#ug}r>*qZ_>a5ve-Ua|KD8?>`}OW@T2(6BfOAI3
z<pPf+PWggz?`pk;tU+G^6MwSTZmoJNBPNvBF0ATp)3+A)`5d~lGdO8ygw2@)l3QF5
zs)+&UC5uffeCO+=)7pd)e?L9<8GkY|uV%!$hzq#lb8x{wpZxD{-&&AE-M8?0BY-~y
zZ0rko@za1;7<en-G;CtG3~^fdtlEZn1$zRH7{_m84vq)Hk=NFe!9nhaiRbY%@_QY>
z4rHnQgW5N+DVP<n;tSMX#!ITb5zJyb<ZYPZNSk;8?+2a81Y0EJv&!P5dId8fM_k4J
zP^Ty^e;n%ch$G9tZU5aZhVaLxhX)7fGc3zas)MShn~FU~!(x?vsLKD)zu2XJb)FM=
ztI2u#1V_o)>Zp;bY)7lIRqWFLaFyMSgLIBvF>mB-l~taCEK=QbcrxZRRKHDO%u~!K
z6mwd6>Bh}{8FNypla6~Eq!O|;QXRqj6nBuUQE8$gH#>@%xPvofO(+|H<S6#Xok)o-
z5^da<na1#H+z}<U%CB)R-lXVbJTDPNU&6tAaj$qu<`E}w8;yhUAa*4V8l|D(LHsb0
z!Ii{USTqa~#l_?fyz8^^`=pHvNdrGh1(O{Cow0H-n`tN?uJUtOd9)a=BptDzu8@Ov
zisDlSHl~7W7ST%irN_Bc9E)-`9ZGQWdom*xncSpWoBVMZ>RFX8ROm~S+9BF;G36we
z__9{EAv0K1Ycq7?N+w*-%g|3zdWYy#32t(NKKWKtkqPJ@!MX(fxYF!+K9_$tsL+R<
zw$LXtgrae6o7GSmHeye@*>jt{>1Twz$7KewihD9~aYk>RBP$Ok*Ou44cJo(oG2@61
z{E{L+kXh=A2JX$o#JjlI98M(GuP+~_Hp_J!Y;inGhW5_kB<<;%+D9&_ZCx7b38XT$
v8NR@k7DwE{KU?;N>ZMLpCK@#5C+rgTWSc$Her>sdliA&#vz+@Ic?N$0m-v$F

diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
index 9bfdab632f1daabdcf74cb3d4c3464e8ac587058..9bda8c4131f5e8fc6c8f5c0694acfa592129b1b1 100644
GIT binary patch
delta 2846
zcmai$PiP!f9LHz&&t$V~%x-pPC%egE)U~@wHrYvyb&H8frH~v-2{ea|G?KJw2sN6t
zt`ael(54WihfRM)rCl(H*h@X7N|Ay^N(m}hwTOp`IcU#bL=hzZely=`hV51#JMZ(}
z@9(_dyf?G=k8e*_+Ka`f_gnic)8rpFZ*Q7?MO(<-WLQxYKVN0{S}&RF7ZRrH-fLOx
zyTAAh8}oQyUmtVtUTgifMbBHI<^cN*@g;p)Nzqg4RrL@0Ufl}Lv+SkK%f6D&_lZgk
z!GX=g!NaQRqwj(`UDEROSc68%e3T*$AvHk%XhvH=3E81`JIx*jlvdi&bpOL_huj1+
zU=GZK7T5<C!G3TEJP3|}hrm&A3@m|1!AWo$oCW8=1+WY*f=l2ExC*X;=fMj2K3D}e
zz>mPI;5G0%cmuo%-U7G4Z@@d?UGOLH9=Od<FCO$O{9J4asA}^3{F)MiGy+D!1lS6;
zgC>{(b6_5{z&@}D_Jc#<L2v{-1df7ZU<o`5PJ+|mEI0=)fMswITmo0XRd5YF4^~hw
z-q#|bWVgNFc_(kf;-XLuN&Vc@;L+M%Tvyxbfp<s=Aa2Bs>zt$i^K|m~V|aQoMYFTV
zC>Gc0OiNk~%jxv{l@|IrX2b(ZboVIQBZFdjT}~`#s@T2(8fcM|d$-2&Nu1m*xl@kV
zERpHUSc0~L0iGvh-sV@5HGYaR#*!$n@VAy>ztpV|pP-pol&bMG-H%s0ybcCW7Ci!a
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zG2cyQ2F`in+`w3>v*eNA@yOry$nVh(=N*BBtFOExRSC-I9JLw4>eS|OW4Mw2&PFyr
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zq(st0{+c~<x^|33E?)(=Ij>^J{$*Flbhn7y;+#j0_-Q4>!dD(vC^=g0G-BfRsz;ln
z!44ypgGA`nS~SnvBD50u6vl!geb8a_dT;22N9!(FGR}D9Chd4KigwncwW!c(G`Sf?
zdy>v}&eNZr`EdEfV!3DP*!<}-wRhc4wXssF=2ps$GQ<ztKHRCtVIf~!Z*wf<gILXn
zQ(0Dp`1)_FUbd*8Z6}`{&$D*-+sqTRXxth6C9d4$0EwOCljatwpU3s0o3z}Weeqe=
z){7p}CB|+Pi7wTsjXun>deN_`6wN2?e+FEL123>yy)<T>G?Jn=O^HrLbv_-}vDjn2
z3k?Y=arco&L@pxo7B-PAAWT2>bg5}t?#UjQeuSU0hZWo^4(zhZv8=tL*X54*x$^g`
zC#$YuHcEqq?6|zC>aDhd*uQ&XH`j^%9?N8*7VKPX&=-ZQdIh;|+POYtWxZT0viG=o
z*U`fB+I4)+GRY<9!Q1$iV`axbWl_E8(VSyD0vD;Syq;>K-(ndTX#r*rFho1npgtRP
k1feE}vSrWEk>0Mx1-VsjRrxYewfBj}5;FeiNb=!-0bc*Hng9R*

delta 2653
zcmai$Uu;uV9LLXDd%IOy)3vwUHq7h}X8)~QJ2S>eW*iA-GeHI2LmwbpVMCDNny$kU
zhYW*?g0b^Q1mjG6zyy;)G}8nV5=iu6F_7#*6CNNLFTNRgF#d@?_&eu*%dSP^N$&6S
zyT9}Meb2e)^xWRn(VzBJTl%|ux_f)NZ98wP=C-!IrB4Uhj6NcS@bdM6`<frNpBo$B
zU!0z(j7*JJrb{CSU#X0j%hRRGln~{EQ~Qo|mMdM8IW5!OyScYET6aFrLv8Kr;U4yT
zd)VoIVsr2O#eD8ohR5Khh8s{0+qj5{a}7e!8x3Nr`a=GtIUy!>pP0Y5D1W5|xhzXd
z2OA0v=4B~8(l12K8tl`z-X{&6zx1c~MM?X88Or;7(xBr$%ds9qc<F>My1@`lj`9QR
z)1Dz>s-N@f*@CzYwu31!3+BNdun+792f*#%5V!-}2@Zn=a5p##j)4cj39tlKz!`8B
zoC8mSr@%8{6+90vfS-aFz(w#Y@CtYpybgW`E`v9~74Qe}7I+(6r8ZwwHtN08*3;<h
z9kWU2G>QNi0!=UmwtzO+4yM2?m<M~nKCmAg0Jnof;0|ynI1CoR-QXxV1|9$>z!F#i
zXTVu-4m=5-0?&X|MH<V7sp|82B-Te_eWVEKJVUG^|E#7Irs9K>p?jSb=QY+jE=^PK
z$GU%<rT?qYvkL23(Ju}?A)bxe*&sC=QIALX70DYm)!g-XcHZj|!l04nwNtB~Fm8y&
z2j|ss9&=7DU2C@Z%r28`?vx=YM-(@BM6|9(h+&R|c!cM}gS=WH`Y61IpZm9PI=-NL
z<U<w5sTj7%jx41A`(3zJWU>1`j~=0d8KRw;CR&YnDQgC#mv)&Jt#mfg#b}6Hj3z2I
zd*y3%Gh)eEdNyg%Uy)e+tu-le7JiI*j5<wAzD-Y?IkwYm-=WXgzD_@~eV2@=vYVqh
zT8svQS5X;a9;ahbD?W#a!fp7?%+qu!YRUKLPIOR?E<L_}&@ac94!7R($#L3~*i;<h
zx3X#*`6_D9F|~MtZ%1A6aaaD{e~GJnx6UEjm9U;UgeukRu9|eI?RTlw;wpciEAFGa
z35%8!f%uFos#ZZYwYNv<=Y$ok=zGV+=u56iB?IvzuBZ>bsyVE8XE7NFs+~}+ov%qc
z#(Q>~qqYihQ<E*xC5{GCfnZ9<gitKeoum~nBcjj;UnxydFlEWI9%UjGpdqe4fPMv=
z=2I5Uqyq9~r6Ui~CwzZ4Y0`3Px3@e#QKU`jPAaCak!^UTO>LQ0Y0|b#E7=(@wRf25
zm58HPTbA{Fs~)ZPS6F+n1Qj!u9OfUeMb%7*><%wo$e3#p*~{vdEYKgBB&|Yy$aK_y
zSCZV6y81h=SKp>;{e8&d*9_0IpV~UC^nfbiR-1>qZRD$7VFwknmj4D6Ds&>-DhIVf
z0SX26tLCO|`ODxTg*{qfKz)61+o<PIPzup6l1{AZKr5`Ho7oQkUSx-L_N-EnbM#GT
zQoicUKIN3$cU3;he*NrEQ(KoMS7>WjQhuye?rW6~wMstil)J}Q4^yvlneKL3{sHHE
zN90L%w93!5!gVMNx#poZzFy%96?2v>(b3#f(eu!m3pz#W1@<Q0%ysx<_|1GxGQY*&
LgwM9`)f)T_8>qw+

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
index 3aaae7a6b13fc2c92003917de3141912b59785b9..f7a2c96968674193184bb62ca225c9322f784547 100644
GIT binary patch
delta 2613
zcmZveT})g>6vt=wW3r0~yRgdzim;`%?6NC+L8RNJQLIK#8`EfGc#u+%`Vrfpl*VdX
zYb;gLRD~WAF(Co#L!W#i8sm#T7&S3|BqqL?*y@un1|Az9#B*l;w_K13cYbHinR90D
z{C95neeAE1*_KM>-hF<bpUd$dw{V}!^;WEtyJJ;KsVF~F!813Mo4cCX8KignKIiVM
z+{csI?(6Mk_V|^`+_&Y%&-0wcEzVEB7~D6jCPl4!Qn%5ZJ|ES~M^|biLy^cQdgW~F
zLrvHG45dsL{cB7#rWCE3EHft5F?!c{JZgk@6FK^~jph(-2X}*ez&zLqmcTC12YbL?
zun(+&`@sX?{a`<M5PTSX1RMk(0}p{ufQP{+!6V?);1GBW90y+jPk>Y4Iq*$z8k_+y
zgIB=!z*%q}TmTorWqL4PACD>nl{Of$GmKL$YLvk^0ak(4U=5f8>%a`y06M*mYL>A!
zR&S$P5p}v7<#ad7>1~wL*{BlcIh~DiIveG5HmVnKr?XK`XQQ0XMme30aylF3bT-QA
zY?Ra4D5tYgPG_T>&PE-=c_naO0b^<zD?8;A%AMcFuRn;ZE%WSHC+H(T%Q{rwzAbLv
zM%``mqQN?8<fWZXI!&+CW$B-Ev##PDXLm$ZoxQu^j&r!h=ww>%W3Zn6Wj4j^$09uY
zF3kSH&b}h&5RIx@sZRUT89E$~@i>Fk8p5g8KEi#9R~xPy;9V=aUN_9@$LkApw0^M=
zp6>DBOvu4|v#pW)*JveE?!E|*;2GEweI2%79CkBvn(DJ<JxvdB|2CcC{w#gW{X6uF
z?V}Cl(My;wn1-EVo`Wrzg)RQ`umy{-<wR#-3--Vk|7AI`_&sc0B5D}Wqbt8P3?%i~
z%C6k1(a%zS$F8Q~h)ZZ^1p61yFkR^In)q(ornx^2TTo3CdGAr#lQfCGYAx4gV2gh;
z<d^f3CjL{_a$O5Okl(!4OQ9&=?t<4H<nHFk$xt-#=h=56<j>I(*A%Zb$(pd1>+<vy
zM}2tY2wo0FE3}^XMl0}0jc_!0Ysoqu$_jQO{^vse9BlDFAM)qv{lexwycmjB=*xmf
zrgNMoI!jek$Inc4jgC!BPSJelH+lz+6x(Ppo=Qv6aN9{Yik|Lg;XSG;rE~|imBQn0
zoB2j5r%SX{^a=~Oqqjs8ZgLS~{3K++EqJK|oagDAv|4m^_uA}PC>_j_Z28G-%^r~K
zq>nWsv|en}2WhF?nBS&=ByTM+M1Ry|`9sx%5@V68rB?kEEtMKGDDfS1kv&w=<6Xt%
zy!->gt=+CSZg)I$xAV<9*!ShS|6B01EO>`fpP@#btuZ5BKAxYWv{r1OAG=ceqAlBq
zYqu6ETf0r!52&r|C3AAZ+*-J(m&7Zn>nPqIyIuU6EuQFb)5Cif*|r|i7j%P*&!V_b
z7fNmVQ(IvH6$V`)`_^)7TPu7`BfgjX3Ka_S&h%&5erU66@FwnbMMU$r=zG7Iyyd>?
QYLV9cy~&$c>sQJC53d}i2LJ#7

delta 2896
zcmaJ@Urd`-6u+1L`GB>{M``y_2drb*ew3EBtk!B!nQ_7lbFd7<9tbe#l#DSfMW=$m
zq6to>;8}FWW#Mr|T{LLIgJ$|>d~r{@C!;YY`Y^=@6W{cl@1DYES3SwSzk7e@+~2+5
zJ@?-Bm!a=Zt<-m<(y2^36$&LoWcE4~x<6}?SPfSTA)Hv=vX|8pp<`pY(<3tzg`w$O
zVP<M*e6o<s=Vzu0(?aCOr$?WQ=L>D;5|&IVb6=)7TPm5vsUFCt(Sz+w8XKwh^uhMk
z^@Q0Q#YxaySURbJbx_oacPfN{3l(B|<#_VKf?QkO%FDlDRL;q%ji2N|h5v?>4p}8c
zv36m5<00p}5`J?<;g-uSU9it>sM_HYPT21bVDFgQz+N5o%3wY7A;u=gX2vk1$rxpf
zF}5)#8QU4tj2Xr(<AaPHj1Mz*GCs=q7~|uN-HcB#_Aoxl*vojF@dV>jj023rjAM+?
zFitQQ7-tz57++yrV!X(>%=iZ53gczQD~wke*WgQ6Kx$T|tlFW83d^UdjA7r+{Yu7a
zMi1j|MxD{e=x5x+sB*4}d$_N1t%*kNtDI{><y;dg*P2i{)<lfsRE{;Fa;yoJV@;&l
zuX3yjm19k)9BV@5SQ9G8nov2`gvzldRE{;Fa;yoJV@;?WYodqrrKG)bNTGH^3bhMT
zs9kW0HC}}}0a94IvV99Iui9_iSu18+QMYoj>tDC#|Ko8z;Pm+*>2^DG&XbNaQck_F
z>I^s>qKXifYy1?2bA6*5L6^|2tG-hiR@1t%cq^^biEB>O7<*mf@=lo5I-p|3GR*_m
z^g5~YT(yh=xLHFt|GSzl+$r1{-ynYTysssA702pAmM97_539b7mj8a=b_UQ&--JGA
z?a_lfq}8G)ldKNQi&jfjMZPqCH^;;gmq@XJv|nPDpg58gXW?vZ0%Cp-T(9+b=WJ19
zu;@47c5O3!hTcklvwRKW{)BuP2C=>fm#q48te4=9-w4jz#;$Oi^05F70VDXj%^T)+
z4dNxp1-j($#)pBfDmk|CXXEc~nS-D2J#b_QpK7uuEF)G+RYjguhHZS#7Jtgl!~U?*
zf5zq=wRwv?so6)Jv&Emb#TR*sABA|>2tIG~dbmv|;XDk64etv!uOB`R8*nA;@y^)T
zdgwzo8}`Vvm<vNr!X51QL_A)~51EN&5*i`~%pyxYvSuvL!ck;Dh<KpR^vFESMT{W+
zY;IeYTQnw5>fWcfeR!fkng*DtIc{T3NFj@Q-ZM5f3qRtjy3H|XJ~uG}@0)S>)w~JA
zPNxjPddof-i0g2>Meo~-gXn;D+6GgzyH*kBncss*+f>Q@;>Xg)67OJMfNV8DkJi=1
zkfG?iJi!dIG{%j^ZoRM=jhsv&Rc=LJ@QVJTp=h)s`oB=RqC?1)Q{TdsMGkkMx19QB
z03B$>?;>>#OR0Jfa+0oTbtkW*PyyA^#=~9cC?|Z2g$L;Rpph{CNx4gS5IIX&egccJ
zNPGbM<@C%5I?#%Dmh^T(f2>u03o;&o1-}#DS6ranf<y7h5jyYXbT(OMi^R}Khu)&n
z52lxZzBCDc#0~f=9&)`$j5WhB$hOGIx3OPthU+Fe(CjOvO(>n=268k5Utw%1`v?|M
zeH}aH)Uz!rs+*%}{d7V~)i;sDBRIuj+wcR(#3KQnP7vCHS0TN<uR?#KwQ9wum`~}K
S6s{$jsup<0uPvrATKx~I?QrD)

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index 9674cd52e55bf53278de3439bc6ee82985151aec..b3fd5ac694b92d25d0f98fb0b27cc09e459c7a80 100644
GIT binary patch
delta 2426
zcmZ{lUuau(6vyu`xw%biU6VBFZM)Lmb#0R-ZIfVZGc7b|St}cCuz`K(Y&)VBowjV5
z7VOr_h7=r<dItJ1m~MmZp@LBV3=vcqT5u2IgXn`!@Kxzv#5d<Tzx%!RHsYZ<pL5T@
z-|znZ-2O82-E_61SbXF_ZaC*S{Kw+gj#DUVC#%^8!!UyUt9ZZlDQErd_&%>ZpUZLW
zf#Rc_%=U1hz|0R9bL-z^Z70c9kdkJ}XgAuZS8b?2>3elMw7}ld=9_`X0)Y<{{bWAA
z*%>;hs5={{s%28yN>gW@6*LWln(7ivQ>aY(*|J$bT(?VeyaRa-*aN1(0Wb#^z#=#b
zmcVgv5<CnZ1&@PM;50Z3mce=O6u1ahz$I`QTm>(JYv3iY3cd?o0p9~}fE(aP;BD}8
z@JsLxxCP#&_e0I0pkZO<cWCMi%Ls#wU<8Z{l_h%<w6GtR;UL-rroaI(2Nu90I0}})
zac~km3?2oKgHzx%I184+dGHjt2v)!)a2Z?$FM?~}C9sP13S+%In#NsZT-FS`C)jtQ
zy|_`6=RQlmyAzH7-T^nV)A|1^<<3M=7d0#yK}9JaOVG7wyK3OhiD1x((O}fxYZ?(;
zRS&i{cJ5wP&(JhBWJX-qB=r=F#_7Y5$<J~0YoR})axX)%iJ+{*k=P0PBog7z$O>)8
zZua{7pYa};Jd&1H))hJy&*qom5nP5X(X+4xS75g@&(UT)tIpAHtXHTxkyWqIldM<i
zjMmo^+5CCr3$|eM8X2#{7EHnx{{?y5kXYv_*fOD}HxIQu9abkcuXk=+>KUTm{cU3b
zx1gIb<C<EJ(Su&Qjqi>Y#d;C8ppmxw?5Dg{m*{C<G!9$*FZulP{vzUkSzE5^pfCD%
zkM*1{8li=ho%d>cI5O{xdj1sqp7;43>Pp&e;uVpq7qsQ76dmDc4jx&87k$wptt9Qa
zB0SQ=ANAf^s%DWR@Ma?ZIiKHwE&h`}KYvG3yXR2$MT<0+vgwUfnYL2{4V7n?DnoN8
z7fx3w-v71QOZWP_=vF8~d(siLk7m-gD)DC9^j0RKl5};~b6#ivop#g!b*1foC+3c`
zCHuf4mqiY6SRPos7a8R`TSe&AOj3<-WoxQ=cY+kk38^idkiz;KXm8R=rb|7chc<9D
zydk86RM&QxqOY0~{MopL9^(O8&2*|`(j?J}CO<ZDC5tp^pl=5<^}oyidzNlJWLXb+
zf4}Riy3pC&`9DLRl_4K8j6JdxEHT|<O}yOIp^?F)x}ZC*%4uS`??QK!snov2J9Kr>
zR*Up0SKdUQs_t`5_gTc}#6L6Hn%X{}(aext|10K|qX+3O^|9_?^tn@*^vy&Tr?$f#
sx;G>{`Pa}`A{TO#XJrvsWGh~yL)lDyRlXD~Ra(i8)K8-K53&yb0E>b_NdN!<

delta 2533
zcmai$QD|FL7{||PZqml3a+BP66Pz^6B)w^yHj&sx?J$K&JK3-uRVV9g%i7twZtL1?
zRv6mNDg`@i{W=w#Fu?~4V=7hX!-jqEp-2ban=cc5@IesPz4)Zych3E1z1E2b?)jbb
zo$vdf@0@c_ZZ`UV9+=<RQ79JLi-lw|pH#(LCzHEN+Q`-5LqZ6HpAWsyLSOQQ;gMrQ
zXU8f7lOvV0;{(S}RYoQz&W=|mg_t-#dGuUvqSAW0P0JM8pKPzrR><dhs;5dt9^rO-
zksF04^2O4^Qd`@G!;_$tHOnF);^N~PA?RX_n4CYDe{EWb)2`3L-D~m>x*}KP!R1$K
zp02U3OX-tAA*!{X+jQA@rq=Zr%eRbul3D{zWCjA#PXhtlt$luB&`==8y$=F5_u{Je
z0Pci638p{?YytCN5iEfnU>V#Cc7yxD9<UEQ1onf2;4nA}j)CJ~1)KuUgVW#)I1A2!
z^WZ1o74Rzf1$Yho7F+>ufUDpS;2OA2l6SjSpMb7?weATp>$Fd;2!SSOfpKsrm;_Ux
z1Ga#9un3mG4zLXF1-rrhU=P>_9s>KpL2wux1;@Z~umVnj=fP=k2Al=wz<EXLYl_f#
zAmEeOABp{u!qk3#u@3)5O(`tJ`|r0Nb$6WiSo?T1Eqxw4{&6GzFG6KC6V_Rg6>+mO
zIU9Ad_4JDo^Z7(jky2qx<*w&5TMeHOe)`JXx_f$seA}*3ubGo3Vxx+W`a}%3cMILz
zG+E<xxQq9LXKaendiZ%>ogK+0=JlxDaz|^DE`)6=N9Gg%`O`(;m{B>)^G0bjYEs#$
zqs@px9np|9XeesaYI7aUS|<H&)X}PG$a8cjV#_yZPuiwXG@f|dGwUMSapn~5iQ00S
zUW~SJ{VvxR={v69q+hvyhhmnhpR?L%&I;A9Au`OIp-Yx6-=mvWmpr`ekG)(c2bPaK
zb~hjg=|Jl7p-%p7RAm=G{kr8=ReOfJhduT#kN=Se*p<Im=Kyu4?0p9irAEC`y&kn8
zk6P8P{9pCh19UrO(@H9o;P1r!VxpzatU`BEc0GRKwLMOsb4)xPN}RbLAw<9vGphIh
zN;*`p_F9z`Kd;kCK9zO0CY6bcO7;YO#@0XCTK(84o}gQ4J8@Dup_D+Sbc+5;+w!EI
zr9Ts*QYKV?wCc!A(uIsoqnVH#Q9AM%UE=;s+M<<AzcDc~Hbl|J9Q8JSPn(7zlN5Fu
zq(ud%flSAs#ca%pxN=iaeT1oYqYnM*x-!)3*s_n`P@AS5lguoKJJyy(wzIe`57BQ<
zBW<v_m9?^iQCDUSmqMxgAE4f;VuKF67U>Kp_;uLTaBvN)nJ5kQUEQAHe(G(qgEye@
z5}j#kkX;nc+SxJ`MseIqfj`jyQaGX&BI-{Emt86gUJon8zD&C|b;DIr3Ond#Q**Eg
z?}+w3uM}htEj2gt-Bfdz)QiYv(}j+FnA_X4f1koFw!BK&mPYxhR$0|5A88e*(GB;`
zukPq}mFsl7#SWTki@D_K9<N|YE381F+a1z*sKeQ=utL2#TbAi~?%CKNbbboCK{n$p
Yx|wSZmhjdr(Y@U6pm5yrAJrcG4QODh5C8xG

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 98781f59418f11850d763cf86172679bd6ed2771..94c9b08b95dc0bd64825eae787ea1de46cdd7340 100644
GIT binary patch
delta 2668
zcma);-)me|5XaBmyL;R$NxPfu=H?g4O}okd$R^onvfajFl2S}4)fVfIL}N`gwN-0V
z>sCe6rcjZ9S~gB;i}+A|P!L2R2*nqDkXjI*3R>{R2NCf_|ARPl&-W&m?FtUL_cLc^
z&YT}}&fWZR<j<$7UFGt9yNjiw>+&B<@a?*zWzWd3g_u&x=BMI6YqRd!2gzQ)`$)0K
zeRr3~IGFX)=qPh!Y*%URhvBvx{oISi;%8D6es`#LMcvjJtB2OCv$l18a{ZprcqsIR
zwf<Q6s%3?!H<F^iA_Y34wH;Q94(gN@riZlC8CFp*%hpSKYFM>N6i3&x3w9UW0j9xz
zFbn3v0yqQ~!F$0`umqODac~d#05}Qm1^0muf-~TL@BsKQcnEw1d=z{foCO!aMeqc8
z60CsB;05q)a20$Htb&)hDlHLP@qT-jErz6RX{nE`m4-J8#=u5!8yE+h!6euUnmTIL
zfwrlmR^4d3psA-;rjA;f`e{{w-_%blQ$MXt{j@Um)5_FOD^owMO#QSn_0!7KPpe7f
zGxgKT)K4o@Kdnstv@-S6>HzkO&#UyLEBQFh>nNYl%gAIZ8dcu@`R6>~_xIV0+w3p#
zrV@>)1a8Rx>M3_5fqn^7D=R@CCsLG8bXYODd7ZXu-nw4UxDQL1eu_JRnfhn0A~UjW
zwO#tthw&s8BVleQk*^h5wlKqLob$b(n6_nyen~vdCupoWN0*wbeSVz7%By~Z$t(4w
zjo%gewPm<z85Y4jEwwmJi?DPs&(ZzKVe1^dlpLm5vXMSbrmffLM{bRCOQ+KGBD0iA
zH=Rc>L6r`soF;s@l&t)stS>Ui+If06HEqqW-%dRdr8oN;*Gt{MYx=yek^1}ELK7i!
zyIb2QLXt))Nipwf=B4SGey5$w=81d~Ux6-&(?*}Ol7vOPFGCl|l10RR%G1oN3%b~s
z0(QQho{0T<=z=(Onc{Ki0_5*dX>Odj+o7_wk#Q2z?S+6hOW*R6vakq)-Xi_Y-ZH$B
z`6P5fnR+tLNN_?60k6Mc8S!Yq?$SzTYeexr7w{J8%Z$_Hk0{<_WM`M?^=u(lIrc_n
z=;*UcXDakj_NLWI$8$ZDjl}6nF5b|~p|V#tE#(}~%0E8Tm5()K*vd!rZjUwMWq2p=
z&K1}%hjWsjpxiL`M%|LsEOMYFPV$NPi`>Jyg!okxpU55B$Y-A1#ag}W7h1fa%`B2#
zGSp_DW?Q}NS&OQ<R{52cg--3|uzJH>t22xYQ9H~mO>Il@>CR)Z`$BX`CnfdZ;r~ee
z6;j{X&H*g4f*2hx3|OaVV<0oN$nAPlTHPtpd{qs+esZsBr*u}P#Q(fhX{C^{R;5MD
zg&5r|xN{ddzFzLOv`P9;Ah%4fHuqJw$x4fe+XPJvW~|R-EKcu+>AOPz+$Zd<H&_(k
zy5K_O>sve6H*Ax^<U|MMG;IuK=DucAz3kVJeFj}*d*uUDoBeyX@h+W4*e0&i%FsmW
nmZWA`kR4``L;Dup9vW!K;&}5HlYim5hIcglh7o@@mVE4AM_5F)

delta 2820
zcmaJ@Urd`-6u+1D>jl>0S6cS9j$vh`?I<1X#M&)H!8l<CbdWJwkbe#qNZ7<uHcd7I
zxEK=u1a=l@Vl?x~5OvP*;)99!Vu(*ZE>UBA(BOj^KA8BVp7Y&P_R)2o<lf)CzjN;I
zp6{OTyY1G{ZzC)9?U}Yrwk;Ehq$6a`J`#B>XOq~CRSO~9*seO;>dDA+6O(7h=VuC|
zbCZSn+0p6qg~@z=ezq_tM1Fei%!O3GaOkC0TPBlzG+W#)lTPDSM{;fG!Ev??2bs)~
z!@1S9*2G`}H$juwI%t4>ScJs&3L#*rLd>o7r<WGwjn(bE{1?v1dD*}IgFIRhyeXwi
zR^dYK4IHmq?&}i1HJV|?@JIuGHZ0w{4B>`fjJkb>sI)h^+j;DvAwuNGxKgZVKEl|@
z7-ftxCK#I;TNn>9rWp@2wlQWIbBsqB+Zi8c>|lJ7@hQfq8M_&uVeDaimhl8*KjTTp
zQ;dU*V~i7wQ;ai=1;$H^3yfD7ml@w;Tw%Nhi$<MPc1`Twr9_48Q@S=d_wc-uv6|7#
zSi@*C)-nbe_cH1lD)AuCbq$qh;JL1)61tX3=o%`aYo|mD$LZQBp=+mvuALIPc1q~l
zDWPkpgsz<ux^_zF+9{!Hr-ZJZ61sLu=-MfvYo~;+of18?zm#-VE-CbBNTE+b3VjNO
zxW-xP%1U9M%Fg?4d-Zwa$=WeHil$wQJ-fb-|BuIfpv_+k+lI$wa-B@vk!tFLm)&(P
zm#89yugoAt;a;t#6*h!<_fxY+mj2%CXEQ|ctt*fc{PRFanyeOJtb;qIg-@mYU3eBX
z(B~h<r~2G~Fua0FrhRej-eL~E@qe7U|6R2^n(|r3y#l?D>~`2!AW<P~^9~<fjbx?q
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zt8f|n*Woj}{|Wm=@CB{#7022bkNt>mz(BA|4y}I>e7;hSuK!hk$0Nt!*8>NRcjDzr
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z{ZP!oaMbb@9Nr*&5w+mGsMj~^VC$g|*<92sr|`5bISqf{yr;?QqY9AGug^5>Z?fPL
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zXB{lw9+*{kY{H$NoEe8tVk!7N_BAZH-7*4e@rPhAX~ONe*|!fDxv_OP7SnLHRujdS
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zOVKDJ16yfEoye6_-@?q|$J)_bPW@I89cabpB6WqWRJ{i|NgrZ$j`KKG0o93yV_oPd
zC%nnRQ+#QWF#fH$N0{DbTUfpWi_P)W;C=McP3S<Qn~IF|_P{`M5;~HVP??Otjer|(
zN=#9H51q;Q@rxKyF0&0*+9nw^Qlk5&^pW30j-E9Qe<m&1Oh%0NiLrO+0ND~h{VvYS
z?Qo0U4m4-3bc>Yka1%M&fj?p#X<LCsRA0kMIrWaXj_T%U%0GauRQ*fj@Fkq(upQU{
rnR=pbi=@$R^JPHy>uWHON>*)9s%UHUn+PAK8mpFh$M0;WAyNGwB^k9R

diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf.a b/riscv-rt/bin/riscv64imf-unknown-none-elf.a
index c8a6c4505d6be4f552c5002be18ec9527847ffae..a5f60d0c43acaca0df7b2f305f19915d960c1d4d 100644
GIT binary patch
delta 2670
zcmai$UuYb45XX0K@0Lr<rFY5RZT^vN^m4aJF1ZWFxYa;X2_#^ZKnhK2#8gv_5>3=o
z0;WwMMS}L>;uP#dz$!(HL=a+2se%ec^H5O~q=KjqqM$<iB8o3@X7{_vay@a#{yuXv
z^PBnoemlFHUmm$WRcdjZI}a543zo%yEWy#T`W)BD!*sQxC>mcy|5~50)?YK){OP@g
z0?$3*+{MAH_xJTNd;1+{{qwwOXL%M&h_4}0cx+M{sa@Sv|D><g%aM7pZM_=0Clq>5
zrSHP`ZnZ`pRMil@8A;MpdX9e3bxL){>3cn@hUp94Yz`|?H`U&tyJ}czpfB~Lb}L(8
zx4<-LgE_DO_JIyK01kn};3#+q90L!76W|m$4bFhG;2gLB7Qsbu30whBfotGtumqk3
zH^6h?d2kc_0K5!-1bzZu1-HR#d{^otn!@MpT0m8o`=aSe6xJFr4jNzs*aBK$8nnS2
zSOEJ#2OI#0z+rF{JOqw`hrtPO3Y-RKz*%q(TmXyUBDe&ufTzGU@HAM$d2zprg;HH^
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z>IwSY$kQuE4P}yP^+mcrnWroK>*Zvceq&xrreh}qdA4c4Va8;IBC_*U*<VDolXP2Z
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zEObGfmNVwE0gHH_hAxmTi-`RhSM!Dz=wg?5sW09u(TjiFH!|bUWr<G&?8x7wq}e!o
zt3$DA*)|h0?a6@GropV)Xu~25dJ8nqUI$*uJO^Fi&>LB^H@KkbfY;x!R6G{2TeK6X
zDBi~c-U8)qGv-$m?{QkS=jksyS6w{5SnN6W==^g<YU%h)ZKhv4_S1z(TpqltHV&0D
z)aXWs>00H(v(Z^yC7-ZpC6C(cX3)E=$sGHoIfwWPij5~}TT-(~Lra|G6Y)1Wz`BI^
zcTIdE+!I~dqj$4bDf`WOH)uDDWS0!(*+<w`Df@Yq;+-k?3(FflcpryVDicLd`iqq^
zQlh-f1bteY<nF$J%?^j?E8UPY>>mG*)D}`--^T$glDe9{$#sSP&}b!>IXJ_HN^AQ2
z4hdJ3k_UI9JXqyxdO_C2|Gw1HPA;pi;g>~&-Py@ij<1w^E$t<}8OSZ`E6@Ep+hnT+
z#Q9jDkGr$#JE&EXT1VevXQf(;c-IB@Aw5%G>k8YXmUMJbehSk{PiFEW+bX4xX1w50
z%#rhzBQH;Xm2G@V3kcgqoOXH!lTO4lOv?$gNF%&N<N2<tv)*?>aX$pKk-xoa3>CkX
JPlMe1e*y1lmwf;L

delta 2856
zcmaKuUrgIo6vyxFKmM#;`sY`FZ2(uX&~DJtYF9fYu}ikV63Ad-3K<Mgm?dGXv}K?{
z!zM8#P6InrNyIplB}zgT4L<O|B1<G$%=XT!FFv`9y_oo5;yJhHXMWV`N$&mJ-#O=g
z@BQ6-f4AKm{B3x-zCDplq>_nHC>|m+*P+lWY30Ofq*e%F!*a`9R{BEc#>Ov?&P*1E
z3**I^-0;LyaXg=&$rTGi<R=PmUyJ37$FH_2nMCSD$`~yXkK<4$(@BhAJC(#n;-&bB
z)XI8W+g=n0L9<}VPy_3r2#7Dx0XHn7uzWuL&VmqERZOfr-H?C4n%t7-HwP@QTC{so
zT4jw8Ms3G7d}e#Cs+2D_AKQ8*q#Va?IULds=Nx*ew%UaadL8~cyQt<=0}j=&ivYzj
zublPl4>7~cD6^FrXC|3xW;-*(Jk9K6b}@UHeawF5AajH{#>_G&nK@>WImeu5E-)9F
zOU#?hW#%e#jd_Q8m$||Gk-5d(X6`V5W<F#-f@gNWtWtZTYHL+#Pmt9rr%E`PZl=Zz
zFzcBiW|$dewld?)Bs0xyXJ(kEnVrloW)HKE+0PtgjxfiVS>_}&$1F1EnDfj9<|1>6
zd6T(Jl#<rUDtUDzuZ|RMm1P%?IQzDu6q@R#PCcGu6)mkduCU7aM^RIIap=JJ@&EZa
zAGquB!id9Rbqj|Y(Ty{qJ$1paHow&>YKYM4(I^YY`r54r?ZRz*XiUBIy{UJz3-zWr
z+YM5JDR)4+S<T1v!?1_G;#p4zu7w*Oc!uz;j(Cp-mr=<rWSPDY1xR?mjs5rSb+7}?
zX9>shb-#Qtpe{vn1+dJRVsu%OmFF98>cQA`QfwgYYm~}n^d!Yu_{-Y{+de0xeNNY$
zk%C+UkETP`7ltm)39G)ayaD%pZSq}sg7t^cpi$k8^>uh((}RnqzMb5rIeY}WT8F&2
z>GHo>Er&P98=gAk2wVuic=i<Czi5qE234z68UAK`ylC=wnDU3repm_X7rIT+OQxvd
zCpB}gUQ_<4Dc|r@{w4S-tOxU^sFT~Y-vxLa)?GzYRD&0qbf|7}x^gCOJv<2O@Lkv`
zv$)#2oPZ(B+Qux}0W$hMnt)Hx`#XC1*GYuYI|=vETi@)2rDmtR0#BOs;1qRXOEam@
z6;gM-WrUCcm~Pf#6*b39-Y9&7Uet44HhJ-O!jZO`$87oW$x*0_#9$!u6YSe;G6ccs
z5vjq+=#has>|(=`F?FTpzPIEsj?i=XNQ+cma;xJ@O<Gp+Tj{}MeJ~x31Y6NVJt{|2
z7@@unEN1J6XVJ(&0$r76mi3i#A5vE|nwcF-`OHqCuabHcrjJI>v}3fAdfblzG-E4C
zo&E=ut9PMK(&t#a&GUG}0`EniKhuGMO2VBioaGOigz<mIzl7;bE8!Y1$)GjTy$GL1
zYh(TRR7v~$CY31Y?jj@YL$G_SMJ8doC1Rh)XQe57;D?sTz$`vj(#g<nqV1QUbPi*?
z{N+DJAH8*)^9<a9L~F$UB}Hjz<PME?_H%r$G+I1T>Svxc-7w{&-6K6L78s4`G7f*@
zv0caKN}4;Y*@<y7S_wKY<(gaQ!$X-v9Iy;b$6ohm={%wB@%2DA?gy|NYpKcbXR)sK
R<nZyvn(C-Z6~7p}^f#R?iQWJJ

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf.a
index 131ca27c95c4f81dd7e66c708b6bea51d5886355..16414444fc4019d9a4c665ae394d89ce773de248 100644
GIT binary patch
delta 2431
zcmZvdU1(fI6vt=w?vA@_aPMw*bCWb|ZjvVZnf++C>9!OTYH4aIet!h|VN#+NwM|Jk
zBG_~*70iR!O;4pynoxy4*{Z=8L8u_=n}Q&Pf_?DCC({St>p3&$x;HUH?)ja2X3m+p
z^Pk!Lee%JvR$sk7wzo1~ab5hw=C`g}tLq?|nWzxL!l&UqE7R`E)#QMeUaeFxcW-?+
z4n}{xRzp^I*J~?3mAmhZU=}tiFi8&DUeO~UEf-`ztjI-6u1&5#64)0Ad?D9g46aJ}
zx|9T01>v7i9&RaR1%-fBl|lxIG6-jsgZ7in7W?~noXZ?!?qrTIv&=lR$Sg4{%w5bH
zbDUXc?qlv}KF*wE9$+419%3G59$_A3KE-^7`5f~F=1a_J<_vR=d7Akav%$Q;yu^H;
zxy<~K*<xOUflz125{h@e&43=Ej1ra-ir>S`D6@n47}I7Zm`P?AQ7Y0BtMzi!=%_@R
z-;JJ17(JCRIx1oGQ=-V@jDAWO{gg2JDPi<e!sw@j(N77ZpAtqtC5(Pb82ywm`YB=b
zQ^M${gwan4qn{E-dB4KEUmk<v8n4VK8Wv{%+9%rU7hA^ZcNvDSN-5N#<G&kV#<lBi
zn`e3R#5pf+bdquSKAwVI@m?9l6{jpqB;Y&S*%1`BzMF01Xt%vi@5D9eOEE7-`EbKd
zLM0T$_axWrf~7d!&5z?#xC#OH<0s&dZR7QCLNjr5*qedspZ8vnIFoMOXdCcnXSsTT
zBZTAZQ|}`CggN$mkxTGIvMiV2JlZCFhW2gv4ececQe?+c<?2NqPiV1^dnDdtpTIv@
zg5sCyYeS>xT?9x?$>ZzyQZI+)iS@DchLR^?Xn3e+B0yO}4C3>O_KcZ;E5l9?-W=T|
z+H>p^I-oh?Jn8K^^)C2&lk8Lcj4w{#PmSVdwP#EpJUy~`uGf6MHayHYRWElZ_MG<h
zdhsmAUiZaaxQ#U_N{zDK(4H|_xR1RRj?fmo>FcdSEaS}9IYKr3z1~+-)(np!cq^g!
ztS|1ePw`W}cotSOo7do-2O3m|UosAKW#^!oEk+x!zSAhpo|<21z~|W?<qnw7^+Psf
z!>2i04!}mvk&`I41L=Y-Gf>X^->Z7`M|oEk;dai+-J!FA?Pt;f8y)5#K4E&n=6%S1
z%yZ;jc$hPF_vq~9&dsAJn~urW>?z8QWO<GN#0vfLfUdB%O$Ex{T45TVjivCnBhNJs
z2EZ<)<?~Q3bSJsS-I!Sots)A?iiOBo`d^K0P|rB0XKW3bSj#|vF&6&cjEgkmqj<Tv
zMnczErYLUEm)6yM7yMDQ<z-#frBj9Nfq||{%h~!J*P%S>NC8u$8F`ayxk0bi4PDFT
zpBDcL6Wi4K7B)tm$T^Y=TLrG<`{g%gSGmGr)1_BK7jf%qet`LsBiG=A(nRW4t}{cM
cfsK@Z7w(k`kqV!Y7R1VXB7br1-)TSo1<X`x+yDRo

delta 2530
zcmai$T}&KR6vyvnXLs0kX=lGWphUK?->}_XUANl?6^s!|sHLP<5=wzk8fu~CW2u<5
zidYRs(=47wAJk|cd>}Cmgc|#%4?ds|rjJduNqsQ!MTJD)G<we5Gi8JrZ!-6H=iGDt
z=gvKIXLqCj*VC2y)_fsfEaW4RT!fmlk3<fZEF*S9yMz!LUhg`ur4x~3XGYHs&yJS|
zXGY7jlY{3jlt-thXD7=uLQJ2V8M&01E+4p<wPf<e$BTBhd@hHn4wVWxgX3ZW2l@P=
z$BIkK+2l|XlVEe<)kXvC>qM=1ze)&Ls1h@k-rT~x{A6ikTK)|qa#r@PeJ>AJg>Fje
zl3pR~-i_lmQ~OxLckVQ-xIHd6DhzwV4r+8S-H`Q|*bn}@N56XZk1!jVQD&T(WTu%d
z%md6E^HFAjS!9-&hncO+Cz)-`r<u<%pJjG3yO`a~=a@arUginrNoF5&h<S!N#vEss
znU|UK%&W{r<~z&^^E%vchg~}F{}!vPd0l8s53`!Ni|J$TVH(T;GsN6SlsZ)svpvLC
zRYhGq!uP70x=_{Bg{q=1RP}Vx!hWiHx=_{Ag{qz|RP}VBs;3K8Jzc2k=|WXc7pi)?
zP}S3gs-7-X^>m@Crwdg*U8w5mqMP!=@2LPxdOR*E)NV+jc0mfY3vO|p*Qu&2h1!*^
zx7?l=PCtjPVO3@Kj#KgfakRdu-&!BsQgj)ZAFC{DU`h+ST*6C)uZ<8rg_U(Bqv5G`
z!!g5joI(5DE5qjAj5IhpNPO5O!qz9i*>&QLfhv3b9k@4p;6^G4<NhwJ`WOCGUB#M}
z&H!sX1N;3Z-1k@N{_~p!$Bm#|#JoYM4jQl+@WBrOpVUAG&6+)|m_fc~`3xDFyaZPQ
zrhEzRMNRlDP+Rw^Bkw65*COZO9{SD0AAv0Pv0zp%!1LI@3~ylnI(%;RKLxYU67tp1
zGf?y6brmupQ@#lUp$^%<_G##aYB{*}SN(4uIRw8nH4V4pXOUVXUUo*hx9xEp_mhEJ
zhr@rsHX?01`8#!v!jDbnk)s?%v(BjF4z*#2nr$cl(+;}_rf{eFqP{x(iFnWq9#PfG
za3yNiTzoJmL@l&q%x#RBa#%f%m@#YrTVuW&+G}c2yk3Nwm<i)(jgSc&E%rP-fz}Vv
z%D*#$cpfHVX59oiaVs%N=>mKdGv$Pp<<FQ8?qc+a?TC!P{<sO%ai1I|9eEZqcpr_0
zpf7$(n;sn>hP8MGHsfEyyr#(rtR@=p_!w|MVZcg4gImc^YA&D@=U8|jk~XB8@9js6
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z06l)pkPat9%4#o!B=AeVL!uitQ>M4XiB5t)-5@()HEE{qu)-J@oD}d!dWXV*rErb@
z0bpySMaVu<2$y2YW}gsJ*bM{eX737n2Q2T)q#*CWk>&)RPRhN`ksC@tP$Zq{?c4h{
ztTvliqHi$r15&AK)1a$4F5iQEx;9BKG&W~`I;GoHZo*WH>8;RzCTuxa!Y5d^*3p?z
zwoV0W9YGv#SGWzEEvEbmyqTxM8?1BJr-DqxD=?60_O4TMY|F5eIq0ph_P4YL{{S3$
BrIr8y

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
index 22449707a5e071a09b4d9a4a1495bc9085fb8fe0..47ba78e5f40a1641998a9a37f544aa9b40a8d7d7 100644
GIT binary patch
delta 2426
zcmZ{l-%lJ>6vyYXv%?QbnO%07LJ_tU*ny?Yt|DC&0~!)AX=0N$N>VCNQHfR|b!$kZ
z1w#`_Y{KGc)Q85PHfbMd+PIoD#s?FdmWL)rAB@JA{sAf`#z%wa-1&|SYdqOGpF8K=
zbMBpUf9&s*4<?Gu`TU~;+5T)Q#Xpv?PNn+t+Q@3E#xRTsKZW2~A5X2npEwwV=dxLj
z9mqe%ow?oL*T>BD5A?6!^PFs&qgYIShNZ!}$!MewwW<E1AJpyWoY+e5RXko%aYND1
z<`bos=yQr5@e;IQnN+a4skhRKZ~|(rOfpTOGU+$VVf}FB9?kw{^h<&5pbPeZS+Ebx
zgM;8OI0BA=N5Ny@32+>o0H?qia27lR&VvPT0bB%^!HeK3cnK_mAAwiE4e%<s34Q_I
z2EPWs0q=lY;C=ceS|5!V7An6>Q}?ipDzFx`!Gus*vNjP5>tPuwc-ui2>;bc2AD9OR
z!C`O&90QMn$G{WdI5+`LfivJNcm|vY3*Z8{2rh#c!By}QSVX<5P_KZdaUVS{YgYL?
zIJBb!zfsoDf0zFLO4R;)27J$M=KqhBGZRBx%&=qx6{Dx(N%}n2q-r>GG7>T3^kmFA
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z$P(?uuXO|?Nd7m27p7bjBK!F%(2EH#x2WHJbs25(o(tKppxwkgPv0gyb)NoYy+ntS
zo_dRpvtFhZtxHKScOewJg*Mm7cqe2Z3)xrXYopTR0@XK+s)^FchUcr)sZyzB+fpyk
zXB~$chbsJlHpV1k1w&NV=``}$(V|$-qb;bVolfVOpz7j18}cU57W?ZVyL`Wh*x%4C
zUp3QrWn;Y@^4hfII=LXWojtQ5Z(w)X_DaZ}A}{SUid96SUezsMxirb%EG$xj*FxSr
zt)-pmJS>tU><zwJqNdPC5X?mE(;<5bZLyyY+4&xE_s(G^<jvEwu0tQVGqmIO)D&J?
zDD+OBo;zEh_O83?0Bv`*()FlKE#0;{NORqe8s^1z=;Ms7(sXmrdrtS>mr1D}^17X_
zY}_AbOV)u!HnVKtDtTcEK4g&N9A(qHnY22>k^9~Hy&WV_c1U^Ps03DDMS7FgGOg-q
zJ+zIj5ey+2B)UAqIDKE2<ZI(Pa*R|^G1H=sOOm9EBtO-0B#R`ep<jA3)xXOBJxiM&
zaz+oS*Pd-f?eTka=Kl<NPKJEQF!o6)SmHXzs#rN|ibfBo)r!tol-<PghYvlzOr`uI
zKBSw69W_t)IPx0u6m_0Yb)IEhC*hgN(v;`<ispKq>Iaxtmg=~iU+N5Yr$2?U&`hK_
u<r(hKcCV~tr8kruj{2RaqzEjs6mQc>FH^lCHw8<P*1RLt<H-G^)Zrf_NJx1A

delta 2532
zcmai$U2GIp6vyxFPPbjzn%Ui1ryFZJz<$j3gKo`Q7A0B|lCGwWg;Xt}*luXCNP*HW
zSQ3<i#E{6tmQ$3(5_#Z-q>`BWP!kd`(WEgn;n4?7=(`9nn)v3qcm7Mqit#3Mes|72
z=YP-KJ9lRv4*fn{Y1-MD@9fHVI!?|}&2JrNdqF$dj65fVF!;Lczvc#<w@1egl}=8S
zho{HNCntvwA1jYdO`V)9PYW@1c>3U}_Nnr=;~iS2v+I?v>TI3498a~QkmnKZcjdX$
z`7(3vW=F?EmnY$-=Id4+wh7TFzN`^~&ew?P%HG@uvqBu#V`A>{qWqH<<g(nmw6EsX
z8tayn0T~jaYHPVqSB%%{ym+y+YV4Erda#9@U{Kc5@u2P5K&>$7L@>^GUk7czYgBj7
zU=#cfm;_z04a|XgumJ7^yTRRH5$px~!2xg(90EtcQE(ib04KpRI0K#mXTb~LMeq_>
z0k47!;C1i@xCnj+E`zthyWo%D3V4qqyxMho2eb{;c{{+Y*D-Y>44R+?HiAu{113Qi
zYy)#(9xQ-6!ESIjSOj~)esBOB1c$&8a1<N|C%{Rt49<XOz*+DDcoDn=RupNpB}%iw
zU_fGhB-Td?Q^(bcdx)Rcl)_Sc`hM$CZ^e0yb&OBb()+RLA1C7fGE`Ob5nUA}qh56;
zSEF{ef!2(8ARt1Dl#f`dc0Hf7%?JolOLxrmv!|bsPun7u%ywxaH>UVvK*Vu+*HPrI
z$r@)PJ-i+~V@r%4MBd`3%S5w@iXN5g;pk1%T*RjSXeIHVKV9^L8Iu=z-WbiqOzL;*
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YtL?3!BHo&tB)4r3nXWhfvs#0{0X%WD)&Kwi

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
index 002d497e621b600dc52a0f19c3496e011b27b7b8..7866563c2081aaeeef2eb5f7a82950dbb953136d 100644
GIT binary patch
delta 2431
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zBG_~*70iR!O;4pynoxy4*{Z=8L8u_=n}Q&Pf_?DCC({St>p3&$x;HUH?)ja2X3m+9
z|J=>rCm$SZ_0{WRdn@A=*Tp|<e(Somx(=e5i3%Ysd>Y=fGVQKhO%8bJ)k+0(_ttmg
zVD!gpHDq;ny|(gGx%<utW?>8AGf58GUeO~UEf-`ztjI-6u1&5#64)0Ad?D9g46aJ}
zx|9T01>v7i9&RaR1%-fBl|lxIG6-jsgZ7in7W?~noXZ?!?qrTIv&=lR$Sg4{%w5bH
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zxy<~K*<xOUflz125{gg0&43=Ej1ra-ir>S`D6@n47}I7Zm`P?AQ7Y0BtMzi!=%_@R
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zKP~<hCbp^dEo_WBk#i&$whCOy_seh0sd9zGrc1AeKE$o7`2prjj$DHeN)xGHxy}q7
c1~yXuUAR{&L@InoS`aJmiTuU2f2Z^K7v5}Y-T(jq

delta 2530
zcmai$T}&KR6vyvnXLs0kX=lGWphUK?->}_XUANl?6^s!|sHLP<5=wzk8fu~CW2u<5
zidYRs(=47wAJk|cd>}Cmgc|#%4?ds|rjJduNqsQ!MTJD)G<we5Gi8JrZ!-6H=iGDt
z=k7goXLh6i*VC2y)_fsfEaW4RT!fmlk3<fZEF*S9yMz!LUhg`ur4x~3XGYHs&yJS|
zXGY7jlY{3jlt-thXD7=uLQJ2V8M&01E+4p<wPf<e$BTBhd@hHn4wVWxgX3ZW2l@P=
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zl3pR~-i_lmQ~OxLckVQ-xIHeEgkewEL5=RE8?qh~`@w(r=vUAF5oRMZ%8WCU%rvuw
zd4QQ?KFTaGi_8-9Fte5UB(shAH1iqev&>Fr7qgrB9J7bn%RIq6$?RheG0!l^nB&Yc
z^D=Xud6l`ye1}<KUWXg*uuJFt-(r<DuM3UoVOBGDF@4NEOoJI<hM4<^Qm0B{wujiN
zs;G-c_+C|07pj`NP*v20s-7-d*iThY7pi)?P}S3gs-7-X^>m@Crwdg*U8w5mLRC)}
zs(QLm)zgKlo-S1NbfK!J3spT`bW?u#Jr#gSkH;m2+6^hxE=Zwv!7Z-yI#qS0P`k4A
zl-u*d>F3Zjtg7tZaVq{lj@B3TTkC^ciY^25W0hqMOle`4OL&R!wGpCUVP##(Xf8b1
zaLh0rXV8B3%CNaNBMpuY5+8Pnu=NUXcAa=*pvqo<2ky-txRDCNxW5al{)InPSFvWL
zGr$_pz<$38_x+W+|9oe`aU&=fF>es6g9a=HeDFiSCpC~kvt|z~W{|I0K0}5kFTs_7
zDPMwnQ4>B3)YiS~$a{*%wa7WRhko<$M<9!RESQxG@I3Y}!yDMY4xd~7Pr)p-gnTvh
z8>sp5x(b<)Dc^*FP>1Ya`!w`IwH#dgtNu5S9D-k(nugo)wMeZIFFPaM+x9q)`^mtq
z!{I+*8<Do1{GB>S;m0QP$We}>S!dL7huW}1&9;;OX@}hdQ@B%oQC}T?A|5n@M^v>k
zT#1@B7az<CQ48%Da~or(99EAbX3X0E)|jt`_L^E0uNR>vX2LjHBV@uxi#-odp!Gwv
z@^?lM&%;E_teYSwZY3ruU4V~brkt>{{2BAXU5p;F9gz{(A2*>o?vtaWBhNwx@1wC0
z^u<qU)1%|Vuoln2X8cQ-*EAV{)kFgx9|P_u3|L8Ma4Q)~%>|U=91HJ5(uP#?z5UbT
zu$eGr4?cn>M3NYv)S!?IZCPXy^~vL{WCA8}mee;`eVtDRsnZvByLvmtdVl7eJ>X9^
zK#w0Yq{GROvf2wF34D|9km!cZl<6&TqLbiHH^>fHO`54YtT4s}Ck6aS?@$=96t3aB
zf?6XjLiUkDxD-=1`-G6fZWu^6dso;yV0m9A1$hUKG$-(MQtow*+)x67BI!(T-+;Ga
zwb{fHeS?u7kV;jX23^f@`5xrcwMlxQu{rb8Dc!De6Q){BZ-xFdVavf1{(@y|9i0hf
z>r}AT5ybI!h1;;%V#=?;n|Ug{!8&(+D#%2<0t1<5?>Z&NwhT*|gWd{je@lDt4=(wo
Am;e9(

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index f1c564a2..e6870810 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -330,13 +330,8 @@
 #![no_std]
 #![deny(missing_docs)]
 
-extern crate r0;
-extern crate riscv;
-extern crate riscv_rt_macros as macros;
-
-pub use macros::{entry, pre_init};
-
 use riscv::register::mcause;
+pub use riscv_rt_macros::{entry, pre_init};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
 #[doc(hidden)]
@@ -549,3 +544,15 @@ pub extern "Rust" fn default_mp_hook() -> bool {
         },
     }
 }
+
+/// Default implementation of `_setup_interrupts` that sets `mtvec` to a trap handler address.
+#[doc(hidden)]
+#[no_mangle]
+#[rustfmt::skip]
+pub unsafe extern "Rust" fn default_setup_interrupts() {
+    use riscv::register::mtvec::{self, TrapMode};
+    extern "C" {
+        fn _start_trap();
+    }
+    mtvec::write(_start_trap as usize, TrapMode::Direct);
+}

From dd232177887f1dc38587a83e1d6cb86a280cfa4e Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 11 Jul 2022 11:19:29 +0300
Subject: [PATCH 180/234] Simplify build.rs example

---
 riscv-rt/src/lib.rs | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index e6870810..5a51b0c6 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -81,23 +81,17 @@
 //!
 //! ``` ignore,no_run
 //! use std::env;
-//! use std::fs::File;
-//! use std::io::Write;
-//! use std::path::Path;
+//! use std::fs;
+//! use std::path::PathBuf;
 //!
-//! /// Put the linker script somewhere the linker can find it.
 //! fn main() {
-//!     let out_dir = env::var("OUT_DIR").expect("No out dir");
-//!     let dest_path = Path::new(&out_dir);
-//!     let mut f = File::create(&dest_path.join("memory.x"))
-//!         .expect("Could not create file");
-//!
-//!     f.write_all(include_bytes!("memory.x"))
-//!         .expect("Could not write file");
-//!
-//!     println!("cargo:rustc-link-search={}", dest_path.display());
+//!     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
 //!
+//!     // Put the linker script somewhere the linker can find it.
+//!     fs::write(out_dir.join("memory.x"), include_bytes!("memory.x")).unwrap();
+//!     println!("cargo:rustc-link-search={}", out_dir.display());
 //!     println!("cargo:rerun-if-changed=memory.x");
+//!
 //!     println!("cargo:rerun-if-changed=build.rs");
 //! }
 //! ```

From b89b4e4920e47815c9b641850e8953c123f8b371 Mon Sep 17 00:00:00 2001
From: Jan Niehusmann <jan@gondor.com>
Date: Thu, 8 Sep 2022 10:34:04 +0000
Subject: [PATCH 181/234] Remove superfluous parentheses from link.x

Fixes #102
---
 riscv-rt/link.x | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index e3b5ff4b..1f52024c 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -55,8 +55,8 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     . = ALIGN(4);
-    (*(.trap));
-    (*(.trap.rust));
+    *(.trap);
+    *(.trap.rust);
 
     *(.text .text.*);
   } > REGION_TEXT

From c5f355dcd0c437a1eca448a093e9477a75b04170 Mon Sep 17 00:00:00 2001
From: Jan Niehusmann <jan@gondor.com>
Date: Thu, 8 Sep 2022 17:11:07 +0000
Subject: [PATCH 182/234] Add CHANGELOG entry

---
 riscv-rt/CHANGELOG.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 3378cf72..b2337141 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Remove superfluous parentheses from link.x, which caused linker errors with nightly.
+
 ## [v0.9.0] - 2022-07-01
 
 ### Added

From 061c0aace3e7216730780ce1dcb6c9385aa56860 Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Thu, 15 Sep 2022 15:55:10 +0200
Subject: [PATCH 183/234] SBI: introducing sbi compatibility

---
 riscv-rt/Cargo.toml             |  3 ++
 riscv-rt/asm.S                  | 17 +++++-
 riscv-rt/assemble.sh            |  8 +++
 riscv-rt/build.rs               |  8 ++-
 riscv-rt/examples/multi_core.rs |  6 +--
 riscv-rt/src/lib.rs             | 93 +++++++++++++++++++++++++++------
 6 files changed, 112 insertions(+), 23 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 8fd31470..aa1ecb95 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -10,6 +10,9 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 edition = "2018"
 
+[features]
+sbi = []
+
 [dependencies]
 r0 = "1.0.0"
 riscv = "0.8"
diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 956b459d..4a4eecbb 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -46,8 +46,14 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
+    #ifdef SBI
+    csrw sie, 0     // interrupt disable 
+    csrw sip, 0     // no pending interrupts
+    #else
     csrw mie, 0
     csrw mip, 0
+    #endif
+    
 
     li  x1, 0
     li  x2, 0
@@ -84,8 +90,13 @@ _abs_start:
     la gp, __global_pointer$
     .option pop
 
-    // Check hart id
+    #ifdef SBI
+    // there is no equivalent of mhartid in supervisor mode.
+    // instead, the hartid is passed as paramter by SBI
+    mv t2, a0   
+    #else 
     csrr t2, mhartid
+    #endif
     lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
     bgtu t2, t0, abort
@@ -165,7 +176,11 @@ default_start_trap:
     LOAD a7, 15*REGBYTES(sp)
 
     addi sp, sp, 16*REGBYTES
+    #ifdef SBI
+    sret
+    #else
     mret
+    #endif
 
 /* Make sure there is an abort when linking */
 .section .text.abort
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index b8d85d67..de38c244 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -31,6 +31,14 @@ do
 
     riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
+
+    #sbi
+    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-sbi.a bin/$crate.o
+
+    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-sbi.a bin/$crate.o
+
 done
 
 rm bin/$crate.o
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 2c307900..9eea713c 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -14,7 +14,13 @@ fn main() {
     if target.starts_with("riscv") {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imfdc");
-        let archive = format!("bin/{}.a", target.to_string());
+        let archive:String;
+        if cfg!(feature = "sbi") {
+            println!("======== compiling riscv-rt for sbi");
+            archive = format!("bin/{}-sbi.a", target.to_string());
+        } else {
+            archive = format!("bin/{}.a", target.to_string());
+        }
 
         fs::copy(&archive, out_dir.join(format!("lib{}.a", name))).unwrap();
         println!("cargo:rerun-if-changed={}", archive);
diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs
index efff6b04..1df8425e 100644
--- a/riscv-rt/examples/multi_core.rs
+++ b/riscv-rt/examples/multi_core.rs
@@ -11,7 +11,7 @@ use riscv_rt::entry;
 
 #[export_name = "_mp_hook"]
 #[rustfmt::skip]
-pub extern "Rust" fn user_mp_hook() -> bool {
+pub extern "Rust" fn user_mp_hook(hartid: usize) -> bool {
     let hartid = mhartid::read();
     if hartid == 0 {
         true
@@ -42,9 +42,7 @@ pub extern "Rust" fn user_mp_hook() -> bool {
 }
 
 #[entry]
-fn main() -> ! {
-    let hartid = mhartid::read();
-
+fn main(hartid: usize) -> ! {
     if hartid == 0 {
         // Waking hart 1...
         let addr = 0x02000004;
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 5a51b0c6..39769edf 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -21,6 +21,8 @@
 //!   filename can be use instead of `memory.x`.
 //!
 //! - A `_sheap` symbol at whose address you can locate a heap.
+//! 
+//! - Support for a runtime in supervisor mode, bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc) 
 //!
 //! ``` text
 //! $ cargo new --bin app && cd $_
@@ -230,12 +232,13 @@
 //! This function is called from all the harts and must return true only for one hart,
 //! which will perform memory initialization. For other harts it must return false
 //! and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
+//! The parameter `hartid` specifies the hartid of the caller.
 //!
 //! This function can be redefined in the following way:
 //!
 //! ``` no_run
 //! #[export_name = "_mp_hook"]
-//! pub extern "Rust" fn mp_hook() -> bool {
+//! pub extern "Rust" fn mp_hook(hartid: usize) -> bool {
 //!    // ...
 //! }
 //! ```
@@ -245,7 +248,7 @@
 //! ### `ExceptionHandler`
 //!
 //! This function is called when exception is occured. The exception reason can be decoded from the
-//! `mcause` register.
+//! `mcause`/`scause` register.
 //!
 //! This function can be redefined in the following way:
 //!
@@ -300,7 +303,7 @@
 //! ### `DefaultHandler`
 //!
 //! This function is called when interrupt without defined interrupt handler is occured.
-//! The interrupt reason can be decoded from the `mcause` register.
+//! The interrupt reason can be decoded from the `mcause`/`scause` register.
 //!
 //! This function can be redefined in the following way:
 //!
@@ -319,12 +322,44 @@
 //! ```
 //!
 //! Default implementation of this function stucks in a busy-loop.
+//! 
+//! # Features
+//! 
+//! ## `sbi`
+//! 
+//! The SBI runtime feature (`sbi`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
+//! 
+//! For example: 
+//! ``` text
+//! [dependencies]
+//! riscv-rt = {features=["sbi"]}
+//! ``` 
+//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine code.
+//! Internally, riscv-rt uses different versions of precompiled static libraries 
+//! for (i) machine mode and (ii) sbi. If the `sbi` feature was activated, 
+//! the build script selects the sbi library. While most registers/instructions have variants for 
+//! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor 
+//! mode. Instead, the hartid is passed as parameter by the calling SBI.
+//! 
+//! QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
+//! ``` text
+//! APP_BINARY=$(find target -name app)
+//! sudo qemu-system-riscv64 -m 2G -nographic -machine virt -kernel $APP_BINARY
+//! ```
+//! It requires the memory layout to be non-overlapping, like
+//! ``` text
+//! MEMORY
+//! {
+//!   RAM : ORIGIN = 0x80200000, LENGTH = 0x8000000
+//!   FLASH : ORIGIN = 0x20000000, LENGTH = 16M
+//! }
+//! ```
 
 // NOTE: Adapted from cortex-m/src/lib.rs
 #![no_std]
 #![deny(missing_docs)]
 
-use riscv::register::mcause;
+use riscv::register::{scause,mcause,mhartid};
 pub use riscv_rt_macros::{entry, pre_init};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
@@ -361,10 +396,18 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
         fn _setup_interrupts();
 
-        fn _mp_hook() -> bool;
+        fn _mp_hook(hartid: usize) -> bool;
+    }
+
+    // sbi passes hartid as first parameter (a0)
+    let hartid : usize;
+    if cfg!(feature = "sbi") {
+        hartid = a0;
+    } else {
+        hartid = mhartid::read();
     }
 
-    if _mp_hook() {
+    if _mp_hook(hartid) {
         __pre_init();
 
         r0::zero_bss(&mut _sbss, &mut _ebss);
@@ -403,7 +446,7 @@ pub struct TrapFrame {
 
 /// Trap entry point rust (_start_trap_rust)
 ///
-/// `mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
+/// `scause`/`mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
 /// if it's an interrupt or an exception. The result is examined and ExceptionHandler
 /// or one of the core interrupt handlers is called.
 #[link_section = ".trap.rust"]
@@ -415,11 +458,22 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     }
 
     unsafe {
-        let cause = mcause::read();
-        if cause.is_exception() {
+        let code : usize;
+        let is_exception: bool;
+
+        if cfg!(feature = "sbi") {
+            let cause = scause::read();
+            is_exception = cause.is_exception();
+            code = cause.code();
+        } else {
+            let cause = mcause::read();
+            is_exception = cause.is_exception();
+            code = cause.code();
+        }
+
+        if is_exception {
             ExceptionHandler(&*trap_frame)
         } else {
-            let code = cause.code();
             if code < __INTERRUPTS.len() {
                 let h = &__INTERRUPTS[code];
                 if h.reserved == 0 {
@@ -430,7 +484,7 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
             } else {
                 DefaultHandler();
             }
-        }
+        }    
     }
 }
 
@@ -529,9 +583,8 @@ pub unsafe extern "Rust" fn default_pre_init() {}
 #[doc(hidden)]
 #[no_mangle]
 #[rustfmt::skip]
-pub extern "Rust" fn default_mp_hook() -> bool {
-    use riscv::register::mhartid;
-    match mhartid::read() {
+pub extern "Rust" fn default_mp_hook(hartid: usize) -> bool {
+    match hartid {
         0 => true,
         _ => loop {
             unsafe { riscv::asm::wfi() }
@@ -539,14 +592,20 @@ pub extern "Rust" fn default_mp_hook() -> bool {
     }
 }
 
-/// Default implementation of `_setup_interrupts` that sets `mtvec` to a trap handler address.
+/// Default implementation of `_setup_interrupts` that sets `mtvec`/`stvec` to a trap handler address.
 #[doc(hidden)]
 #[no_mangle]
 #[rustfmt::skip]
 pub unsafe extern "Rust" fn default_setup_interrupts() {
-    use riscv::register::mtvec::{self, TrapMode};
     extern "C" {
         fn _start_trap();
     }
-    mtvec::write(_start_trap as usize, TrapMode::Direct);
+
+    if cfg!(feature = "sbi") {
+        use riscv::register::stvec::{self, TrapMode};
+        stvec::write(_start_trap as usize, TrapMode::Direct);
+    } else {
+        use riscv::register::mtvec::{self, TrapMode};
+        mtvec::write(_start_trap as usize, TrapMode::Direct);        
+    }
 }

From 7d5d5873bfe94e72ebaadfc86e7cbbaf9bd652ae Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Thu, 15 Sep 2022 15:56:07 +0200
Subject: [PATCH 184/234] SBI: upload static libs

---
 riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a  | Bin 0 -> 7732 bytes
 riscv-rt/bin/riscv32i-unknown-none-elf.a      | Bin 7712 -> 7732 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a | Bin 0 -> 7600 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a     | Bin 7588 -> 7608 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a | Bin 0 -> 7736 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a     | Bin 7716 -> 7736 bytes
 .../bin/riscv32ifc-unknown-none-elf-sbi.a     | Bin 0 -> 7604 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a    | Bin 7592 -> 7612 bytes
 .../bin/riscv32ifd-unknown-none-elf-sbi.a     | Bin 0 -> 7740 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a    | Bin 7720 -> 7740 bytes
 .../bin/riscv32ifdc-unknown-none-elf-sbi.a    | Bin 0 -> 7612 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a   | Bin 7600 -> 7620 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a | Bin 0 -> 7420 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a     | Bin 7400 -> 7420 bytes
 .../bin/riscv32imc-unknown-none-elf-sbi.a     | Bin 0 -> 7296 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a    | Bin 7276 -> 7296 bytes
 .../bin/riscv32imf-unknown-none-elf-sbi.a     | Bin 0 -> 7424 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a    | Bin 7404 -> 7424 bytes
 .../bin/riscv32imfc-unknown-none-elf-sbi.a    | Bin 0 -> 7304 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a   | Bin 7284 -> 7304 bytes
 .../bin/riscv32imfd-unknown-none-elf-sbi.a    | Bin 0 -> 7432 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a   | Bin 7412 -> 7432 bytes
 .../bin/riscv32imfdc-unknown-none-elf-sbi.a   | Bin 0 -> 7308 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a  | Bin 7288 -> 7308 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a  | Bin 0 -> 12400 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a      | Bin 12376 -> 12400 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a | Bin 0 -> 12280 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a     | Bin 12248 -> 12280 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a | Bin 0 -> 12408 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a     | Bin 12376 -> 12408 bytes
 .../bin/riscv64ifc-unknown-none-elf-sbi.a     | Bin 0 -> 12280 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a    | Bin 12256 -> 12280 bytes
 .../bin/riscv64ifd-unknown-none-elf-sbi.a     | Bin 0 -> 12408 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a    | Bin 12384 -> 12408 bytes
 .../bin/riscv64ifdc-unknown-none-elf-sbi.a    | Bin 0 -> 12288 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a   | Bin 12264 -> 12288 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a | Bin 0 -> 11888 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a     | Bin 11856 -> 11888 bytes
 .../bin/riscv64imc-unknown-none-elf-sbi.a     | Bin 0 -> 11776 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a    | Bin 11752 -> 11776 bytes
 .../bin/riscv64imf-unknown-none-elf-sbi.a     | Bin 0 -> 11888 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a    | Bin 11864 -> 11888 bytes
 .../bin/riscv64imfc-unknown-none-elf-sbi.a    | Bin 0 -> 11784 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a   | Bin 11760 -> 11784 bytes
 .../bin/riscv64imfd-unknown-none-elf-sbi.a    | Bin 0 -> 11896 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a   | Bin 11872 -> 11896 bytes
 .../bin/riscv64imfdc-unknown-none-elf-sbi.a   | Bin 0 -> 11792 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a  | Bin 11760 -> 11792 bytes
 48 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32ifc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32ifd-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32ifdc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32imc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32imf-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32imfc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32imfd-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv32imfdc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64ifc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64ifd-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64ifdc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64imc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64imf-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64imfc-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64imfd-unknown-none-elf-sbi.a
 create mode 100644 riscv-rt/bin/riscv64imfdc-unknown-none-elf-sbi.a

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..69a8508ae12111165199dc877622e89cc38d5579
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 8894afe85e9b8e719cf590cbffc3d1d16192c62c..4b012b6763b0c06d7261ec3bbe949218daa0189f 100644
GIT binary patch
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diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..31587d81c01ad5d2d6cb05a4f23ef99a9c96759a
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index f110f40c17b2ebc5657fac29d28926baff046ca1..1eda54bcf28bd643f54273e479cfee1b1cc27c48 100644
GIT binary patch
delta 755
zcmYk2&rcIk5Xax_k7kh;iZ-EiTeIyJ8x(cBOX~rHc#~+-7&LGpU?|$EAQmkiOi)2X
zjEN<4g^MxKiw9E=9`tW8TueNB_F%$+0|(~K+Xg0?na}&q&U-WaarFCWD`k}fzvLAI
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delta 663
zcmYk1O-~bH5XYbCZkrlQ3j}RTcX4qERgt)T0~!v-GlwQdA{S!}<)w(c6s(#^`T_(F
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diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..4b67f91c63f9120ebcabe3e905cee0ccfa346971
GIT binary patch
literal 7736
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf.a b/riscv-rt/bin/riscv32if-unknown-none-elf.a
index 7afee313b635a790ae88838fb0341f2579a26504..c8aa87196db0d625cca6fbca4238eff38df8e74c 100644
GIT binary patch
delta 750
zcmYk&&ubGw6bJBm`y*X#(<HXgB)cn{Y#^3u-Rw5;Qamd{iiaYC;Gwk|Yk!!wX%9lR
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z79MINIIT~cPXTld3&wS-CaAMHtU9Pm00>i~S?CA&!r0ZT;}vwx2z0z^mWo9xG#e{3
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brtgujc!=Lz+uTS}qU!(LwE3C}KjhPY*fnlm

delta 678
zcmYk1%S#(k6vpq#ok>zOnI<SPotb#;2t#q<n3oDJbSD%NS`e2O8Xu|8Mvc41_}sWq
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z9J4my96wrpVBt^eDF_^}%P@ycyAQhY!ggXmG{!dNUDWsnezQ%e;BVW71MJD9{sFKM
BX_x>2

diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..7abb52f4f2dd2d74ddc6bdf2d36697e8d8c00285
GIT binary patch
literal 7604
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf.a
index e863bd41d8613cc8d60d735cbffe64227c76db42..670ec4381741f132c7994a290835022e54c403e4 100644
GIT binary patch
delta 673
zcmYk1yHDG25XXOKJC*?x3X0@}*p;cHx;$EvI0*v-&<UxkvJ}CDgi0Ub{b&OlZ-gpT
zh^|s6Bv@z%7L=s}OaFq3v426gO6}Bvf&2X~mH0___wn~0zWX|OHF(@<m7;txn~U<b
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z`%`<In7dQ6By0BYH`VN**%qYsx#l5-_5)_=AMezkwvAgG?^&`bK$ZEP<Z0%F<Q3+m
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delta 709
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diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..0b0c7cb54c54346aa55c817c5842cb9f41c22bee
GIT binary patch
literal 7740
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
index 8fa49cec31b1711cba0e0d7b6244865cd369ee0d..1de4e64732323f37d62d1b808418630785b60f17 100644
GIT binary patch
delta 666
zcmYk3yHDFt6vpp~?O-4eQbjT*Hgf6+7l9zbBy?cuR;d!G1FDeNO3OQiPyz!I?+76V
zqQlw^sdQ}9ks<2dp+i-%ATd_z)W3jp?+Jpz=ll6P-#xxZz8t?AKkG3|;YcxG2*di*
z+3Y=gULl{)KdPnDsOOCpOZCtFu>JMdHvk)FG#8s%4ikC|2lWZ!?l!$$2+&MyMl77t
zri>E+ErMBnnz~U+R?;d#DFGmi2&vGn@LaEH#i0VaMhF_dHgd6m8kL3hw^acy?irSD
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zZd^RdT*}N5mML?9wWM#?IP;Pub<8Yl>Y(u>`NrJYU@JxfRpu_qv&?D973OZq>&%Yi
zkIYfYOU&x*GP6AEuRL(j^3|L&`#W-w|AAj52d#!j46E$tNc^=24qCn`Gw;|}3%qAm
zmzZN#3(PaC4=*sQ1r|lavacZ$OW^;W2}t9M%p`bNr#gtYRJX9;Y(f*iI0Mj&znxd`
o9JB5u?Bbd`0MGD~>&O4;^k?WQa{4a*bThDxf878sFx6|_0k9lpj{pDw

delta 722
zcmYMv&ubGw6bJBmo!vCj#5K{9AG-^q8we!_x6Kb*=|K;IA~bji{sG1|)oQiX_L#O>
z1@VyZJcxKy>_HE8FCG-?pWvn7QBV2@2qK8SnYT*@X5MGNZ)bMr<NV(Ipqy^DX6tid
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zBUj@*t>5W#ZZ2@0ZGK{rZ7#6HHXrV>%>|Z4R4aXjvENxtxeFk$<F+A#uW2pfFIu~J
z!P|tl_{pn*hd;f`P{F3(h85iPYvg@D$o{Z|*rH$2r}y!j??Mm%`c->C!66RI$NvK&
CzG%1r

diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..39cc21f0560a199f16e07f26eeb2da1a5a5fb0f0
GIT binary patch
literal 7612
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literal 0
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diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
index 8c98e12cdfdd28b7516bf5873add32c367d2dc5a..8086113f3afedd8175f968cd147025516c8d8f26 100644
GIT binary patch
delta 735
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delta 723
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diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..0e7ca1500a06528844631897f6d45b5cd50efc1f
GIT binary patch
literal 7420
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index b460f2c1bb6c5f8cd789264791fe6ba52ddfa56b..45dafb4db9b2e673a6b85f4a20c4af28f341cb35 100644
GIT binary patch
delta 677
zcmYk1&r4KM6vyv*KXS_Pp&>kH-b>!hQw9<2&3n$6(88r)G(;O0l{rr7_@i`$5r5<;
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delta 731
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L!$KV3Sof84MaODo

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..fee0b02536325f32a427087a8abaf6424f78e7dd
GIT binary patch
literal 7296
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 374f06b5eb4143392b6d136d7c951ead1c899e0f..1d28508c3b839d02e6e2eb376a64357870e1c56a 100644
GIT binary patch
delta 721
zcmYk&&1(};5CHI*-51@~jdX2klHDlVrn+sVHJg}JLGUP|n2Ul?skPsqY9lIYZ0bP|
zo-Fehc=9a4TMvr<0rsFG2!7z92k{T^<ji{;+JTw(+j$?mZ~vUyIQ_zRs^wCp7?(?%
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z*3HtDJ+rsjLDCnucTKXr1{aPEPOm8fIL7Hc(bQ$6(ON(FeScH-a=4thrU_l*>&89e
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EAI8~Yr2qf`

delta 715
zcmYk4Jxmlq6vyZ7?BRjyAq3dF+bah4!UYLo;o!I{)X+&ZxyFKoM8G=~kk2DgzM(R)
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zyt^=q8(tYc;-S|IS^VqyJw=<IjE<tauhXE^JfZ$^B#nC9!O=`EdE6nyN!=oah%W%C
Cona3E

diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imf-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..467fd6acac9b8222e9224cf8f78d92758b41ce8f
GIT binary patch
literal 7424
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MZX7%I&TVr40bDZu-~a#s

literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf.a b/riscv-rt/bin/riscv32imf-unknown-none-elf.a
index 929902b898ec39b611e0dc06ef38ace045c460c9..bfc8eb27e89c04126679eddd0d27431c82437775 100644
GIT binary patch
delta 722
zcmYk%Pe>GT6bJC%n?JecD6R_Y?o2V;3X=#r>$n?<hlCD>(AGh^2<oc2{;f7pG;0g?
zAko3)T@pkHin@fzB6zTK=Pp4c1VXnub_?<Ses7j_;P>8VzP~>+zdtu$4sItR*`Pn;
zr-Pt!Z6;Z>>!y9*zfiN;0oT3JKT!GD4Yv-y?Ll+AQ3%jMRRiDY89dP~{Gu&2L{z4s
zua9W20r#~$O%*!~8PgB|!qlh>{TTDcmY(TN<6k2H9g}94<<UfO{^|6pfGc?4j2RKQ
z+=K^)Q!SgPCbU%_G$jGIth>ao)&ktwkVgqorqNkc6mO^{p4A;N#Wr<2%%yAjE;;rb
zH(L6}UhvZQ7iK?^?J$?F?Rra&Zc?G=h(@%eC`P1Tv1N^JR?k{~HIyE6WKn}B>{jUs
zc8BybyHk3F?MOdjUy^>vR(t2za&M|ow-@H>oO#Ym@}SfLzes!GgiD4+&bz3kmg@Gx
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zaoO&HtGHv2!hig2=ioMGoF2H2Q%<V+*bu^{Kaq#8W5u!I1V1~TS%?Yo9f#xX=ad*`
APXGV_

delta 719
zcmYk)Pe>GT6bJC%+nF(?Vbw*Mo!vQ%&BA5|j=Q?LQHO3u!V-83DqS_Vv~)$QHPfJj
zkcjdw9U|yd7X_V*9TL3N(Mu2nfhP&2vnPFT-Yz=u`@PS6e}CrpgIT(9lwV8K_vHGr
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z*w4gu>``&Jc1+A`y~pQHSMzY6amg2XBd;Vc>~wX&CBqZRQ&haC=T2AidY<!8^6&zW
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z7Y^|xSpXmJI319}S;uSN(UoeVlkny*snM(A1Mq*NQL8;aaL-A{2Q8(3)gr1;^%?AT
BWM%*W

diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..4c9e61a9610057090cd1c4c83e8650c93c1d7275
GIT binary patch
literal 7304
zcmcIoZH!b`89rxcS?Kc7U7!oyrF6JU&jP}*y93)o5tdz8zLo_R7tpp0GrO}ebiX<?
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literal 0
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diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf.a
index 13d1f2171ccb6fab0a1f353d6202d6bde4388480..978c886c8929ed42fb9b29728e47e85174ad0a5f 100644
GIT binary patch
delta 733
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delta 656
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diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..6ee7e54859c7ac00878971168be08660edce2482
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf.a
index 96d34eecae575ac210d9be086e37e018e152d610..343f4c2aef7d46ec9d65c0b1ab364e905ba8a724 100644
GIT binary patch
delta 735
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delta 661
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diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..8c09102c4ba15a615b68ff229f22c1e2a4aaddab
GIT binary patch
literal 7308
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diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
index 2403fb0e916edcabd750069b6ddef6bb6fbe284b..385e9a84005557e733e223b2c23b8650a3f1ae58 100644
GIT binary patch
delta 663
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delta 714
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diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..29c790a2857fe75b84f0b632ae1228328e92c062
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index e6cee106cb761b6b392b7fea4c7344d8abd6a0fe..77cc42dbc5b2227d5dde4f132711331bcc10854c 100644
GIT binary patch
delta 670
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delta 606
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diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..35d6d91ba748da35f8f4a8f7c9b6d2dc1e4c0ff8
GIT binary patch
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diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index 375ecb0e3c71df739e8dd9da96029d5e69b3c029..6e0410a723083f905d21a58d2fc28fb86fc9d5b6 100644
GIT binary patch
delta 674
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delta 683
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diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..36bfce073da288c13fe49bf1ec47cc8a3d745e0c
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
index 216a89d3fac5a709b18d11af05a94ef5fa86a636..633ad9190e8a274e500dc1a953a9945ec38df401 100644
GIT binary patch
delta 679
zcmYjOOKTHh6rDSdG}Q?vY2qYBV@xG8&?NI{8@lnaOBNy(S5ma0K7+=_RO><|i)yWk
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delta 637
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diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..011281003f85ce4f59c7586a78c3527e6bcc5e01
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf.a
index 352517453fc6ee3f8297f7e73682f76881a2b1dd..8200507efe993bc2e924f338aaafb8b9cdd57a00 100644
GIT binary patch
delta 615
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delta 665
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diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..f500705df35b57593fd6bf6ccd09e9527a600c78
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
index 9bda8c4131f5e8fc6c8f5c0694acfa592129b1b1..621f1556d9558d13801704d4f2b9f04fe621770a 100644
GIT binary patch
delta 632
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delta 619
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Bh}8f9

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..0ecce8dd3f41d1837deb3d5d9b8e24c0851c8ef4
GIT binary patch
literal 12288
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
index f7a2c96968674193184bb62ca225c9322f784547..ebbf2f69f8f3673c699fb385547140f35da43ab0 100644
GIT binary patch
delta 655
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delta 636
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diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..d5a32897e47ea75875d3d5da02a259ede487cffd
GIT binary patch
literal 11888
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index b3fd5ac694b92d25d0f98fb0b27cc09e459c7a80..e2fc324ceaa61ca0cf0d66c74007fc0b29249838 100644
GIT binary patch
delta 655
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delta 638
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diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..2bb848e4e901e240470e6f6318eca5e378d61a21
GIT binary patch
literal 11776
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 94c9b08b95dc0bd64825eae787ea1de46cdd7340..417487034ffb4dac315c4f83dbf436d779fafc2d 100644
GIT binary patch
delta 661
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delta 643
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diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imf-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..026428372643beaadb80e7fe8b73ee39b7be3a86
GIT binary patch
literal 11888
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf.a b/riscv-rt/bin/riscv64imf-unknown-none-elf.a
index a5f60d0c43acaca0df7b2f305f19915d960c1d4d..3667454a41222a8ced98b460b52b61a1015e6bbe 100644
GIT binary patch
delta 645
zcmYk2%WD%+6vpSw+@w(_<TW}@X-d$^G)*$iOk!g|#O&%q3ogZ$YAxEA5~@fRO~=<t
zsHFWwaG~f%5EK%!wc^6=?B2&lw<2i&fP(jq6X=EeeP@2>-tS!I%hcbg_F$x1DUUmD
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z)=FH@bM?^DbmKms(O+kSBEkJ3pOfODjJ)2q_9uqVrW#d)1H^p=JEm@24u~)<s73cC
z_DmhctQsBKM;mx<>U14@NgcPd8X8$<EChXFM}s=YeIDys-B=8WFhRvK`Ch_SR;NX@
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W_>bZ}tJt;+)WNQOhUVdpjr;=>M2PAD

delta 617
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Je@5Fo_#YXmh#~+0

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..c9dc0813d6a8e3e706f89d68fdd901a6ba141e21
GIT binary patch
literal 11784
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf.a
index 16414444fc4019d9a4c665ae394d89ce773de248..2976e285a0985a49d6dd471882a1a88b8fc14f09 100644
GIT binary patch
delta 658
zcmYk1PiPZS5XN`*?WU>jlFc8xMl=m=Hf)-#*%%vg5DJ3CLWFwoVjHy7f7KMJg7(n5
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z5t_w`jE?z?qH6vyaXpI#PM>qSH$boA1*dgRLjigbUov{~l21J8zR7Su4b{;11iNW(
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mwBUF%g&J9iS|jS5(z)V&bRG>WPsg!rjr0oH4*!U#+5aE;mXA3A

delta 655
zcmYk2!D|yy5XN`*ZI-CJ8k23;NGOZVhHR3hTTMcWR>4cW2=;1QOsv|5wrDFA!L~{1
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dE5Sb$&v}FeH%lJ2+)GEk*&OiraL}1P`X3;dka_?B

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..e5b2922c46327ff74662c753444a1c310df0a993
GIT binary patch
literal 11896
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
index 47ba78e5f40a1641998a9a37f544aa9b40a8d7d7..8a70b49567cb1d013a5bff045e34298307eebb7b 100644
GIT binary patch
delta 634
zcmYjMO-vI}7~F5)wiMZwmaZ-}{A{qhDYQ$slvWx;&=Xwb=D|pU1W}O^Q4{4Lu2oN-
zz`;Zlxe`5+jfo^R;K9U$y_%>ofr~K&<5h0HZMVt3!_2(-=6#d5H}!97^;D#oA1c_n
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R?{Q>}wJw<r|0^n~-v6&<h-Ux*

delta 620
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Is0^L_2f%2E2LJ#7

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf-sbi.a
new file mode 100644
index 0000000000000000000000000000000000000000..6040a04e94c2239d0904e98ab9ed6c33e2585867
GIT binary patch
literal 11792
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literal 0
HcmV?d00001

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
index 7866563c2081aaeeef2eb5f7a82950dbb953136d..2fc054c389bb3b39ecdb43245a987970f40b6519 100644
GIT binary patch
delta 664
zcmYk1KWGzi6vyw~@9uil3%Mk1&j`lY=3?69%w1zo2SE`e1R})2#TvBKf7KSLf_7+)
zRR^m}>UULV1%;I8R?x*ELs1v0ppr!g7hT+x`n%);_lEcVzR!EV_xSyute>v$RNcb(
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z98VcoOlcwAA11D6vBc>MPIm<8RlMZ1%&8Kf7x6V^#4q{8lir&Y_cI8Y#$d3U^hS7y
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zh6Pij^RUteU1%Ol-xaBiR;EVJP#Ue#TeNuIL}{!>4YbDI&=IU;i<H2}>`k&!%5`RP
lMH)xMIxx5?b#E+aUG=`Zh^m#P3RbMc{c5_)KOvIY{U3XQkCXra

delta 649
zcmYk1O=}ZT6o%)_oe34EWZER1Mrs}HOh}W)Of-op3W^}vSgBjvV$q_EwNfK~fTn42
zBchP<g1Au>++^XRj0+cn{Q(xcQE=CdV#Lz=12o>-+(7T*JnwnW7q>pSJyGA+RVbE@
zj(SCJ`OwTzN85JJ^E}%gEfwq?UCie>bA?iVxsj#Sm2ans_F{=ym}Dum)DT{>3m9j;
z_^gIV!+BoWRFCT|g_w#JR>lS!<UJugVFo_16Cx)<i}lf4^l9(d5k<k8Ho?7NJ!xbV
zMXC6=F5gjT2vhn&RJ6h1jsB|(=faNzFKiPw%zliU&w_vE526S7-kYT=Vi6I~@L0p`
z$VFPj7p@nfN3-z-zO(b{QuJ^xVJvFVL)_FNy12U#RHIvAn#Y`D;ksjVo3fcWD|q2p
z@j2-T^h+(OH?YQMKJl5*F82!lI#%qebObsx4tiV*r(7+*yK2i$mD9(RYsIfgM<6M+
zppU1n6`PfgKuKx`uleS6SEE^Rou;wL^WUz~ZOaa^{Sx*kEDR(JJa-M6!5GiZCX8S{
zaZjaHG?O)Y1b?_juh8W2J^WOS>S(4ul8r{XOau6nzDp+jk)58AG95-Pb1b&5wXaMY
ZZHf=yM>Ufs4~@*pJwM&H{}s99f&Y!JkRSj6


From 67b2fcd8f6c3ed235b5e88a385b5fda8b7b881b9 Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Fri, 16 Sep 2022 19:13:19 +0200
Subject: [PATCH 185/234] SBI: fix formatting and CHANGELOG

---
 riscv-rt/CHANGELOG.md |  5 +++++
 riscv-rt/build.rs     |  2 +-
 riscv-rt/src/lib.rs   | 34 +++++++++++++++++-----------------
 3 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index b2337141..0b195276 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,9 +7,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Optional cargo feature `sbi` for SBI compatibility, including conditional compilation for machine mode instructions.
+
 ### Changed
 
 - Remove superfluous parentheses from link.x, which caused linker errors with nightly.
+- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `sbi` feature).
 
 ## [v0.9.0] - 2022-07-01
 
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 9eea713c..e0382da8 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -14,7 +14,7 @@ fn main() {
     if target.starts_with("riscv") {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imfdc");
-        let archive:String;
+        let archive: String;
         if cfg!(feature = "sbi") {
             println!("======== compiling riscv-rt for sbi");
             archive = format!("bin/{}-sbi.a", target.to_string());
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 39769edf..3d0918fd 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -21,8 +21,8 @@
 //!   filename can be use instead of `memory.x`.
 //!
 //! - A `_sheap` symbol at whose address you can locate a heap.
-//! 
-//! - Support for a runtime in supervisor mode, bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc) 
+//!
+//! - Support for a runtime in supervisor mode, bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
 //!
 //! ``` text
 //! $ cargo new --bin app && cd $_
@@ -322,25 +322,25 @@
 //! ```
 //!
 //! Default implementation of this function stucks in a busy-loop.
-//! 
+//!
 //! # Features
-//! 
+//!
 //! ## `sbi`
-//! 
+//!
 //! The SBI runtime feature (`sbi`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
-//! 
-//! For example: 
+//!
+//! For example:
 //! ``` text
 //! [dependencies]
 //! riscv-rt = {features=["sbi"]}
-//! ``` 
+//! ```
 //! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine code.
-//! Internally, riscv-rt uses different versions of precompiled static libraries 
-//! for (i) machine mode and (ii) sbi. If the `sbi` feature was activated, 
-//! the build script selects the sbi library. While most registers/instructions have variants for 
-//! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor 
+//! Internally, riscv-rt uses different versions of precompiled static libraries
+//! for (i) machine mode and (ii) sbi. If the `sbi` feature was activated,
+//! the build script selects the sbi library. While most registers/instructions have variants for
+//! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor
 //! mode. Instead, the hartid is passed as parameter by the calling SBI.
-//! 
+//!
 //! QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
 //! ``` text
 //! APP_BINARY=$(find target -name app)
@@ -359,7 +359,7 @@
 #![no_std]
 #![deny(missing_docs)]
 
-use riscv::register::{scause,mcause,mhartid};
+use riscv::register::{mcause, mhartid, scause};
 pub use riscv_rt_macros::{entry, pre_init};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
@@ -400,7 +400,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
     }
 
     // sbi passes hartid as first parameter (a0)
-    let hartid : usize;
+    let hartid: usize;
     if cfg!(feature = "sbi") {
         hartid = a0;
     } else {
@@ -458,7 +458,7 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     }
 
     unsafe {
-        let code : usize;
+        let code: usize;
         let is_exception: bool;
 
         if cfg!(feature = "sbi") {
@@ -484,7 +484,7 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
             } else {
                 DefaultHandler();
             }
-        }    
+        }
     }
 }
 

From 3e4c04f53780dabcb27ed5f17e40d8a9ca80e082 Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Sat, 17 Sep 2022 01:14:46 +0200
Subject: [PATCH 186/234] SMODE: rename feature sbi to s-mode

---
 riscv-rt/CHANGELOG.md           |  4 ++--
 riscv-rt/Cargo.toml             |  2 +-
 riscv-rt/asm.S                  |  8 ++++----
 riscv-rt/assemble.sh            | 10 +++++-----
 riscv-rt/build.rs               |  6 +++---
 riscv-rt/examples/multi_core.rs |  3 +--
 riscv-rt/src/lib.rs             | 24 ++++++++++++------------
 7 files changed, 28 insertions(+), 29 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 0b195276..251205d6 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -9,12 +9,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
-- Optional cargo feature `sbi` for SBI compatibility, including conditional compilation for machine mode instructions.
+- Optional cargo feature `s-mode` for supervisor mode, including conditional compilation for supervisor/machine mode instructions.
 
 ### Changed
 
 - Remove superfluous parentheses from link.x, which caused linker errors with nightly.
-- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `sbi` feature).
+- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `s-mode` feature).
 
 ## [v0.9.0] - 2022-07-01
 
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index aa1ecb95..31f74450 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -11,7 +11,7 @@ license = "ISC"
 edition = "2018"
 
 [features]
-sbi = []
+s-mode = []
 
 [dependencies]
 r0 = "1.0.0"
diff --git a/riscv-rt/asm.S b/riscv-rt/asm.S
index 4a4eecbb..17f10937 100644
--- a/riscv-rt/asm.S
+++ b/riscv-rt/asm.S
@@ -46,7 +46,7 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
-    #ifdef SBI
+    #ifdef SMODE
     csrw sie, 0     // interrupt disable 
     csrw sip, 0     // no pending interrupts
     #else
@@ -90,9 +90,9 @@ _abs_start:
     la gp, __global_pointer$
     .option pop
 
-    #ifdef SBI
+    #ifdef SMODE
     // there is no equivalent of mhartid in supervisor mode.
-    // instead, the hartid is passed as paramter by SBI
+    // instead, the hartid is passed as paramter by SMODE
     mv t2, a0   
     #else 
     csrr t2, mhartid
@@ -176,7 +176,7 @@ default_start_trap:
     LOAD a7, 15*REGBYTES(sp)
 
     addi sp, sp, 16*REGBYTES
-    #ifdef SBI
+    #ifdef SMODE
     sret
     #else
     mret
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
index de38c244..296a6dd6 100755
--- a/riscv-rt/assemble.sh
+++ b/riscv-rt/assemble.sh
@@ -32,12 +32,12 @@ do
     riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
 
-    #sbi
-    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-sbi.a bin/$crate.o
+    #s-mode
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
 
-    riscv64-unknown-elf-gcc -DSBI -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-sbi.a bin/$crate.o
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
 
 done
 
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index e0382da8..aa987ad4 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -15,9 +15,9 @@ fn main() {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("imfdc");
         let archive: String;
-        if cfg!(feature = "sbi") {
-            println!("======== compiling riscv-rt for sbi");
-            archive = format!("bin/{}-sbi.a", target.to_string());
+        if cfg!(feature = "s-mode") {
+            println!("======== compiling riscv-rt for s-mode");
+            archive = format!("bin/{}-smode.a", target.to_string());
         } else {
             archive = format!("bin/{}.a", target.to_string());
         }
diff --git a/riscv-rt/examples/multi_core.rs b/riscv-rt/examples/multi_core.rs
index 1df8425e..a3cbab79 100644
--- a/riscv-rt/examples/multi_core.rs
+++ b/riscv-rt/examples/multi_core.rs
@@ -6,13 +6,12 @@ extern crate riscv;
 extern crate riscv_rt;
 
 use riscv::asm::wfi;
-use riscv::register::{mhartid, mie, mip};
+use riscv::register::{mie, mip};
 use riscv_rt::entry;
 
 #[export_name = "_mp_hook"]
 #[rustfmt::skip]
 pub extern "Rust" fn user_mp_hook(hartid: usize) -> bool {
-    let hartid = mhartid::read();
     if hartid == 0 {
         true
     } else {
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 3d0918fd..ce19c668 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -22,7 +22,7 @@
 //!
 //! - A `_sheap` symbol at whose address you can locate a heap.
 //!
-//! - Support for a runtime in supervisor mode, bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
+//! - Support for a runtime in supervisor mode, that can be bootstrapped via [Supervisor Binary Interface (SBI)](https://github.com/riscv-non-isa/riscv-sbi-doc)
 //!
 //! ``` text
 //! $ cargo new --bin app && cd $_
@@ -325,23 +325,23 @@
 //!
 //! # Features
 //!
-//! ## `sbi`
+//! ## `s-mode`
 //!
-//! The SBI runtime feature (`sbi`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
+//! The supervisor mode feature (`s-mode`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).
 //!
 //! For example:
 //! ``` text
 //! [dependencies]
-//! riscv-rt = {features=["sbi"]}
+//! riscv-rt = {features=["s-mode"]}
 //! ```
-//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine code.
 //! Internally, riscv-rt uses different versions of precompiled static libraries
-//! for (i) machine mode and (ii) sbi. If the `sbi` feature was activated,
-//! the build script selects the sbi library. While most registers/instructions have variants for
+//! for (i) machine mode and (ii) supervisor mode. If the `s-mode` feature was activated,
+//! the build script selects the s-mode library. While most registers/instructions have variants for
 //! both `mcause` and `scause`, the `mhartid` hardware thread register is not available in supervisor
-//! mode. Instead, the hartid is passed as parameter by the calling SBI.
+//! mode. Instead, the hartid is passed as parameter by a bootstrapping firmware (i.e., SBI).
 //!
-//! QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
+//! Use case: QEMU supports [OpenSBI](https://github.com/riscv-software-src/opensbi) as default firmware.
+//! Using the SBI requires riscv-rt to be run in supervisor mode instead of machine mode.
 //! ``` text
 //! APP_BINARY=$(find target -name app)
 //! sudo qemu-system-riscv64 -m 2G -nographic -machine virt -kernel $APP_BINARY
@@ -401,7 +401,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
     // sbi passes hartid as first parameter (a0)
     let hartid: usize;
-    if cfg!(feature = "sbi") {
+    if cfg!(feature = "s-mode") {
         hartid = a0;
     } else {
         hartid = mhartid::read();
@@ -461,7 +461,7 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
         let code: usize;
         let is_exception: bool;
 
-        if cfg!(feature = "sbi") {
+        if cfg!(feature = "s-mode") {
             let cause = scause::read();
             is_exception = cause.is_exception();
             code = cause.code();
@@ -601,7 +601,7 @@ pub unsafe extern "Rust" fn default_setup_interrupts() {
         fn _start_trap();
     }
 
-    if cfg!(feature = "sbi") {
+    if cfg!(feature = "s-mode") {
         use riscv::register::stvec::{self, TrapMode};
         stvec::write(_start_trap as usize, TrapMode::Direct);
     } else {

From 20837cf0680a6ed12b52e9aa110de06d64409c45 Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Sat, 17 Sep 2022 01:17:08 +0200
Subject: [PATCH 187/234] SMODE: upload static libs

---
 ...bi.a => riscv32i-unknown-none-elf-smode.a} | Bin 7732 -> 7732 bytes
 riscv-rt/bin/riscv32i-unknown-none-elf.a      | Bin 7732 -> 7732 bytes
 ...i.a => riscv32ic-unknown-none-elf-smode.a} | Bin 7600 -> 7600 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a     | Bin 7608 -> 7608 bytes
 ...i.a => riscv32if-unknown-none-elf-smode.a} | Bin 7736 -> 7736 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a     | Bin 7736 -> 7736 bytes
 ....a => riscv32ifc-unknown-none-elf-smode.a} | Bin 7604 -> 7604 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a    | Bin 7612 -> 7612 bytes
 ....a => riscv32ifd-unknown-none-elf-smode.a} | Bin 7740 -> 7740 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a    | Bin 7740 -> 7740 bytes
 ...a => riscv32ifdc-unknown-none-elf-smode.a} | Bin 7612 -> 7612 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a   | Bin 7620 -> 7620 bytes
 ...i.a => riscv32im-unknown-none-elf-smode.a} | Bin 7420 -> 7420 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a     | Bin 7420 -> 7420 bytes
 ....a => riscv32imc-unknown-none-elf-smode.a} | Bin 7296 -> 7296 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a    | Bin 7296 -> 7296 bytes
 ....a => riscv32imf-unknown-none-elf-smode.a} | Bin 7424 -> 7424 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a    | Bin 7424 -> 7424 bytes
 ...a => riscv32imfc-unknown-none-elf-smode.a} | Bin 7304 -> 7304 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a   | Bin 7304 -> 7304 bytes
 ...a => riscv32imfd-unknown-none-elf-smode.a} | Bin 7432 -> 7432 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a   | Bin 7432 -> 7432 bytes
 ... => riscv32imfdc-unknown-none-elf-smode.a} | Bin 7308 -> 7308 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a  | Bin 7308 -> 7308 bytes
 ...bi.a => riscv64i-unknown-none-elf-smode.a} | Bin 12400 -> 12400 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a      | Bin 12400 -> 12400 bytes
 ...i.a => riscv64ic-unknown-none-elf-smode.a} | Bin 12280 -> 12280 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a     | Bin 12280 -> 12280 bytes
 ...i.a => riscv64if-unknown-none-elf-smode.a} | Bin 12408 -> 12408 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a     | Bin 12408 -> 12408 bytes
 ....a => riscv64ifc-unknown-none-elf-smode.a} | Bin 12280 -> 12280 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a    | Bin 12280 -> 12280 bytes
 ....a => riscv64ifd-unknown-none-elf-smode.a} | Bin 12408 -> 12408 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a    | Bin 12408 -> 12408 bytes
 ...a => riscv64ifdc-unknown-none-elf-smode.a} | Bin 12288 -> 12288 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a   | Bin 12288 -> 12288 bytes
 ...i.a => riscv64im-unknown-none-elf-smode.a} | Bin 11888 -> 11888 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a     | Bin 11888 -> 11888 bytes
 ....a => riscv64imc-unknown-none-elf-smode.a} | Bin 11776 -> 11776 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a    | Bin 11776 -> 11776 bytes
 ....a => riscv64imf-unknown-none-elf-smode.a} | Bin 11888 -> 11888 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a    | Bin 11888 -> 11888 bytes
 ...a => riscv64imfc-unknown-none-elf-smode.a} | Bin 11784 -> 11784 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a   | Bin 11784 -> 11784 bytes
 ...a => riscv64imfd-unknown-none-elf-smode.a} | Bin 11896 -> 11896 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a   | Bin 11896 -> 11896 bytes
 ... => riscv64imfdc-unknown-none-elf-smode.a} | Bin 11792 -> 11792 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a  | Bin 11792 -> 11792 bytes
 48 files changed, 0 insertions(+), 0 deletions(-)
 rename riscv-rt/bin/{riscv32i-unknown-none-elf-sbi.a => riscv32i-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32ic-unknown-none-elf-sbi.a => riscv32ic-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32if-unknown-none-elf-sbi.a => riscv32if-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32ifc-unknown-none-elf-sbi.a => riscv32ifc-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32ifd-unknown-none-elf-sbi.a => riscv32ifd-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32ifdc-unknown-none-elf-sbi.a => riscv32ifdc-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32im-unknown-none-elf-sbi.a => riscv32im-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32imc-unknown-none-elf-sbi.a => riscv32imc-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32imf-unknown-none-elf-sbi.a => riscv32imf-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32imfc-unknown-none-elf-sbi.a => riscv32imfc-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32imfd-unknown-none-elf-sbi.a => riscv32imfd-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv32imfdc-unknown-none-elf-sbi.a => riscv32imfdc-unknown-none-elf-smode.a} (98%)
 rename riscv-rt/bin/{riscv64i-unknown-none-elf-sbi.a => riscv64i-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64ic-unknown-none-elf-sbi.a => riscv64ic-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64if-unknown-none-elf-sbi.a => riscv64if-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64ifc-unknown-none-elf-sbi.a => riscv64ifc-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64ifd-unknown-none-elf-sbi.a => riscv64ifd-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64ifdc-unknown-none-elf-sbi.a => riscv64ifdc-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64im-unknown-none-elf-sbi.a => riscv64im-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64imc-unknown-none-elf-sbi.a => riscv64imc-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64imf-unknown-none-elf-sbi.a => riscv64imf-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64imfc-unknown-none-elf-sbi.a => riscv64imfc-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64imfd-unknown-none-elf-sbi.a => riscv64imfd-unknown-none-elf-smode.a} (99%)
 rename riscv-rt/bin/{riscv64imfdc-unknown-none-elf-sbi.a => riscv64imfdc-unknown-none-elf-smode.a} (99%)

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32i-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32i-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32i-unknown-none-elf-smode.a
index 69a8508ae12111165199dc877622e89cc38d5579..40260c7fc3d68672f89ecec834fe1b7440fde578 100644
GIT binary patch
delta 27
dcmdmDv&CkD44bi;rLmd$M5Qz+Yh&LsSpak<2si)$

delta 27
dcmdmDv&CkD44aXufuXU{M5Qz+Yh&LsSpae@2o3-M

diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
index 4b012b6763b0c06d7261ec3bbe949218daa0189f..bbf60ba6cd7246091644547cc66d722346da9496 100644
GIT binary patch
delta 27
ecmdmDv&CkD44bi;rLmd$M5Qzc%WPxcGFbq0AqY1B

delta 27
ecmdmDv&CkD44aXufuXU{M5Qzc%Wz}gGFbp}CkPDy

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ic-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32ic-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32ic-unknown-none-elf-smode.a
index 31587d81c01ad5d2d6cb05a4f23ef99a9c96759a..8e74f5eec9760c26f65a9e560755dcc1d4de3f41 100644
GIT binary patch
delta 27
dcmdmBy}^2d44bi;rLmd$M5Qz+Yh$01EC6yG2dV%7

delta 27
dcmdmBy}^2d44aXufuXU{M5Qz+Yh$01EC6sK2Y>(o

diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf.a b/riscv-rt/bin/riscv32ic-unknown-none-elf.a
index 1eda54bcf28bd643f54273e479cfee1b1cc27c48..5418605e17563ffc181dbc67029f2ed178cc0557 100644
GIT binary patch
delta 27
dcmdmCy~BEf44bi;rLmd$M5Qz+Yh$05EC6%N2f_dV

delta 27
dcmdmCy~BEf44aXufuXU{M5Qz+Yh$05EC6xR2bcf=

diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32if-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32if-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32if-unknown-none-elf-smode.a
index 4b67f91c63f9120ebcabe3e905cee0ccfa346971..3fa6ea326a1a0789dfafdcab913ff12f2e2fe9be 100644
GIT binary patch
delta 27
dcmdmCv%_YB44bi;rLmd$M5Qz+Yh&LkSpanY2t)t?

delta 27
dcmdmCv%_YB44aXufuXU{M5Qz+Yh&LkSpahc2pRwY

diff --git a/riscv-rt/bin/riscv32if-unknown-none-elf.a b/riscv-rt/bin/riscv32if-unknown-none-elf.a
index c8aa87196db0d625cca6fbca4238eff38df8e74c..a966014159fa73c391c0f20adf95340604461e94 100644
GIT binary patch
delta 27
dcmdmCv%_YB44bi;rLmd$M5Qz+Yh&LkSpanY2t)t?

delta 27
dcmdmCv%_YB44aXufuXU{M5Qz+Yh&LkSpahc2pRwY

diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32ifc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32ifc-unknown-none-elf-smode.a
index 7abb52f4f2dd2d74ddc6bdf2d36697e8d8c00285..b671efb16879d13fa77bc0becd95ba0498973d08 100644
GIT binary patch
delta 27
dcmdmDy~TQh44bi;rLmdCM5Qz+Yh$09EC6!|2e<$L

delta 27
dcmdmDy~TQh44aXufuXVSM5Qz+Yh$09EC6v12aW&$

diff --git a/riscv-rt/bin/riscv32ifc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifc-unknown-none-elf.a
index 670ec4381741f132c7994a290835022e54c403e4..1d78a2d23f619331a3eb5ea2294a1b9772f2d39a 100644
GIT binary patch
delta 27
dcmdmEy~lcj44bi;rLmdCM5Qz+Yh$0DEC6)42hacj

delta 27
dcmdmEy~lcj44aXufuXU{M5Qz+Yh$0DEC6z<2c!T1

diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32ifd-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32ifd-unknown-none-elf-smode.a
index 0b0c7cb54c54346aa55c817c5842cb9f41c22bee..09b227acc2889518451bcfd86d8f31a15753e1d8 100644
GIT binary patch
delta 27
dcmdmEv&UwF44bi;rLmdCM5Qz+Yh&L!SpaqF2vPt5

delta 27
dcmdmEv&UwF44aXufuXVSM5Qz+Yh&L!SpakJ2q*vm

diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
index 1de4e64732323f37d62d1b808418630785b60f17..549caacd5d4aecaf8f622ecdc86e56350a59a2d8 100644
GIT binary patch
delta 27
dcmdmEv&UwF44bi;rLmdCM5Qz+Yh&L!SpaqF2vPt5

delta 27
dcmdmEv&UwF44aXufuXVSM5Qz+Yh&L!SpakJ2q*vm

diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32ifdc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32ifdc-unknown-none-elf-smode.a
index 39cc21f0560a199f16e07f26eeb2da1a5a5fb0f0..9729b5adcb77478b99787577c4b3fe2637bbd905 100644
GIT binary patch
delta 27
dcmdmEy~lcj44bi;rLmdCM5Qz+Yh$0DEC6)42hacj

delta 27
dcmdmEy~lcj44aXufuXVSM5Qz+Yh$0DEC6!82c`f3

diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
index 8086113f3afedd8175f968cd147025516c8d8f26..626737a414f0a0f301edd439797c79f838cd8807 100644
GIT binary patch
delta 27
dcmX?NeZ+c#44bi;rLmdCM5Qz+Yh$08EC6<B2j~C*

delta 27
dcmX?NeZ+c#44aXufuXVSM5Qz+Yh$08EC6(F2fhFR

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32im-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32im-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32im-unknown-none-elf-smode.a
index 0e7ca1500a06528844631897f6d45b5cd50efc1f..a035e3a4bfbcbd514648616f8a0f444c80a084df 100644
GIT binary patch
delta 27
dcmexk`NwjC44bi;rLmd$M5Qz+Yhz!Y3;=<@2#Ejy

delta 27
dcmexk`NwjC44aXufuXU{M5Qz+Yhz!Y3;=({2wwmI

diff --git a/riscv-rt/bin/riscv32im-unknown-none-elf.a b/riscv-rt/bin/riscv32im-unknown-none-elf.a
index 45dafb4db9b2e673a6b85f4a20c4af28f341cb35..50720ea64a69bde483a81941021212d72fe5b2cf 100644
GIT binary patch
delta 27
dcmexk`NwjC44bi;rLmd$M5Qz+Yhz!Y3;=<@2#Ejy

delta 27
dcmexk`NwjC44aXufuXU{M5Qz+Yhz!Y3;=({2wwmI

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imc-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32imc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32imc-unknown-none-elf-smode.a
index fee0b02536325f32a427087a8abaf6424f78e7dd..656b17ca2221488508b70362dcafadccdb9f672c 100644
GIT binary patch
delta 27
dcmZp$Y_Oal!)9z|X>4XbQ7H||+SvC=8USgQ2owMS

delta 27
dcmZp$Y_Oal!)9b^U}$VKQ7H||+SvC=8USaU2kHO-

diff --git a/riscv-rt/bin/riscv32imc-unknown-none-elf.a b/riscv-rt/bin/riscv32imc-unknown-none-elf.a
index 1d28508c3b839d02e6e2eb376a64357870e1c56a..7c7806a0c792ceaf625f448fb3cfd7c9e7fcd403 100644
GIT binary patch
delta 27
dcmZp$Y_Oal!)9z|X>4XbQ7H||+SvC=8USgQ2owMS

delta 27
dcmZp$Y_Oal!)9b^U}$VKQ7H||+SvC=8USaU2kHO-

diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imf-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32imf-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32imf-unknown-none-elf-smode.a
index 467fd6acac9b8222e9224cf8f78d92758b41ce8f..837b09d8b4a710fac68043a03ea660bf3e32a39c 100644
GIT binary patch
delta 27
dcmZp$YOtCh!)9z|X>4XOQ7H||+Spel0|02<2bll>

delta 27
dcmZp$YOtCh!)9b^U}$VSQ7H||+Spel0{~{@2X6oX

diff --git a/riscv-rt/bin/riscv32imf-unknown-none-elf.a b/riscv-rt/bin/riscv32imf-unknown-none-elf.a
index bfc8eb27e89c04126679eddd0d27431c82437775..af20afbd582b0f160a0385d4864873f5f7cacc74 100644
GIT binary patch
delta 27
dcmZp$YOtCh!)9z|X>4XOQ7H||+Spel0|02<2bll>

delta 27
dcmZp$YOtCh!)9b^U}$VSQ7H||+Spel0{~{@2X6oX

diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32imfc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32imfc-unknown-none-elf-smode.a
index 4c9e61a9610057090cd1c4c83e8650c93c1d7275..f1e86383bec12df9512e0c01f02974ec2680e66c 100644
GIT binary patch
delta 27
dcmeCM?6905!)9z|X>4XOQ7H||+SvC?8USlr2rd8s

delta 27
dcmeCM?6905!)9b^U}$VSQ7H||+SvC?8USfv2m}BC

diff --git a/riscv-rt/bin/riscv32imfc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfc-unknown-none-elf.a
index 978c886c8929ed42fb9b29728e47e85174ad0a5f..08443736149fbd781df5cd170dde215795a20762 100644
GIT binary patch
delta 27
dcmeCM?6905!)9z|X>4XOQ7H||+SvC?8USlr2rd8s

delta 27
dcmeCM?6905!)9b^U}$VSQ7H||+SvC?8USfv2m}BC

diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32imfd-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32imfd-unknown-none-elf-smode.a
index 6ee7e54859c7ac00878971168be08660edce2482..8f27bd4c1151d621b737a6ba12468d0a5da2d61e 100644
GIT binary patch
delta 27
dcmeCM>adz1!)9z|X>4XOQ7H||+Spem0|07`2eAME

delta 27
dcmeCM>adz1!)9b^U}$VSQ7H||+Spem0|01~2ZsOv

diff --git a/riscv-rt/bin/riscv32imfd-unknown-none-elf.a b/riscv-rt/bin/riscv32imfd-unknown-none-elf.a
index 343f4c2aef7d46ec9d65c0b1ab364e905ba8a724..a6e8387f1dd08bb1f61d6c55ce891347595ef35e 100644
GIT binary patch
delta 27
dcmeCM>adz1!)9z|X>4XOQ7H||+Spem0|07`2eAME

delta 27
dcmeCM>adz1!)9b^U}$VSQ7H||+Spem0|01~2ZsOv

diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf-smode.a
similarity index 98%
rename from riscv-rt/bin/riscv32imfdc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv32imfdc-unknown-none-elf-smode.a
index 8c09102c4ba15a615b68ff229f22c1e2a4aaddab..e8b0c4b63227dc2900c123bd662ab6e03b7c0ecc 100644
GIT binary patch
delta 27
bcmeCN?6I66!)9z|2}Bc>(x9x3egC8ZY(@w?

delta 27
ecmeCN?6I66!)9b^U}$VIQ7H|=GTzwtPZ|JfM+gxB

diff --git a/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
index 385e9a84005557e733e223b2c23b8650a3f1ae58..83ffff761ac618367f45016fda03132f431e1cd8 100644
GIT binary patch
delta 27
bcmeCN?6I66!)9z|2}Bc>(x9x3egC8ZY(@w?

delta 27
dcmeCN?6I66!)9b^U}$VSQ7H||+SvC`8USiI2oL}O

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64i-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64i-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64i-unknown-none-elf-smode.a
index 29c790a2857fe75b84f0b632ae1228328e92c062..58f194262d124194f763e618ad4a9e20b6664ba3 100644
GIT binary patch
delta 27
dcmey6@F8J>44bi;rLmd$M5Qz+Yh&LdeE^5(2}S?_

delta 27
dcmey6@F8J>44aXufuXU{M5Qz+Yh&LdeE@~-2^;_b

diff --git a/riscv-rt/bin/riscv64i-unknown-none-elf.a b/riscv-rt/bin/riscv64i-unknown-none-elf.a
index 77cc42dbc5b2227d5dde4f132711331bcc10854c..c4bb936f51d0b335f23e0408ac76b5ad6d270a08 100644
GIT binary patch
delta 27
dcmey6@F8J>44bi;rLmd$M5Qz+Yh&LdeE^5(2}S?_

delta 27
dcmey6@F8J>44aXufuXU{M5Qz+Yh&LdeE@~-2^;_b

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ic-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64ic-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64ic-unknown-none-elf-smode.a
index 35d6d91ba748da35f8f4a8f7c9b6d2dc1e4c0ff8..a078472bfa8a627df9dba5bf5ab150cfb161e589 100644
GIT binary patch
delta 27
dcmewn|08~a44bi;rLmd$M5Qz+Yhz!QJ^+Yj2;2Yw

delta 27
dcmewn|08~a44aXufuXU{M5Qz+Yhz!QJ^+Sn2(kbG

diff --git a/riscv-rt/bin/riscv64ic-unknown-none-elf.a b/riscv-rt/bin/riscv64ic-unknown-none-elf.a
index 6e0410a723083f905d21a58d2fc28fb86fc9d5b6..ee453fe279ba43f25b40f04aca7f7b98835f7710 100644
GIT binary patch
delta 27
dcmewn|08~a44bi;rLmd$M5Qz+Yhz!QJ^+Yj2;2Yw

delta 27
dcmewn|08~a44aXufuXU{M5Qz+Yhz!QJ^+Sn2(kbG

diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64if-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64if-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64if-unknown-none-elf-smode.a
index 36bfce073da288c13fe49bf1ec47cc8a3d745e0c..310211ff4878237048aba3a98603717e5eef929d 100644
GIT binary patch
delta 27
dcmey7@FQV@44bi;rLmd$M5Qz+Yh&LleE^A=30?pI

delta 27
dcmey7@FQV@44aXufuXU{M5Qz+Yh&LleE^4^2{Zrz

diff --git a/riscv-rt/bin/riscv64if-unknown-none-elf.a b/riscv-rt/bin/riscv64if-unknown-none-elf.a
index 633ad9190e8a274e500dc1a953a9945ec38df401..2b52368c11fa6f5e57d4b770f886762ce08ae58a 100644
GIT binary patch
delta 27
dcmey7@FQV@44bi;rLmd$M5Qz+Yh&LleE^A=30?pI

delta 27
dcmey7@FQV@44aXufuXU{M5Qz+Yh&LleE^4^2{Zrz

diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64ifc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64ifc-unknown-none-elf-smode.a
index 011281003f85ce4f59c7586a78c3527e6bcc5e01..907e93809bc54f4012554db49313197ab88c5df6 100644
GIT binary patch
delta 27
dcmewn|08~a44bi;rLmdCM5Qz+Yhz!QJ^+Y%2;Kky

delta 27
dcmewn|08~a44aXufuXVSM5Qz+Yhz!QJ^+S*2($nI

diff --git a/riscv-rt/bin/riscv64ifc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifc-unknown-none-elf.a
index 8200507efe993bc2e924f338aaafb8b9cdd57a00..04573b2dc43559c6396d4a5b8181663b58837286 100644
GIT binary patch
delta 27
dcmewn|08~a44bi;rLmdCM5Qz+Yhz!QJ^+Y%2;Kky

delta 27
dcmewn|08~a44aXufuXU{M5Qz+Yhz!QJ^+Sn2(kbG

diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64ifd-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64ifd-unknown-none-elf-smode.a
index f500705df35b57593fd6bf6ccd09e9527a600c78..60c99cda1e1d5e67aa8acd59453e75e6fc89ef3b 100644
GIT binary patch
delta 27
dcmey7@FQV@44bi;rLmdCM5Qz+Yh&LleE^B9319#K

delta 27
dcmey7@FQV@44aXufuXVSM5Qz+Yh&LleE^5D2{r%#

diff --git a/riscv-rt/bin/riscv64ifd-unknown-none-elf.a b/riscv-rt/bin/riscv64ifd-unknown-none-elf.a
index 621f1556d9558d13801704d4f2b9f04fe621770a..f75a8874055a0de647681942e3927d73aeea1908 100644
GIT binary patch
delta 27
dcmey7@FQV@44bi;rLmdCM5Qz+Yh&LleE^B9319#K

delta 27
dcmey7@FQV@44aXufuXVSM5Qz+Yh&LleE^5D2{r%#

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64ifdc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64ifdc-unknown-none-elf-smode.a
index 0ecce8dd3f41d1837deb3d5d9b8e24c0851c8ef4..a038d7d957e92092684d1bd26a25a72bbf597ee0 100644
GIT binary patch
delta 27
dcmZojXh@hK!)9z|X>4XOQ7H||+Spg54*+mn2lxO0

delta 27
dcmZojXh@hK!)9b^U}$VSQ7H||+Spg54*+gr2hIQh

diff --git a/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a b/riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
index ebbf2f69f8f3673c699fb385547140f35da43ab0..fb7fe2f09950a0b6596193146e270f39f5613875 100644
GIT binary patch
delta 27
dcmZojXh@hK!)9z|X>4XOQ7H||+Spg54*+mn2lxO0

delta 27
dcmZojXh@hK!)9b^U}$VSQ7H||+Spg54*+gr2hIQh

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64im-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64im-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64im-unknown-none-elf-smode.a
index d5a32897e47ea75875d3d5da02a259ede487cffd..aafe0a057e9d505b31654b3a4d038e6286fe9ca8 100644
GIT binary patch
delta 27
dcmewm^C4z}44bi;rLmd$M5Qz+Yh&LdT>yt32|NG*

delta 27
dcmewm^C4z}44aXufuXU{M5Qz+Yh&LdT>yn72@(JR

diff --git a/riscv-rt/bin/riscv64im-unknown-none-elf.a b/riscv-rt/bin/riscv64im-unknown-none-elf.a
index e2fc324ceaa61ca0cf0d66c74007fc0b29249838..126631b4d4c7215c81350611915469904d68e523 100644
GIT binary patch
delta 27
dcmewm^C4z}44bi;rLmd$M5Qz+Yh&LdT>yt32|NG*

delta 27
dcmewm^C4z}44aXufuXU{M5Qz+Yh&LdT>yn72@(JR

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imc-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64imc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64imc-unknown-none-elf-smode.a
index 2bb848e4e901e240470e6f6318eca5e378d61a21..d5d0000109f6df083845a053263a9974064081fb 100644
GIT binary patch
delta 27
dcmZpOX^5F1!)9z|X>4XbQ7H||+Spg53jl9^2kZa<

delta 27
dcmZpOX^5F1!)9b^U}$VKQ7H||+Spg53jl3|2f_dV

diff --git a/riscv-rt/bin/riscv64imc-unknown-none-elf.a b/riscv-rt/bin/riscv64imc-unknown-none-elf.a
index 417487034ffb4dac315c4f83dbf436d779fafc2d..6b7f7f7fb19079ab8cddf1168765c12b35e5024c 100644
GIT binary patch
delta 27
dcmZpOX^5F1!)9z|X>4XbQ7H||+Spg53jl9^2kZa<

delta 27
dcmZpOX^5F1!)9b^U}$VKQ7H||+Spg53jl3|2f_dV

diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imf-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64imf-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64imf-unknown-none-elf-smode.a
index 026428372643beaadb80e7fe8b73ee39b7be3a86..264d2d83a3a8da79d2d3acee4dc4d84dac58a802 100644
GIT binary patch
delta 27
dcmewm^C4z}44bi;rLmdCM5Qz+Yh&LdT>ytN2|fS-

delta 27
dcmewm^C4z}44aXufuXVSM5Qz+Yh&LdT>ynR2^0VT

diff --git a/riscv-rt/bin/riscv64imf-unknown-none-elf.a b/riscv-rt/bin/riscv64imf-unknown-none-elf.a
index 3667454a41222a8ced98b460b52b61a1015e6bbe..e90f1b95f15a151381635fccce09da33a48dc166 100644
GIT binary patch
delta 27
dcmewm^C4z}44bi;rLmdCM5Qz+Yh&LdT>ytN2|fS-

delta 27
dcmewm^C4z}44aXufuXVSM5Qz+Yh&LdT>ynR2^0VT

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64imfc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64imfc-unknown-none-elf-smode.a
index c9dc0813d6a8e3e706f89d68fdd901a6ba141e21..fad4683e8217fe605cdb0a5429af9603bbd5be88 100644
GIT binary patch
delta 27
dcmeB(>4=#i!)9z|X>4XOQ7H||+Spg63jlFK2nGNE

delta 27
dcmeB(>4=#i!)9b^U}$VSQ7H||+Spg63jl9O2iyPv

diff --git a/riscv-rt/bin/riscv64imfc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfc-unknown-none-elf.a
index 2976e285a0985a49d6dd471882a1a88b8fc14f09..6ad9e5958a40712072e25b4d1c214adbcb74423a 100644
GIT binary patch
delta 27
dcmeB(>4=#i!)9z|X>4XOQ7H||+Spg63jlFK2nGNE

delta 27
dcmeB(>4=#i!)9b^U}$VSQ7H||+Spg63jl9O2iyPv

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64imfd-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64imfd-unknown-none-elf-smode.a
index e5b2922c46327ff74662c753444a1c310df0a993..083f18f1877ee4e74740a0c3a6cc2ae083084374 100644
GIT binary patch
delta 27
dcmewn^CM=044bi;rLmdCM5Qz+Yh&LlT>yyU3043A

delta 27
dcmewn^CM=044aXufuXVSM5Qz+Yh&LlT>ysY2`m5r

diff --git a/riscv-rt/bin/riscv64imfd-unknown-none-elf.a b/riscv-rt/bin/riscv64imfd-unknown-none-elf.a
index 8a70b49567cb1d013a5bff045e34298307eebb7b..80f2c2149edd7081a4225bb8a7cc7685943d7219 100644
GIT binary patch
delta 27
dcmewn^CM=044bi;rLmdCM5Qz+Yh&LlT>yyU3043A

delta 27
dcmewn^CM=044aXufuXVSM5Qz+Yh&LlT>ysY2`m5r

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf-sbi.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf-smode.a
similarity index 99%
rename from riscv-rt/bin/riscv64imfdc-unknown-none-elf-sbi.a
rename to riscv-rt/bin/riscv64imfdc-unknown-none-elf-smode.a
index 6040a04e94c2239d0904e98ab9ed6c33e2585867..59eaff9f9f4336d9aeca33cdde1d66e17a102b21 100644
GIT binary patch
delta 27
ccmbObGa+Vz44bi;B@j(iN`taC_BH7O0CNTiAOHXW

delta 27
dcmbObGa+Vz44aXufuXU<M5Qz+Yhz!NE&y>12lfB}

diff --git a/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a b/riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
index 2fc054c389bb3b39ecdb43245a987970f40b6519..7e4aa4a9890618f19c412e350726daa6a8082775 100644
GIT binary patch
delta 27
ccmbObGa+Vz44bi;B@j(iN`taC_BH7O0CNTiAOHXW

delta 27
dcmbObGa+Vz44aXufuXVSM5Qz+Yhz!NE&y=&2lM~{


From 68e99b335261f611606f94c46dc7a7438f827af9 Mon Sep 17 00:00:00 2001
From: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>
Date: Tue, 20 Sep 2022 00:24:03 +0200
Subject: [PATCH 188/234] SMODE: remove redundand paths

---
 riscv-rt/src/lib.rs | 44 +++++++++++++++-----------------------------
 1 file changed, 15 insertions(+), 29 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index ce19c668..3027452c 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -359,7 +359,12 @@
 #![no_std]
 #![deny(missing_docs)]
 
-use riscv::register::{mcause, mhartid, scause};
+#[cfg(feature = "s-mode")]
+use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};
+
+#[cfg(not(feature = "s-mode"))]
+use riscv::register::{mcause as xcause, mhartid, mtvec as xtvec, mtvec::TrapMode as xTrapMode};
+
 pub use riscv_rt_macros::{entry, pre_init};
 
 #[export_name = "error: riscv-rt appears more than once in the dependency graph"]
@@ -400,12 +405,10 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
     }
 
     // sbi passes hartid as first parameter (a0)
-    let hartid: usize;
-    if cfg!(feature = "s-mode") {
-        hartid = a0;
-    } else {
-        hartid = mhartid::read();
-    }
+    #[cfg(feature = "s-mode")]
+    let hartid = a0;
+    #[cfg(not(feature = "s-mode"))]
+    let hartid = mhartid::read();
 
     if _mp_hook(hartid) {
         __pre_init();
@@ -458,24 +461,13 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     }
 
     unsafe {
-        let code: usize;
-        let is_exception: bool;
+        let cause = xcause::read();
 
-        if cfg!(feature = "s-mode") {
-            let cause = scause::read();
-            is_exception = cause.is_exception();
-            code = cause.code();
-        } else {
-            let cause = mcause::read();
-            is_exception = cause.is_exception();
-            code = cause.code();
-        }
-
-        if is_exception {
+        if cause.is_exception() {
             ExceptionHandler(&*trap_frame)
         } else {
-            if code < __INTERRUPTS.len() {
-                let h = &__INTERRUPTS[code];
+            if cause.code() < __INTERRUPTS.len() {
+                let h = &__INTERRUPTS[cause.code()];
                 if h.reserved == 0 {
                     DefaultHandler();
                 } else {
@@ -601,11 +593,5 @@ pub unsafe extern "Rust" fn default_setup_interrupts() {
         fn _start_trap();
     }
 
-    if cfg!(feature = "s-mode") {
-        use riscv::register::stvec::{self, TrapMode};
-        stvec::write(_start_trap as usize, TrapMode::Direct);
-    } else {
-        use riscv::register::mtvec::{self, TrapMode};
-        mtvec::write(_start_trap as usize, TrapMode::Direct);        
-    }
+    xtvec::write(_start_trap as usize, xTrapMode::Direct);
 }

From edf0387398497f0fe7545aef3c875ce1f20427ae Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Fri, 4 Nov 2022 20:00:21 -0700
Subject: [PATCH 189/234] release v0.10.0

---
 riscv-rt/CHANGELOG.md | 6 +++++-
 riscv-rt/Cargo.toml   | 4 ++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 251205d6..5ab83981 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.10.0] - 2022-11-04
+
 ### Added
 
 - Optional cargo feature `s-mode` for supervisor mode, including conditional compilation for supervisor/machine mode instructions.
@@ -15,6 +17,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Remove superfluous parentheses from link.x, which caused linker errors with nightly.
 - Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `s-mode` feature).
+- Update `riscv` to version 0.9
 
 ## [v0.9.0] - 2022-07-01
 
@@ -91,7 +94,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.0..HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0..HEAD
+[v0.10.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.1...v0.10.0
 [v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0
 [v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
 [v0.8.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...v0.8.0
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 31f74450..c0f76cb3 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.9.0"
+version = "0.10.0"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
@@ -15,7 +15,7 @@ s-mode = []
 
 [dependencies]
 r0 = "1.0.0"
-riscv = "0.8"
+riscv = "0.9"
 riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]

From d66bf9fe7ee91667cf0850c6d291ab8e60150dd9 Mon Sep 17 00:00:00 2001
From: tfx2001 <tfx2001@outlook.com>
Date: Sat, 24 Dec 2022 09:58:16 +0000
Subject: [PATCH 190/234] update to riscv 0.10

---
 riscv-rt/CHANGELOG.md | 4 ++++
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 5ab83981..102e8ed2 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update `riscv` to version 0.10
+
 ## [v0.10.0] - 2022-11-04
 
 ### Added
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index c0f76cb3..31cb8ef3 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -15,7 +15,7 @@ s-mode = []
 
 [dependencies]
 r0 = "1.0.0"
-riscv = "0.9"
+riscv = "0.10"
 riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]

From bb86d3485fd009be3359b9f2a31531476a1032bf Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Wed, 18 Jan 2023 11:39:13 -0800
Subject: [PATCH 191/234] release v0.10.1 with riscv CS fix

---
 riscv-rt/CHANGELOG.md | 7 +++++--
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 102e8ed2..af563848 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,9 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.10.1] - 2023-01-18
+
 ### Changed
 
-- Update `riscv` to version 0.10
+- Update `riscv` to version 0.10.1 fixing a critical section bug
 
 ## [v0.10.0] - 2022-11-04
 
@@ -98,7 +100,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0..HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.1..HEAD
+[v0.10.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0...v0.10.1
 [v0.10.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.1...v0.10.0
 [v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0
 [v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 31cb8ef3..497ee4e2 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.10.0"
+version = "0.10.1"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]

From fcc69ab4909c298708bb339c40e0cbf91fa7b345 Mon Sep 17 00:00:00 2001
From: Ales Katona <ales@katona.me>
Date: Wed, 18 Jan 2023 12:11:38 -0800
Subject: [PATCH 192/234] use v0.11.0 due to major dependency bump

---
 riscv-rt/CHANGELOG.md | 6 +++---
 riscv-rt/Cargo.toml   | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index af563848..95f4e334 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,7 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-## [v0.10.1] - 2023-01-18
+## [v0.11.0] - 2023-01-18
 
 ### Changed
 
@@ -100,8 +100,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.1..HEAD
-[v0.10.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0...v0.10.1
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.11.0..HEAD
+[v0.10.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0...v0.11.0
 [v0.10.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.1...v0.10.0
 [v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0
 [v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 497ee4e2..5fc45ccf 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.10.1"
+version = "0.11.0"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]

From 527ed05eaef818187242e9213088baf5cde10b6e Mon Sep 17 00:00:00 2001
From: sethp <seth@codecopse.net>
Date: Sat, 21 Jan 2023 09:47:24 -0800
Subject: [PATCH 193/234] fix: avoid rust-analyzer snake case warning

It seems that rust-analyzer needs to operate over the expanded text of the proc macro (in order to e.g. support completion in the function body, see #11014 for way more details), so it "sees" the non-snake-case name emitted by riscv-rt's `entry` here.

Without this change, rust-analyzer will show a "weak warning" on invocations of `#[entry]` with the text:

```
Function `__risc_v_rt__main` should have snake_case name, e.g. `__risc_v_rt_main`
```
---
 riscv-rt/macros/src/lib.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/macros/src/lib.rs b/riscv-rt/macros/src/lib.rs
index 3c79864b..f63d8ceb 100644
--- a/riscv-rt/macros/src/lib.rs
+++ b/riscv-rt/macros/src/lib.rs
@@ -109,6 +109,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let stmts = f.block.stmts;
 
     quote!(
+        #[allow(non_snake_case)]
         #[export_name = "main"]
         #(#attrs)*
         pub #unsafety fn __risc_v_rt__main(#args) -> ! {

From a47997756eb6ab99d0aab4247da5dd51cc77ba42 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 4 Jul 2023 16:16:36 +0200
Subject: [PATCH 194/234] moving to ghmq

---
 riscv-rt/.github/bors.toml              |  8 -----
 riscv-rt/.github/workflows/blobs.yaml   | 17 ++++++++++
 riscv-rt/.github/workflows/build.yaml   | 45 +++++++++++++++++++++++++
 riscv-rt/.github/workflows/ci.yaml      | 40 ----------------------
 riscv-rt/.github/workflows/rustfmt.yaml | 21 +++++-------
 5 files changed, 70 insertions(+), 61 deletions(-)
 delete mode 100644 riscv-rt/.github/bors.toml
 create mode 100644 riscv-rt/.github/workflows/blobs.yaml
 create mode 100644 riscv-rt/.github/workflows/build.yaml
 delete mode 100644 riscv-rt/.github/workflows/ci.yaml

diff --git a/riscv-rt/.github/bors.toml b/riscv-rt/.github/bors.toml
deleted file mode 100644
index b50b7c62..00000000
--- a/riscv-rt/.github/bors.toml
+++ /dev/null
@@ -1,8 +0,0 @@
-block_labels = ["needs-decision"]
-delete_merged_branches = true
-required_approvals = 1
-status = [
-    "ci-linux (stable)",
-    "ci-linux (1.59.0)",
-    "Rustfmt"
-]
diff --git a/riscv-rt/.github/workflows/blobs.yaml b/riscv-rt/.github/workflows/blobs.yaml
new file mode 100644
index 00000000..b0b6b640
--- /dev/null
+++ b/riscv-rt/.github/workflows/blobs.yaml
@@ -0,0 +1,17 @@
+on:
+  push:
+    branches: [ master, ghmq ]
+  pull_request:
+  merge_group:
+
+name: Check blobs
+
+jobs:
+  blobs:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - name: Install riscv gcc
+        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
+      - name: Check blobs
+        run: ./check-blobs.sh
diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
new file mode 100644
index 00000000..da7c7154
--- /dev/null
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -0,0 +1,45 @@
+on:
+  push:
+    branches: [ master, ghmq ]
+  pull_request:
+  merge_group:
+
+name: Build check
+
+jobs:
+  build-riscv:
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.59.0
+        toolchain: [ stable, nightly, 1.59.0 ]
+        target:
+          - riscv32i-unknown-none-elf
+          - riscv32imc-unknown-none-elf
+          - riscv32imac-unknown-none-elf
+          - riscv64imac-unknown-none-elf
+          - riscv64gc-unknown-none-elf
+        cargo_flags: [ "--no-default-features", "--all-features" ]
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+      - uses: actions/checkout@v3
+      - uses: dtolnay/rust-toolchain@master
+        with:
+          toolchain: ${{ matrix.toolchain }}
+          targets: ${{ matrix.target }}
+      - name: Build library
+        run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
+  
+  # Job to check that all the builds succeeded
+  build-check:
+    needs:
+    - build-riscv
+    runs-on: ubuntu-latest
+    if: always()
+    steps:
+      - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
+  
\ No newline at end of file
diff --git a/riscv-rt/.github/workflows/ci.yaml b/riscv-rt/.github/workflows/ci.yaml
deleted file mode 100644
index 94d99f49..00000000
--- a/riscv-rt/.github/workflows/ci.yaml
+++ /dev/null
@@ -1,40 +0,0 @@
-on:
-  push:
-    branches: [ staging, trying, master ]
-  pull_request:
-
-name: Continuous integration
-
-jobs:
-  ci-linux:
-    runs-on: ubuntu-20.04
-    continue-on-error: ${{ matrix.experimental || false }}
-    strategy:
-      matrix:
-        # All generated code should be running on stable now, MSRV is 1.59.0
-        rust: [nightly, stable, 1.59.0]
-
-        include:
-          # Nightly is only for reference and allowed to fail
-          - rust: nightly
-            experimental: true
-
-    steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
-        with:
-          profile: minimal
-          toolchain: ${{ matrix.rust }}
-          override: true
-      - name: Install all Rust targets for ${{ matrix.rust }}
-        run: rustup target install --toolchain=${{ matrix.rust }} riscv32imac-unknown-none-elf riscv64imac-unknown-none-elf riscv64gc-unknown-none-elf
-      - name: Install riscv gcc
-        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
-      - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
-        run: cargo check --target riscv32imac-unknown-none-elf
-      - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
-        run: cargo check --target riscv64imac-unknown-none-elf
-      - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
-        run: cargo check --target riscv64gc-unknown-none-elf
-      - name: Check blobs
-        run: ./check-blobs.sh
diff --git a/riscv-rt/.github/workflows/rustfmt.yaml b/riscv-rt/.github/workflows/rustfmt.yaml
index 07273842..79854611 100644
--- a/riscv-rt/.github/workflows/rustfmt.yaml
+++ b/riscv-rt/.github/workflows/rustfmt.yaml
@@ -1,24 +1,19 @@
 
 on:
   push:
-    branches: [ staging, trying, master ]
+    branches: [ master, ghmq ]
   pull_request:
+  merge_group:
 
 name: Code formatting check
 
 jobs:
-  fmt:
-    name: Rustfmt
-    runs-on: ubuntu-20.04
+  rustfmt:
+    runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v2
-      - uses: actions-rs/toolchain@v1
+      - uses: actions/checkout@v3
+      - uses: dtolnay/rust-toolchain@stable
         with:
-          profile: minimal
-          toolchain: stable
-          override: true
           components: rustfmt
-      - uses: actions-rs/cargo@v1
-        with:
-          command: fmt
-          args: --all -- --check
\ No newline at end of file
+      - name: Run Rustfmt
+        run: cargo fmt --all -- --check --verbose

From 86d70ab7df5d95919b5578833218f103b1f8805f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 4 Jul 2023 16:25:01 +0200
Subject: [PATCH 195/234] ready to merge

---
 riscv-rt/.github/workflows/blobs.yaml   | 2 +-
 riscv-rt/.github/workflows/build.yaml   | 2 +-
 riscv-rt/.github/workflows/rustfmt.yaml | 2 +-
 riscv-rt/CHANGELOG.md                   | 4 ++++
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/.github/workflows/blobs.yaml b/riscv-rt/.github/workflows/blobs.yaml
index b0b6b640..0c9bea51 100644
--- a/riscv-rt/.github/workflows/blobs.yaml
+++ b/riscv-rt/.github/workflows/blobs.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, ghmq ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
index da7c7154..71333df4 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, ghmq ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
diff --git a/riscv-rt/.github/workflows/rustfmt.yaml b/riscv-rt/.github/workflows/rustfmt.yaml
index 79854611..72993e73 100644
--- a/riscv-rt/.github/workflows/rustfmt.yaml
+++ b/riscv-rt/.github/workflows/rustfmt.yaml
@@ -1,7 +1,7 @@
 
 on:
   push:
-    branches: [ master, ghmq ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 95f4e334..50b44407 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Removed bors in favor of GitHub Merge Queue
+
 ## [v0.11.0] - 2023-01-18
 
 ### Changed

From 0abe2ab583aa37d14eeb503c95bdf26dd0d34066 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Thu, 6 Jul 2023 11:00:04 +0200
Subject: [PATCH 196/234] use core::arch::global_asm

---
 riscv-rt/{asm.S => asm/original_asm.S}        |   0
 riscv-rt/asm/riscv32i-unknown-none-elf-m.s    | 123 ++++++++++++
 riscv-rt/asm/riscv32i-unknown-none-elf-s.s    | 123 ++++++++++++
 riscv-rt/asm/riscv32imac-unknown-none-elf-m.s | 116 +++++++++++
 riscv-rt/asm/riscv32imac-unknown-none-elf-s.s | 116 +++++++++++
 riscv-rt/asm/riscv64imac-unknown-none-elf-m.s | 126 ++++++++++++
 riscv-rt/asm/riscv64imac-unknown-none-elf-s.s | 126 ++++++++++++
 riscv-rt/assemble.ps1                         |  27 ---
 riscv-rt/assemble.sh                          |  44 -----
 .../bin/riscv32i-unknown-none-elf-smode.a     | Bin 7732 -> 0 bytes
 riscv-rt/bin/riscv32i-unknown-none-elf.a      | Bin 7732 -> 0 bytes
 .../bin/riscv32ic-unknown-none-elf-smode.a    | Bin 7600 -> 0 bytes
 riscv-rt/bin/riscv32ic-unknown-none-elf.a     | Bin 7608 -> 0 bytes
 .../bin/riscv32if-unknown-none-elf-smode.a    | Bin 7736 -> 0 bytes
 riscv-rt/bin/riscv32if-unknown-none-elf.a     | Bin 7736 -> 0 bytes
 .../bin/riscv32ifc-unknown-none-elf-smode.a   | Bin 7604 -> 0 bytes
 riscv-rt/bin/riscv32ifc-unknown-none-elf.a    | Bin 7612 -> 0 bytes
 .../bin/riscv32ifd-unknown-none-elf-smode.a   | Bin 7740 -> 0 bytes
 riscv-rt/bin/riscv32ifd-unknown-none-elf.a    | Bin 7740 -> 0 bytes
 .../bin/riscv32ifdc-unknown-none-elf-smode.a  | Bin 7612 -> 0 bytes
 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a   | Bin 7620 -> 0 bytes
 .../bin/riscv32im-unknown-none-elf-smode.a    | Bin 7420 -> 0 bytes
 riscv-rt/bin/riscv32im-unknown-none-elf.a     | Bin 7420 -> 0 bytes
 .../bin/riscv32imc-unknown-none-elf-smode.a   | Bin 7296 -> 0 bytes
 riscv-rt/bin/riscv32imc-unknown-none-elf.a    | Bin 7296 -> 0 bytes
 .../bin/riscv32imf-unknown-none-elf-smode.a   | Bin 7424 -> 0 bytes
 riscv-rt/bin/riscv32imf-unknown-none-elf.a    | Bin 7424 -> 0 bytes
 .../bin/riscv32imfc-unknown-none-elf-smode.a  | Bin 7304 -> 0 bytes
 riscv-rt/bin/riscv32imfc-unknown-none-elf.a   | Bin 7304 -> 0 bytes
 .../bin/riscv32imfd-unknown-none-elf-smode.a  | Bin 7432 -> 0 bytes
 riscv-rt/bin/riscv32imfd-unknown-none-elf.a   | Bin 7432 -> 0 bytes
 .../bin/riscv32imfdc-unknown-none-elf-smode.a | Bin 7308 -> 0 bytes
 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a  | Bin 7308 -> 0 bytes
 .../bin/riscv64i-unknown-none-elf-smode.a     | Bin 12400 -> 0 bytes
 riscv-rt/bin/riscv64i-unknown-none-elf.a      | Bin 12400 -> 0 bytes
 .../bin/riscv64ic-unknown-none-elf-smode.a    | Bin 12280 -> 0 bytes
 riscv-rt/bin/riscv64ic-unknown-none-elf.a     | Bin 12280 -> 0 bytes
 .../bin/riscv64if-unknown-none-elf-smode.a    | Bin 12408 -> 0 bytes
 riscv-rt/bin/riscv64if-unknown-none-elf.a     | Bin 12408 -> 0 bytes
 .../bin/riscv64ifc-unknown-none-elf-smode.a   | Bin 12280 -> 0 bytes
 riscv-rt/bin/riscv64ifc-unknown-none-elf.a    | Bin 12280 -> 0 bytes
 .../bin/riscv64ifd-unknown-none-elf-smode.a   | Bin 12408 -> 0 bytes
 riscv-rt/bin/riscv64ifd-unknown-none-elf.a    | Bin 12408 -> 0 bytes
 .../bin/riscv64ifdc-unknown-none-elf-smode.a  | Bin 12288 -> 0 bytes
 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a   | Bin 12288 -> 0 bytes
 .../bin/riscv64im-unknown-none-elf-smode.a    | Bin 11888 -> 0 bytes
 riscv-rt/bin/riscv64im-unknown-none-elf.a     | Bin 11888 -> 0 bytes
 .../bin/riscv64imc-unknown-none-elf-smode.a   | Bin 11776 -> 0 bytes
 riscv-rt/bin/riscv64imc-unknown-none-elf.a    | Bin 11776 -> 0 bytes
 .../bin/riscv64imf-unknown-none-elf-smode.a   | Bin 11888 -> 0 bytes
 riscv-rt/bin/riscv64imf-unknown-none-elf.a    | Bin 11888 -> 0 bytes
 .../bin/riscv64imfc-unknown-none-elf-smode.a  | Bin 11784 -> 0 bytes
 riscv-rt/bin/riscv64imfc-unknown-none-elf.a   | Bin 11784 -> 0 bytes
 .../bin/riscv64imfd-unknown-none-elf-smode.a  | Bin 11896 -> 0 bytes
 riscv-rt/bin/riscv64imfd-unknown-none-elf.a   | Bin 11896 -> 0 bytes
 .../bin/riscv64imfdc-unknown-none-elf-smode.a | Bin 11792 -> 0 bytes
 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a  | Bin 11792 -> 0 bytes
 riscv-rt/build.rs                             |  29 +--
 riscv-rt/check-blobs.sh                       |  20 +-
 riscv-rt/examples/device.x                    |  14 ++
 riscv-rt/src/asm.rs                           | 186 ++++++++++++++++++
 riscv-rt/src/lib.rs                           |   3 +
 62 files changed, 949 insertions(+), 104 deletions(-)
 rename riscv-rt/{asm.S => asm/original_asm.S} (100%)
 create mode 100644 riscv-rt/asm/riscv32i-unknown-none-elf-m.s
 create mode 100644 riscv-rt/asm/riscv32i-unknown-none-elf-s.s
 create mode 100644 riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
 create mode 100644 riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
 create mode 100644 riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
 create mode 100644 riscv-rt/asm/riscv64imac-unknown-none-elf-s.s
 delete mode 100644 riscv-rt/assemble.ps1
 delete mode 100755 riscv-rt/assemble.sh
 delete mode 100644 riscv-rt/bin/riscv32i-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32i-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32ic-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32ic-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32if-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32if-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32ifc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32ifc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32ifd-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32ifd-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32ifdc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32im-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32im-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32imc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imf-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32imf-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imfc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32imfc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imfd-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32imfd-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv32imfdc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64i-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64i-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64ic-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64ic-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64if-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64if-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64ifc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64ifc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64ifd-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64ifd-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64ifdc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64im-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64im-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64imc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imf-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64imf-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imfc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64imfc-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imfd-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64imfd-unknown-none-elf.a
 delete mode 100644 riscv-rt/bin/riscv64imfdc-unknown-none-elf-smode.a
 delete mode 100644 riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
 create mode 100644 riscv-rt/examples/device.x
 create mode 100644 riscv-rt/src/asm.rs

diff --git a/riscv-rt/asm.S b/riscv-rt/asm/original_asm.S
similarity index 100%
rename from riscv-rt/asm.S
rename to riscv-rt/asm/original_asm.S
diff --git a/riscv-rt/asm/riscv32i-unknown-none-elf-m.s b/riscv-rt/asm/riscv32i-unknown-none-elf-m.s
new file mode 100644
index 00000000..f501993c
--- /dev/null
+++ b/riscv-rt/asm/riscv32i-unknown-none-elf-m.s
@@ -0,0 +1,123 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0"
+	.file	"zk0t2u2b1an050m"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	beqz	t2, .Ltmp0
+	mv	t1, t2
+	mv	t3, t0
+.Ltmp1:
+	add	t0, t0, t3
+	addi	t1, t1, -1
+	bnez	t1, .Ltmp1
+.Ltmp0:
+	sub	sp, sp, t0
+	add	s0, sp, zero
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/asm/riscv32i-unknown-none-elf-s.s b/riscv-rt/asm/riscv32i-unknown-none-elf-s.s
new file mode 100644
index 00000000..52b84f70
--- /dev/null
+++ b/riscv-rt/asm/riscv32i-unknown-none-elf-s.s
@@ -0,0 +1,123 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0"
+	.file	"eaqpawb8fun9h0d"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	beqz	t2, .Ltmp0
+	mv	t1, t2
+	mv	t3, t0
+.Ltmp1:
+	add	t0, t0, t3
+	addi	t1, t1, -1
+	bnez	t1, .Ltmp1
+.Ltmp0:
+	sub	sp, sp, t0
+	add	s0, sp, zero
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s b/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
new file mode 100644
index 00000000..eee62b9f
--- /dev/null
+++ b/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
@@ -0,0 +1,116 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
+	.file	"3wdx7lxc78dgym21"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s b/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
new file mode 100644
index 00000000..32d504a9
--- /dev/null
+++ b/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
@@ -0,0 +1,116 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
+	.file	"2mpkjzuft8hmeuib"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	lui	ra, %hi(_abs_start)
+	jalr	zero, %lo(_abs_start)(ra)
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -64
+	sw	ra, 0(sp)
+	sw	t0, 4(sp)
+	sw	t1, 8(sp)
+	sw	t2, 12(sp)
+	sw	t3, 16(sp)
+	sw	t4, 20(sp)
+	sw	t5, 24(sp)
+	sw	t6, 28(sp)
+	sw	a0, 32(sp)
+	sw	a1, 36(sp)
+	sw	a2, 40(sp)
+	sw	a3, 44(sp)
+	sw	a4, 48(sp)
+	sw	a5, 52(sp)
+	sw	a6, 56(sp)
+	sw	a7, 60(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	lw	ra, 0(sp)
+	lw	t0, 4(sp)
+	lw	t1, 8(sp)
+	lw	t2, 12(sp)
+	lw	t3, 16(sp)
+	lw	t4, 20(sp)
+	lw	t5, 24(sp)
+	lw	t6, 28(sp)
+	lw	a0, 32(sp)
+	lw	a1, 36(sp)
+	lw	a2, 40(sp)
+	lw	a3, 44(sp)
+	lw	a4, 48(sp)
+	lw	a5, 52(sp)
+	lw	a6, 56(sp)
+	lw	a7, 60(sp)
+	addi	sp, sp, 64
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s b/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
new file mode 100644
index 00000000..3d57d129
--- /dev/null
+++ b/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
@@ -0,0 +1,126 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
+	.file	"1ruuache5c4x1fns"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	.option	push
+
+	.option	norelax
+.Ltmp0:
+	auipc	ra, %pcrel_hi(.Ltmp1)
+	ld	ra, %pcrel_lo(.Ltmp0)(ra)
+	ret
+	.p2align	3
+.Ltmp1:
+	.quad	_abs_start
+	.option	pop
+
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	mie, 0
+	csrwi	mip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	csrr	t2, mhartid
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -128
+	sd	ra, 0(sp)
+	sd	t0, 8(sp)
+	sd	t1, 16(sp)
+	sd	t2, 24(sp)
+	sd	t3, 32(sp)
+	sd	t4, 40(sp)
+	sd	t5, 48(sp)
+	sd	t6, 56(sp)
+	sd	a0, 64(sp)
+	sd	a1, 72(sp)
+	sd	a2, 80(sp)
+	sd	a3, 88(sp)
+	sd	a4, 96(sp)
+	sd	a5, 104(sp)
+	sd	a6, 112(sp)
+	sd	a7, 120(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	ld	ra, 0(sp)
+	ld	t0, 8(sp)
+	ld	t1, 16(sp)
+	ld	t2, 24(sp)
+	ld	t3, 32(sp)
+	ld	t4, 40(sp)
+	ld	t5, 48(sp)
+	ld	t6, 56(sp)
+	ld	a0, 64(sp)
+	ld	a1, 72(sp)
+	ld	a2, 80(sp)
+	ld	a3, 88(sp)
+	ld	a4, 96(sp)
+	ld	a5, 104(sp)
+	ld	a6, 112(sp)
+	ld	a7, 120(sp)
+	addi	sp, sp, 128
+	mret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s b/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s
new file mode 100644
index 00000000..5626f5d5
--- /dev/null
+++ b/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s
@@ -0,0 +1,126 @@
+	.text
+	.attribute	4, 16
+	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
+	.file	"5194e8m2dkkkh98p"
+
+	.section	.init,"ax",@progbits
+	.globl	_start
+
+_start:
+
+	.option	push
+
+	.option	norelax
+.Ltmp0:
+	auipc	ra, %pcrel_hi(.Ltmp1)
+	ld	ra, %pcrel_lo(.Ltmp0)(ra)
+	ret
+	.p2align	3
+.Ltmp1:
+	.quad	_abs_start
+	.option	pop
+
+
+_abs_start:
+	.cfi_startproc
+	.cfi_undefined ra
+	csrwi	sie, 0
+	csrwi	sip, 0
+	li	ra, 0
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+
+	.option	push
+
+	.option	norelax
+
+.Lpcrel_hi0:
+	auipc	gp, %pcrel_hi(__global_pointer$)
+	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
+	.option	pop
+
+	mv	t2, a0
+	lui	t0, %hi(_max_hart_id)
+	addi	t0, t0, %lo(_max_hart_id)
+	bltu	t0, t2, abort
+
+.Lpcrel_hi1:
+	auipc	sp, %pcrel_hi(_stack_start)
+	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
+	lui	t0, %hi(_hart_stack_size)
+	addi	t0, t0, %lo(_hart_stack_size)
+	mul	t0, t2, t0
+	sub	sp, sp, t0
+	mv	s0, sp
+	j	_start_rust
+
+	.cfi_endproc
+	.section	.trap,"ax",@progbits
+	.globl	default_start_trap
+default_start_trap:
+	addi	sp, sp, -128
+	sd	ra, 0(sp)
+	sd	t0, 8(sp)
+	sd	t1, 16(sp)
+	sd	t2, 24(sp)
+	sd	t3, 32(sp)
+	sd	t4, 40(sp)
+	sd	t5, 48(sp)
+	sd	t6, 56(sp)
+	sd	a0, 64(sp)
+	sd	a1, 72(sp)
+	sd	a2, 80(sp)
+	sd	a3, 88(sp)
+	sd	a4, 96(sp)
+	sd	a5, 104(sp)
+	sd	a6, 112(sp)
+	sd	a7, 120(sp)
+	mv	a0, sp
+	jal	_start_trap_rust
+	ld	ra, 0(sp)
+	ld	t0, 8(sp)
+	ld	t1, 16(sp)
+	ld	t2, 24(sp)
+	ld	t3, 32(sp)
+	ld	t4, 40(sp)
+	ld	t5, 48(sp)
+	ld	t6, 56(sp)
+	ld	a0, 64(sp)
+	ld	a1, 72(sp)
+	ld	a2, 80(sp)
+	ld	a3, 88(sp)
+	ld	a4, 96(sp)
+	ld	a5, 104(sp)
+	ld	a6, 112(sp)
+	ld	a7, 120(sp)
+	addi	sp, sp, 128
+	sret	
+	.section	.text.abort,"ax",@progbits
+	.globl	abort
+abort:
+	j	abort
diff --git a/riscv-rt/assemble.ps1 b/riscv-rt/assemble.ps1
deleted file mode 100644
index c5e67f67..00000000
--- a/riscv-rt/assemble.ps1
+++ /dev/null
@@ -1,27 +0,0 @@
-New-Item -Force -Name bin -Type Directory
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-Remove-Item -Force bin/*.a
-
-$crate = "riscv-rt"
-
-$extension_sets = @("i", "im", "ic", "imc", "if", "ifc", "imf", "imfc", "ifd", "ifdc", "imfd", "imfdc")
-
-$pwd = Get-Location
-
-foreach ($ext in $extension_sets)
-{
-    $abi = ""
-    if ($ext.contains("d"))
-        {$abi = "d"}
-    elseif ($ext.contains("f"))
-        {$abi = "f"}
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=ilp32$abi" "-march=rv32$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32$ext-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$pwd=/riscv-rt -c "-mabi=lp64$abi" "-march=rv64$ext" asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64$ext-unknown-none-elf.a bin/$crate.o
-}
-
-Remove-Item bin/$crate.o
diff --git a/riscv-rt/assemble.sh b/riscv-rt/assemble.sh
deleted file mode 100755
index 296a6dd6..00000000
--- a/riscv-rt/assemble.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/bash
-
-set -euxo pipefail
-
-crate=riscv-rt
-
-# remove existing blobs because otherwise this will append object files to the old blobs
-rm -f bin/*.a
-
-exts=('i' 'ic' 'im' 'imc' 'if' 'ifc' 'imf' 'imfc' 'ifd' 'ifdc' 'imfd' 'imfdc')
-
-for ext in ${exts[@]}
-do
-    case $ext in
-
-        *'d'*)
-            abi='d'
-            ;;
-        
-        *'f'*)
-            abi='f'
-            ;;
-        
-        *)
-            abi=''
-            ;;
-    esac
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
-
-    #s-mode
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
-    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
-
-done
-
-rm bin/$crate.o
diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf-smode.a b/riscv-rt/bin/riscv32i-unknown-none-elf-smode.a
deleted file mode 100644
index 40260c7fc3d68672f89ecec834fe1b7440fde578..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/riscv-rt/bin/riscv32i-unknown-none-elf.a b/riscv-rt/bin/riscv32i-unknown-none-elf.a
deleted file mode 100644
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GIT binary patch
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diff --git a/riscv-rt/bin/riscv32ic-unknown-none-elf-smode.a b/riscv-rt/bin/riscv32ic-unknown-none-elf-smode.a
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GIT binary patch
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HcmV?d00001

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diff --git a/riscv-rt/bin/riscv32ifd-unknown-none-elf.a b/riscv-rt/bin/riscv32ifd-unknown-none-elf.a
deleted file mode 100644
index 549caacd5d4aecaf8f622ecdc86e56350a59a2d8..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 7740
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diff --git a/riscv-rt/bin/riscv32ifdc-unknown-none-elf-smode.a b/riscv-rt/bin/riscv32ifdc-unknown-none-elf-smode.a
deleted file mode 100644
index 9729b5adcb77478b99787577c4b3fe2637bbd905..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index aa987ad4..23177c28 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,5 +1,4 @@
 // NOTE: Adapted from cortex-m/build.rs
-extern crate riscv_target;
 
 use riscv_target::Target;
 use std::env;
@@ -9,22 +8,24 @@ use std::path::PathBuf;
 fn main() {
     let target = env::var("TARGET").unwrap();
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
-    let name = env::var("CARGO_PKG_NAME").unwrap();
+    let _name = env::var("CARGO_PKG_NAME").unwrap();
 
+    // set configuration flags depending on the target
     if target.starts_with("riscv") {
-        let mut target = Target::from_target_str(&target);
-        target.retain_extensions("imfdc");
-        let archive: String;
-        if cfg!(feature = "s-mode") {
-            println!("======== compiling riscv-rt for s-mode");
-            archive = format!("bin/{}-smode.a", target.to_string());
-        } else {
-            archive = format!("bin/{}.a", target.to_string());
+        println!("cargo:rustc-cfg=riscv");
+        let target = Target::from_target_str(&target);
+        match target.bits {
+            32 => {
+                println!("cargo:rustc-cfg=riscv32");
+            }
+            64 => {
+                println!("cargo:rustc-cfg=riscv64");
+            }
+            _ => panic!("Unsupported bit width"),
+        }
+        if target.has_extension('m') {
+            println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
         }
-
-        fs::copy(&archive, out_dir.join(format!("lib{}.a", name))).unwrap();
-        println!("cargo:rerun-if-changed={}", archive);
-        println!("cargo:rustc-link-lib=static={}", name);
     }
 
     // Put the linker script somewhere the linker can find it
diff --git a/riscv-rt/check-blobs.sh b/riscv-rt/check-blobs.sh
index 36d885e6..471470a1 100755
--- a/riscv-rt/check-blobs.sh
+++ b/riscv-rt/check-blobs.sh
@@ -1,21 +1,3 @@
 #!/bin/bash
 
-# Checks that the blobs are up to date with the committed assembly files
-
-set -euxo pipefail
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
-done
-
-./assemble.sh
-
-for lib in $(ls bin/*.a); do
-    filename=$(basename $lib)
-    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
-done
-
-for cksum in $(ls bin/*.after); do
-    diff -u $cksum ${cksum%.after}.before
-done
+return 0 # not needed anymore
diff --git a/riscv-rt/examples/device.x b/riscv-rt/examples/device.x
new file mode 100644
index 00000000..78e7bac8
--- /dev/null
+++ b/riscv-rt/examples/device.x
@@ -0,0 +1,14 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16K
+    FLASH : ORIGIN = 0x20000000, LENGTH = 4M
+}
+
+REGION_ALIAS("REGION_TEXT", FLASH);
+REGION_ALIAS("REGION_RODATA", FLASH);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+
+INCLUDE link.x
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
new file mode 100644
index 00000000..f4dbf5d8
--- /dev/null
+++ b/riscv-rt/src/asm.rs
@@ -0,0 +1,186 @@
+use core::arch::global_asm;
+
+/// Parse cfg attributes inside a global_asm call.
+macro_rules! cfg_global_asm {
+    {@inner, [$($x:tt)*], } => {
+        global_asm!{$($x)*}
+    };
+    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
+        #[cfg($meta)]
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+        #[cfg(not($meta))]
+        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
+    };
+    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+    };
+    {$($asms:tt)*} => {
+        cfg_global_asm!{@inner, [], $($asms)*}
+    };
+}
+
+// Entry point of all programs (_start). It initializes DWARF call frame information,
+// the stack pointer, the frame pointer (needed for closures to work in start_rust)
+// and the global pointer. Then it calls _start_rust.
+cfg_global_asm!(
+    ".section .init, \"ax\"
+    .global _start
+
+_start:",
+    #[cfg(riscv32)]
+    "lui ra, %hi(_abs_start)
+     jr %lo(_abs_start)(ra)",
+    #[cfg(riscv64)]
+    ".option push
+    .option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
+1:
+    auipc ra, %pcrel_hi(1f)
+    ld ra, %pcrel_lo(1b)(ra)
+    jr ra
+    .align  3
+1:
+    .dword _abs_start
+    .option pop",
+    "
+_abs_start:
+    .option norelax
+    .cfi_startproc
+    .cfi_undefined ra",
+    #[cfg(feature = "s-mode")]
+    "csrw sie, 0
+    csrw sip, 0",
+    #[cfg(not(feature = "s-mode"))]
+    "csrw mie, 0
+    csrw mip, 0",
+    "li  x1, 0
+    li  x2, 0
+    li  x3, 0
+    li  x4, 0
+    li  x5, 0
+    li  x6, 0
+    li  x7, 0
+    li  x8, 0
+    li  x9, 0
+    // a0..a2 (x10..x12) skipped
+    li  x13, 0
+    li  x14, 0
+    li  x15, 0
+    li  x16, 0
+    li  x17, 0
+    li  x18, 0
+    li  x19, 0
+    li  x20, 0
+    li  x21, 0
+    li  x22, 0
+    li  x23, 0
+    li  x24, 0
+    li  x25, 0
+    li  x26, 0
+    li  x27, 0
+    li  x28, 0
+    li  x29, 0
+    li  x30, 0
+    li  x31, 0
+
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop",
+    #[cfg(feature = "s-mode")]
+    "mv t2, a0 // the hartid is passed as parameter by SMODE",
+    #[cfg(not(feature = "s-mode"))]
+    "csrr t2, mhartid",
+    "lui t0, %hi(_max_hart_id)
+    add t0, t0, %lo(_max_hart_id)
+    bgtu t2, t0, abort
+
+    // Allocate stacks
+    la sp, _stack_start
+    lui t0, %hi(_hart_stack_size)
+    add t0, t0, %lo(_hart_stack_size)",
+    #[cfg(riscvm)]
+    "mul t0, t2, t0",
+    #[cfg(not(riscvm))]
+    "beqz t2, 2f  // Jump if single-hart
+    mv t1, t2
+    mv t3, t0
+1:
+    add t0, t0, t3
+    addi t1, t1, -1
+    bnez t1, 1b
+2:  ",
+    "sub sp, sp, t0
+    
+    // Set frame pointer 
+    add s0, sp, zero
+
+    jal zero, _start_rust
+
+    .cfi_endproc",
+);
+
+/// Trap entry point (_start_trap). It saves caller saved registers, calls
+/// _start_trap_rust, restores caller saved registers and then returns.
+/// 
+/// # Usage
+/// 
+/// The macro takes 5 arguments:
+/// - `$STORE`: the instruction used to store a register in the stack (e.g. `sd` for riscv64)
+/// - `$LOAD`: the instruction used to load a register from the stack (e.g. `ld` for riscv64)
+/// - `$BYTES`: the number of bytes used to store a register (e.g. 8 for riscv64)
+/// - `$TRAP_SIZE`: the number of registers to store in the stack (e.g. 32 for all the user registers)
+/// - list of tuples of the form `($REG, $LOCATION)`, where:
+///     - `$REG`: the register to store/load
+///     - `$LOCATION`: the location in the stack where to store/load the register
+#[rustfmt::skip]
+macro_rules! trap_handler {
+    ($STORE:ident, $LOAD:ident, $BYTES:literal, $TRAP_SIZE:literal, [$(($REG:ident, $LOCATION:literal)),*]) => {
+        global_asm!(
+        "
+            .section .trap, \"ax\"
+            .global default_start_trap
+        default_start_trap:",
+            // save space for trap handler in stack
+            concat!("addi sp, sp, -", stringify!($TRAP_SIZE * $BYTES)),
+            // save registers in the desired order
+            $(concat!(stringify!($STORE), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // call rust trap handler
+            "add a0, sp, zero
+            jal ra, _start_trap_rust",
+            // restore registers in the desired order
+            $(concat!(stringify!($LOAD), " ", stringify!($REG), ", ", stringify!($LOCATION * $BYTES), "(sp)"),)*
+            // free stack
+            concat!("addi sp, sp, ", stringify!($TRAP_SIZE * $BYTES)),
+        );
+        cfg_global_asm!(
+            // return from trap
+            #[cfg(feature = "s-mode")]
+            "sret",
+            #[cfg(not(feature = "s-mode"))]
+            "mret",
+        );
+    };
+}
+
+#[rustfmt::skip]
+#[cfg(riscv32)]
+trap_handler!(
+    sw, lw, 4, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+#[rustfmt::skip]
+#[cfg(riscv64)]
+trap_handler!(
+    sd, ld, 8, 16,
+    [(ra, 0), (t0, 1), (t1, 2), (t2, 3), (t3, 4), (t4, 5), (t5, 6), (t6, 7),
+     (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
+);
+
+// Make sure there is an abort when linking
+global_asm!(
+    ".section .text.abort
+     .globl abort
+abort:
+    j abort"
+);
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 3027452c..e0613127 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -359,6 +359,9 @@
 #![no_std]
 #![deny(missing_docs)]
 
+#[cfg(riscv)]
+mod asm;
+
 #[cfg(feature = "s-mode")]
 use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};
 

From 19c30c6ecad11cb45b61a0d0e078bb9a8102f394 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Thu, 6 Jul 2023 11:01:07 +0200
Subject: [PATCH 197/234] add .vscode to .gitignore

---
 riscv-rt/.gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/riscv-rt/.gitignore b/riscv-rt/.gitignore
index e38997ad..7f8712d0 100644
--- a/riscv-rt/.gitignore
+++ b/riscv-rt/.gitignore
@@ -3,3 +3,5 @@ target/
 bin/*.after
 bin/*.before
 bin/*.o
+
+.vscode/
\ No newline at end of file

From 11049a4dba43bd507e7134def559b1c833b700e1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Thu, 6 Jul 2023 11:07:55 +0200
Subject: [PATCH 198/234] modify build CI task

---
 riscv-rt/.github/workflows/blobs.yaml | 17 -----------------
 riscv-rt/.github/workflows/build.yaml |  7 ++++++-
 riscv-rt/check-blobs.sh               |  3 ---
 3 files changed, 6 insertions(+), 21 deletions(-)
 delete mode 100644 riscv-rt/.github/workflows/blobs.yaml
 delete mode 100755 riscv-rt/check-blobs.sh

diff --git a/riscv-rt/.github/workflows/blobs.yaml b/riscv-rt/.github/workflows/blobs.yaml
deleted file mode 100644
index 0c9bea51..00000000
--- a/riscv-rt/.github/workflows/blobs.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-on:
-  push:
-    branches: [ master ]
-  pull_request:
-  merge_group:
-
-name: Check blobs
-
-jobs:
-  blobs:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - name: Install riscv gcc
-        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
-      - name: Check blobs
-        run: ./check-blobs.sh
diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
index 71333df4..5f7e7840 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master ]
+    branches: [ master, global_asm ]
   pull_request:
   merge_group:
 
@@ -18,6 +18,9 @@ jobs:
           - riscv32imac-unknown-none-elf
           - riscv64imac-unknown-none-elf
           - riscv64gc-unknown-none-elf
+        example:
+          - empty
+          - multi_core
         cargo_flags: [ "--no-default-features", "--all-features" ]
         include:
           # Nightly is only for reference and allowed to fail
@@ -33,6 +36,8 @@ jobs:
           targets: ${{ matrix.target }}
       - name: Build library
         run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
+      - name: Build example
+        run: RUSTFLAGS="-C link-arg=-Texamples/device.x" cargo build --target ${{ matrix.target }} --example ${{ matrix.example }} ${{ matrix.cargo_flags }}
   
   # Job to check that all the builds succeeded
   build-check:
diff --git a/riscv-rt/check-blobs.sh b/riscv-rt/check-blobs.sh
deleted file mode 100755
index 471470a1..00000000
--- a/riscv-rt/check-blobs.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-return 0 # not needed anymore

From a94931687fabbcb8be5e97fbd2e99f25d777eb6c Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 15:41:46 +0200
Subject: [PATCH 199/234] testing oor branch

---
 riscv-rt/src/asm.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index f4dbf5d8..4817f6c7 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -92,7 +92,11 @@ _abs_start:
     "csrr t2, mhartid",
     "lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort
+    // bgtu t2, t0, abort
+    bleu t2, t0, not_abort
+    la t0, abort
+    jr t0
+    not_abort:
 
     // Allocate stacks
     la sp, _stack_start

From f823dd9c823e72bb4e8c911cb72aae96a713e733 Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 15:51:24 +0200
Subject: [PATCH 200/234] fix oor branch via linking

---
 riscv-rt/link.x     | 1 +
 riscv-rt/src/asm.rs | 6 +-----
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 1f52024c..fd6f6165 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -55,6 +55,7 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     . = ALIGN(4);
+    *(.abort)
     *(.trap);
     *(.trap.rust);
 
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index 4817f6c7..f4dbf5d8 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -92,11 +92,7 @@ _abs_start:
     "csrr t2, mhartid",
     "lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    // bgtu t2, t0, abort
-    bleu t2, t0, not_abort
-    la t0, abort
-    jr t0
-    not_abort:
+    bgtu t2, t0, abort
 
     // Allocate stacks
     la sp, _stack_start

From 47082d0cbf59bb1dacc61a8438b8de41a1386a38 Mon Sep 17 00:00:00 2001
From: onsdagens <112828711+onsdagens@users.noreply.github.com>
Date: Thu, 6 Jul 2023 15:56:52 +0200
Subject: [PATCH 201/234] run workflow on new branch

---
 riscv-rt/.github/workflows/build.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
index 5f7e7840..4c7bb21d 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, global_asm ]
+    branches: [ master, global_asm, global_asm_link ]
   pull_request:
   merge_group:
 
@@ -47,4 +47,4 @@ jobs:
     if: always()
     steps:
       - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
-  
\ No newline at end of file
+  

From 3358321837780d2ccd8a5c0271e93d5af257a150 Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 16:09:27 +0200
Subject: [PATCH 202/234] fix oor branch via linking

---
 riscv-rt/link.x | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index fd6f6165..31b9d388 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -55,7 +55,7 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     . = ALIGN(4);
-    *(.abort)
+    *(.abort);
     *(.trap);
     *(.trap.rust);
 

From f18290127eecc0ee2f0f177e1cc575847b0f8350 Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 16:14:06 +0200
Subject: [PATCH 203/234] does this even matter

---
 riscv-rt/link.x | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 31b9d388..69fa5a03 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -4,6 +4,8 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
+beep boop xdd
+
 PROVIDE(UserSoft = DefaultHandler);
 PROVIDE(SupervisorSoft = DefaultHandler);
 PROVIDE(MachineSoft = DefaultHandler);

From 3fa3c37fdb5a409e0f131e4d6af8e62ce0391cbd Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 16:29:30 +0200
Subject: [PATCH 204/234] fix oor branch via linking

---
 riscv-rt/link.x | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 69fa5a03..da1caab4 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -4,7 +4,6 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
-beep boop xdd
 
 PROVIDE(UserSoft = DefaultHandler);
 PROVIDE(SupervisorSoft = DefaultHandler);
@@ -57,10 +56,9 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     . = ALIGN(4);
-    *(.abort);
     *(.trap);
     *(.trap.rust);
-
+    *(.text.abort);
     *(.text .text.*);
   } > REGION_TEXT
 

From fc48c008e253aff08295ecd26b83d5099445e25a Mon Sep 17 00:00:00 2001
From: onsdagens <pawdzi-7@student.ltu.se>
Date: Thu, 6 Jul 2023 16:43:41 +0200
Subject: [PATCH 205/234] fix oor branch via linking

---
 riscv-rt/.github/workflows/build.yaml | 3 +--
 riscv-rt/link.x                       | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
index 4c7bb21d..3b532aa2 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, global_asm, global_asm_link ]
+    branches: [ master, global_asm ]
   pull_request:
   merge_group:
 
@@ -47,4 +47,3 @@ jobs:
     if: always()
     steps:
       - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
-  
diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index da1caab4..57301e2c 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -4,7 +4,6 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
-
 PROVIDE(UserSoft = DefaultHandler);
 PROVIDE(SupervisorSoft = DefaultHandler);
 PROVIDE(MachineSoft = DefaultHandler);

From 9e589b549344a76a43806f0c4c6d6d31e18653a1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Sat, 8 Jul 2023 19:26:40 +0200
Subject: [PATCH 206/234] Ready for PR

---
 riscv-rt/.github/workflows/build.yaml         |   2 +-
 riscv-rt/CHANGELOG.md                         |   1 +
 riscv-rt/asm/original_asm.S                   | 189 ------------------
 riscv-rt/asm/riscv32i-unknown-none-elf-m.s    | 123 ------------
 riscv-rt/asm/riscv32i-unknown-none-elf-s.s    | 123 ------------
 riscv-rt/asm/riscv32imac-unknown-none-elf-m.s | 116 -----------
 riscv-rt/asm/riscv32imac-unknown-none-elf-s.s | 116 -----------
 riscv-rt/asm/riscv64imac-unknown-none-elf-m.s | 126 ------------
 riscv-rt/asm/riscv64imac-unknown-none-elf-s.s | 126 ------------
 9 files changed, 2 insertions(+), 920 deletions(-)
 delete mode 100644 riscv-rt/asm/original_asm.S
 delete mode 100644 riscv-rt/asm/riscv32i-unknown-none-elf-m.s
 delete mode 100644 riscv-rt/asm/riscv32i-unknown-none-elf-s.s
 delete mode 100644 riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
 delete mode 100644 riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
 delete mode 100644 riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
 delete mode 100644 riscv-rt/asm/riscv64imac-unknown-none-elf-s.s

diff --git a/riscv-rt/.github/workflows/build.yaml b/riscv-rt/.github/workflows/build.yaml
index 3b532aa2..4c95f06a 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/riscv-rt/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, global_asm ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 50b44407..3cb7aeb0 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
 
 ## [v0.11.0] - 2023-01-18
diff --git a/riscv-rt/asm/original_asm.S b/riscv-rt/asm/original_asm.S
deleted file mode 100644
index 17f10937..00000000
--- a/riscv-rt/asm/original_asm.S
+++ /dev/null
@@ -1,189 +0,0 @@
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
-#else
-# define STORE    sw
-# define LOAD     lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-/*
-    Entry point of all programs (_start).
-
-    It initializes DWARF call frame information, the stack pointer, the
-    frame pointer (needed for closures to work in start_rust) and the global
-    pointer. Then it calls _start_rust.
-*/
-
-.section .init, "ax"
-.global _start
-
-_start:
-    /* Jump to the absolute address defined by the linker script. */
-    // for 32bit
-    .if __riscv_xlen == 32
-    lui ra, %hi(_abs_start)
-    jr %lo(_abs_start)(ra)
-    .endif
-
-    // for 64bit
-    .if __riscv_xlen == 64
-.option push
-.option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
-1:
-    auipc ra, %pcrel_hi(1f)
-    ld ra, %pcrel_lo(1b)(ra)
-    jr ra
-    .align  3
-1:
-    .dword _abs_start
-.option pop
-    .endif
-
-_abs_start:
-    .cfi_startproc
-    .cfi_undefined ra
-
-    #ifdef SMODE
-    csrw sie, 0     // interrupt disable 
-    csrw sip, 0     // no pending interrupts
-    #else
-    csrw mie, 0
-    csrw mip, 0
-    #endif
-    
-
-    li  x1, 0
-    li  x2, 0
-    li  x3, 0
-    li  x4, 0
-    li  x5, 0
-    li  x6, 0
-    li  x7, 0
-    li  x8, 0
-    li  x9, 0
-    // a0..a2 (x10..x12) skipped
-    li  x13,0
-    li  x14,0
-    li  x15,0
-    li  x16,0
-    li  x17,0
-    li  x18,0
-    li  x19,0
-    li  x20,0
-    li  x21,0
-    li  x22,0
-    li  x23,0
-    li  x24,0
-    li  x25,0
-    li  x26,0
-    li  x27,0
-    li  x28,0
-    li  x29,0
-    li  x30,0
-    li  x31,0
-
-    .option push
-    .option norelax
-    la gp, __global_pointer$
-    .option pop
-
-    #ifdef SMODE
-    // there is no equivalent of mhartid in supervisor mode.
-    // instead, the hartid is passed as paramter by SMODE
-    mv t2, a0   
-    #else 
-    csrr t2, mhartid
-    #endif
-    lui t0, %hi(_max_hart_id)
-    add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort
-
-    // Allocate stacks
-    la sp, _stack_start
-    lui t0, %hi(_hart_stack_size)
-    add t0, t0, %lo(_hart_stack_size)
-#ifdef __riscv_mul
-    mul t0, t2, t0
-#else
-    beqz t2, 2f  // Jump if single-hart
-    mv t1, t2
-    mv t3, t0
-1:
-    add t0, t0, t3
-    addi t1, t1, -1
-    bnez t1, 1b
-2:
-#endif
-    sub sp, sp, t0
-
-    // Set frame pointer
-    add s0, sp, zero
-
-    jal zero, _start_rust
-
-    .cfi_endproc
-
-/*
-    Trap entry point (_start_trap)
-
-    Saves caller saved registers ra, t0..6, a0..7, calls _start_trap_rust,
-    restores caller saved registers and then returns.
-*/
-.section .trap, "ax"
-.global default_start_trap
-
-default_start_trap:
-    addi sp, sp, -16*REGBYTES
-
-    STORE ra, 0*REGBYTES(sp)
-    STORE t0, 1*REGBYTES(sp)
-    STORE t1, 2*REGBYTES(sp)
-    STORE t2, 3*REGBYTES(sp)
-    STORE t3, 4*REGBYTES(sp)
-    STORE t4, 5*REGBYTES(sp)
-    STORE t5, 6*REGBYTES(sp)
-    STORE t6, 7*REGBYTES(sp)
-    STORE a0, 8*REGBYTES(sp)
-    STORE a1, 9*REGBYTES(sp)
-    STORE a2, 10*REGBYTES(sp)
-    STORE a3, 11*REGBYTES(sp)
-    STORE a4, 12*REGBYTES(sp)
-    STORE a5, 13*REGBYTES(sp)
-    STORE a6, 14*REGBYTES(sp)
-    STORE a7, 15*REGBYTES(sp)
-
-    add a0, sp, zero
-    jal ra, _start_trap_rust
-
-    LOAD ra, 0*REGBYTES(sp)
-    LOAD t0, 1*REGBYTES(sp)
-    LOAD t1, 2*REGBYTES(sp)
-    LOAD t2, 3*REGBYTES(sp)
-    LOAD t3, 4*REGBYTES(sp)
-    LOAD t4, 5*REGBYTES(sp)
-    LOAD t5, 6*REGBYTES(sp)
-    LOAD t6, 7*REGBYTES(sp)
-    LOAD a0, 8*REGBYTES(sp)
-    LOAD a1, 9*REGBYTES(sp)
-    LOAD a2, 10*REGBYTES(sp)
-    LOAD a3, 11*REGBYTES(sp)
-    LOAD a4, 12*REGBYTES(sp)
-    LOAD a5, 13*REGBYTES(sp)
-    LOAD a6, 14*REGBYTES(sp)
-    LOAD a7, 15*REGBYTES(sp)
-
-    addi sp, sp, 16*REGBYTES
-    #ifdef SMODE
-    sret
-    #else
-    mret
-    #endif
-
-/* Make sure there is an abort when linking */
-.section .text.abort
-.globl abort
-abort:
-    j abort
diff --git a/riscv-rt/asm/riscv32i-unknown-none-elf-m.s b/riscv-rt/asm/riscv32i-unknown-none-elf-m.s
deleted file mode 100644
index f501993c..00000000
--- a/riscv-rt/asm/riscv32i-unknown-none-elf-m.s
+++ /dev/null
@@ -1,123 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0"
-	.file	"zk0t2u2b1an050m"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	beqz	t2, .Ltmp0
-	mv	t1, t2
-	mv	t3, t0
-.Ltmp1:
-	add	t0, t0, t3
-	addi	t1, t1, -1
-	bnez	t1, .Ltmp1
-.Ltmp0:
-	sub	sp, sp, t0
-	add	s0, sp, zero
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort
diff --git a/riscv-rt/asm/riscv32i-unknown-none-elf-s.s b/riscv-rt/asm/riscv32i-unknown-none-elf-s.s
deleted file mode 100644
index 52b84f70..00000000
--- a/riscv-rt/asm/riscv32i-unknown-none-elf-s.s
+++ /dev/null
@@ -1,123 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0"
-	.file	"eaqpawb8fun9h0d"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	beqz	t2, .Ltmp0
-	mv	t1, t2
-	mv	t3, t0
-.Ltmp1:
-	add	t0, t0, t3
-	addi	t1, t1, -1
-	bnez	t1, .Ltmp1
-.Ltmp0:
-	sub	sp, sp, t0
-	add	s0, sp, zero
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort
diff --git a/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s b/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
deleted file mode 100644
index eee62b9f..00000000
--- a/riscv-rt/asm/riscv32imac-unknown-none-elf-m.s
+++ /dev/null
@@ -1,116 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
-	.file	"3wdx7lxc78dgym21"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort
diff --git a/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s b/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
deleted file mode 100644
index 32d504a9..00000000
--- a/riscv-rt/asm/riscv32imac-unknown-none-elf-s.s
+++ /dev/null
@@ -1,116 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv32i2p0_m2p0_a2p0_c2p0"
-	.file	"2mpkjzuft8hmeuib"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	lui	ra, %hi(_abs_start)
-	jalr	zero, %lo(_abs_start)(ra)
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -64
-	sw	ra, 0(sp)
-	sw	t0, 4(sp)
-	sw	t1, 8(sp)
-	sw	t2, 12(sp)
-	sw	t3, 16(sp)
-	sw	t4, 20(sp)
-	sw	t5, 24(sp)
-	sw	t6, 28(sp)
-	sw	a0, 32(sp)
-	sw	a1, 36(sp)
-	sw	a2, 40(sp)
-	sw	a3, 44(sp)
-	sw	a4, 48(sp)
-	sw	a5, 52(sp)
-	sw	a6, 56(sp)
-	sw	a7, 60(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	lw	ra, 0(sp)
-	lw	t0, 4(sp)
-	lw	t1, 8(sp)
-	lw	t2, 12(sp)
-	lw	t3, 16(sp)
-	lw	t4, 20(sp)
-	lw	t5, 24(sp)
-	lw	t6, 28(sp)
-	lw	a0, 32(sp)
-	lw	a1, 36(sp)
-	lw	a2, 40(sp)
-	lw	a3, 44(sp)
-	lw	a4, 48(sp)
-	lw	a5, 52(sp)
-	lw	a6, 56(sp)
-	lw	a7, 60(sp)
-	addi	sp, sp, 64
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort
diff --git a/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s b/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
deleted file mode 100644
index 3d57d129..00000000
--- a/riscv-rt/asm/riscv64imac-unknown-none-elf-m.s
+++ /dev/null
@@ -1,126 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
-	.file	"1ruuache5c4x1fns"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	.option	push
-
-	.option	norelax
-.Ltmp0:
-	auipc	ra, %pcrel_hi(.Ltmp1)
-	ld	ra, %pcrel_lo(.Ltmp0)(ra)
-	ret
-	.p2align	3
-.Ltmp1:
-	.quad	_abs_start
-	.option	pop
-
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	mie, 0
-	csrwi	mip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	csrr	t2, mhartid
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -128
-	sd	ra, 0(sp)
-	sd	t0, 8(sp)
-	sd	t1, 16(sp)
-	sd	t2, 24(sp)
-	sd	t3, 32(sp)
-	sd	t4, 40(sp)
-	sd	t5, 48(sp)
-	sd	t6, 56(sp)
-	sd	a0, 64(sp)
-	sd	a1, 72(sp)
-	sd	a2, 80(sp)
-	sd	a3, 88(sp)
-	sd	a4, 96(sp)
-	sd	a5, 104(sp)
-	sd	a6, 112(sp)
-	sd	a7, 120(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	ld	ra, 0(sp)
-	ld	t0, 8(sp)
-	ld	t1, 16(sp)
-	ld	t2, 24(sp)
-	ld	t3, 32(sp)
-	ld	t4, 40(sp)
-	ld	t5, 48(sp)
-	ld	t6, 56(sp)
-	ld	a0, 64(sp)
-	ld	a1, 72(sp)
-	ld	a2, 80(sp)
-	ld	a3, 88(sp)
-	ld	a4, 96(sp)
-	ld	a5, 104(sp)
-	ld	a6, 112(sp)
-	ld	a7, 120(sp)
-	addi	sp, sp, 128
-	mret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort
diff --git a/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s b/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s
deleted file mode 100644
index 5626f5d5..00000000
--- a/riscv-rt/asm/riscv64imac-unknown-none-elf-s.s
+++ /dev/null
@@ -1,126 +0,0 @@
-	.text
-	.attribute	4, 16
-	.attribute	5, "rv64i2p0_m2p0_a2p0_c2p0"
-	.file	"5194e8m2dkkkh98p"
-
-	.section	.init,"ax",@progbits
-	.globl	_start
-
-_start:
-
-	.option	push
-
-	.option	norelax
-.Ltmp0:
-	auipc	ra, %pcrel_hi(.Ltmp1)
-	ld	ra, %pcrel_lo(.Ltmp0)(ra)
-	ret
-	.p2align	3
-.Ltmp1:
-	.quad	_abs_start
-	.option	pop
-
-
-_abs_start:
-	.cfi_startproc
-	.cfi_undefined ra
-	csrwi	sie, 0
-	csrwi	sip, 0
-	li	ra, 0
-	li	sp, 0
-	li	gp, 0
-	li	tp, 0
-	li	t0, 0
-	li	t1, 0
-	li	t2, 0
-	li	s0, 0
-	li	s1, 0
-	li	a3, 0
-	li	a4, 0
-	li	a5, 0
-	li	a6, 0
-	li	a7, 0
-	li	s2, 0
-	li	s3, 0
-	li	s4, 0
-	li	s5, 0
-	li	s6, 0
-	li	s7, 0
-	li	s8, 0
-	li	s9, 0
-	li	s10, 0
-	li	s11, 0
-	li	t3, 0
-	li	t4, 0
-	li	t5, 0
-	li	t6, 0
-
-	.option	push
-
-	.option	norelax
-
-.Lpcrel_hi0:
-	auipc	gp, %pcrel_hi(__global_pointer$)
-	addi	gp, gp, %pcrel_lo(.Lpcrel_hi0)
-	.option	pop
-
-	mv	t2, a0
-	lui	t0, %hi(_max_hart_id)
-	addi	t0, t0, %lo(_max_hart_id)
-	bltu	t0, t2, abort
-
-.Lpcrel_hi1:
-	auipc	sp, %pcrel_hi(_stack_start)
-	addi	sp, sp, %pcrel_lo(.Lpcrel_hi1)
-	lui	t0, %hi(_hart_stack_size)
-	addi	t0, t0, %lo(_hart_stack_size)
-	mul	t0, t2, t0
-	sub	sp, sp, t0
-	mv	s0, sp
-	j	_start_rust
-
-	.cfi_endproc
-	.section	.trap,"ax",@progbits
-	.globl	default_start_trap
-default_start_trap:
-	addi	sp, sp, -128
-	sd	ra, 0(sp)
-	sd	t0, 8(sp)
-	sd	t1, 16(sp)
-	sd	t2, 24(sp)
-	sd	t3, 32(sp)
-	sd	t4, 40(sp)
-	sd	t5, 48(sp)
-	sd	t6, 56(sp)
-	sd	a0, 64(sp)
-	sd	a1, 72(sp)
-	sd	a2, 80(sp)
-	sd	a3, 88(sp)
-	sd	a4, 96(sp)
-	sd	a5, 104(sp)
-	sd	a6, 112(sp)
-	sd	a7, 120(sp)
-	mv	a0, sp
-	jal	_start_trap_rust
-	ld	ra, 0(sp)
-	ld	t0, 8(sp)
-	ld	t1, 16(sp)
-	ld	t2, 24(sp)
-	ld	t3, 32(sp)
-	ld	t4, 40(sp)
-	ld	t5, 48(sp)
-	ld	t6, 56(sp)
-	ld	a0, 64(sp)
-	ld	a1, 72(sp)
-	ld	a2, 80(sp)
-	ld	a3, 88(sp)
-	ld	a4, 96(sp)
-	ld	a5, 104(sp)
-	ld	a6, 112(sp)
-	ld	a7, 120(sp)
-	addi	sp, sp, 128
-	sret	
-	.section	.text.abort,"ax",@progbits
-	.globl	abort
-abort:
-	j	abort

From e540f1e410d5d010f9b9d90c5aea99c1742bd2ac Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Sun, 30 Jul 2023 23:18:44 +0800
Subject: [PATCH 207/234] Add feature single-hart

Signed-off-by: Chien Wong <m@xv97.com>
---
 riscv-rt/Cargo.toml |  1 +
 riscv-rt/src/asm.rs | 22 +++++++++++-----------
 riscv-rt/src/lib.rs |  4 ++++
 3 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 5fc45ccf..719beb50 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -12,6 +12,7 @@ edition = "2018"
 
 [features]
 s-mode = []
+single-hart = []
 
 [dependencies]
 r0 = "1.0.0"
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index f4dbf5d8..c29d9183 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -86,21 +86,21 @@ _abs_start:
     .option norelax
     la gp, __global_pointer$
     .option pop",
-    #[cfg(feature = "s-mode")]
+    #[cfg(all(not(feature = "single-hart"), feature = "s-mode"))]
     "mv t2, a0 // the hartid is passed as parameter by SMODE",
-    #[cfg(not(feature = "s-mode"))]
+    #[cfg(all(not(feature = "single-hart"), not(feature = "s-mode")))]
     "csrr t2, mhartid",
+    #[cfg(not(feature = "single-hart"))]
     "lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort
-
-    // Allocate stacks
+    bgtu t2, t0, abort",
+    "// Allocate stacks
     la sp, _stack_start
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)",
-    #[cfg(riscvm)]
+    #[cfg(all(not(feature = "single-hart"), riscvm))]
     "mul t0, t2, t0",
-    #[cfg(not(riscvm))]
+    #[cfg(all(not(feature = "single-hart"), not(riscvm)))]
     "beqz t2, 2f  // Jump if single-hart
     mv t1, t2
     mv t3, t0
@@ -110,8 +110,8 @@ _abs_start:
     bnez t1, 1b
 2:  ",
     "sub sp, sp, t0
-    
-    // Set frame pointer 
+
+    // Set frame pointer
     add s0, sp, zero
 
     jal zero, _start_rust
@@ -121,9 +121,9 @@ _abs_start:
 
 /// Trap entry point (_start_trap). It saves caller saved registers, calls
 /// _start_trap_rust, restores caller saved registers and then returns.
-/// 
+///
 /// # Usage
-/// 
+///
 /// The macro takes 5 arguments:
 /// - `$STORE`: the instruction used to store a register in the stack (e.g. `sd` for riscv64)
 /// - `$LOAD`: the instruction used to load a register from the stack (e.g. `ld` for riscv64)
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index e0613127..3aff50ef 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -325,6 +325,10 @@
 //!
 //! # Features
 //!
+//! ## `single-hart`
+//!
+//! This feature saves a little code size by removing unnecessary stack space calculation if there is only one hart on the target.
+//!
 //! ## `s-mode`
 //!
 //! The supervisor mode feature (`s-mode`) can be activated via [Cargo features](https://doc.rust-lang.org/cargo/reference/features.html).

From 89be0f4d1fb228d92e2e8a22dfc10d46749c8e68 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 11 Aug 2023 16:49:41 +0200
Subject: [PATCH 208/234] cargo clippy --fix

---
 riscv-rt/src/lib.rs | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 3aff50ef..f8bf60a2 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -472,17 +472,15 @@ pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
 
         if cause.is_exception() {
             ExceptionHandler(&*trap_frame)
-        } else {
-            if cause.code() < __INTERRUPTS.len() {
-                let h = &__INTERRUPTS[cause.code()];
-                if h.reserved == 0 {
-                    DefaultHandler();
-                } else {
-                    (h.handler)();
-                }
-            } else {
+        } else if cause.code() < __INTERRUPTS.len() {
+            let h = &__INTERRUPTS[cause.code()];
+            if h.reserved == 0 {
                 DefaultHandler();
+            } else {
+                (h.handler)();
             }
+        } else {
+            DefaultHandler();
         }
     }
 }

From a47aca14412374641f7909ecd035da9776e6209d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 11 Aug 2023 17:07:20 +0200
Subject: [PATCH 209/234] Added clippy workflow

---
 riscv-rt/.github/workflows/clippy.yaml | 42 ++++++++++++++++++++++++
 riscv-rt/CHANGELOG.md                  |  5 +++
 riscv-rt/src/lib.rs                    | 45 +++++++++++++++-----------
 3 files changed, 73 insertions(+), 19 deletions(-)
 create mode 100644 riscv-rt/.github/workflows/clippy.yaml

diff --git a/riscv-rt/.github/workflows/clippy.yaml b/riscv-rt/.github/workflows/clippy.yaml
new file mode 100644
index 00000000..7c0d5474
--- /dev/null
+++ b/riscv-rt/.github/workflows/clippy.yaml
@@ -0,0 +1,42 @@
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+  merge_group:
+
+name: Lints compliance check
+
+env:
+  CLIPPY_PARAMS: -W clippy::all -W clippy::pedantic -W clippy::nursery -W clippy::cargo
+
+jobs:
+  clippy:
+    strategy:
+      matrix:
+        toolchain: [ stable, nightly ]
+        cargo_flags:
+          - "--no-default-features"
+          - "--all-features"
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+      - uses: actions/checkout@v3
+      - uses: dtolnay/rust-toolchain@master
+        with:
+          toolchain: ${{ matrix.toolchain }}
+          components: clippy
+      - name: Run clippy
+        run: cargo clippy --all ${{ matrix.cargo_flags }} -- -D warnings
+
+   # Job to check that all the lint checks succeeded
+  clippy-check:
+    needs:
+    - clippy
+    runs-on: ubuntu-latest
+    if: always()
+    steps:
+      - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 3cb7aeb0..ed532c57 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,10 +7,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- New GitHub workflow for checking clippy lints in PRs
+
 ### Changed
 
 - Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
+- `start_trap_rust` is now marked as `unsafe`
 
 ## [v0.11.0] - 2023-01-18
 
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index f8bf60a2..b96c4283 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -106,9 +106,9 @@
 //! Disassembly of section .text:
 //!
 //! 20000000 <_start>:
-//! 20000000:	800011b7          	lui	gp,0x80001
-//! 20000004:	80018193          	addi	gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
-//! 20000008:	80004137          	lui	sp,0x80004
+//! 20000000:    800011b7        lui     gp,0x80001
+//! 20000004:    80018193        addi    gp,gp,-2048 # 80000800 <_stack_start+0xffffc800>
+//! 20000008:    80004137        lui     sp,0x80004
 //! ```
 //!
 //! # Symbol interfaces
@@ -393,8 +393,12 @@ extern "C" {
 
 /// Rust entry point (_start_rust)
 ///
-/// Zeros bss section, initializes data section and calls main. This function
-/// never returns.
+/// Zeros bss section, initializes data section and calls main. This function never returns.
+///
+/// # Safety
+///
+/// This function must be called only from assembly `_start` function.
+/// Do **NOT** call this function directly.
 #[link_section = ".init.rust"]
 #[export_name = "_start_rust"]
 pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
@@ -459,29 +463,32 @@ pub struct TrapFrame {
 /// `scause`/`mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
 /// if it's an interrupt or an exception. The result is examined and ExceptionHandler
 /// or one of the core interrupt handlers is called.
+///
+/// # Safety
+///
+/// This function must be called only from assembly `_start_trap` function.
+/// Do **NOT** call this function directly.
 #[link_section = ".trap.rust"]
 #[export_name = "_start_trap_rust"]
-pub extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
+pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
     extern "C" {
         fn ExceptionHandler(trap_frame: &TrapFrame);
         fn DefaultHandler();
     }
 
-    unsafe {
-        let cause = xcause::read();
-
-        if cause.is_exception() {
-            ExceptionHandler(&*trap_frame)
-        } else if cause.code() < __INTERRUPTS.len() {
-            let h = &__INTERRUPTS[cause.code()];
-            if h.reserved == 0 {
-                DefaultHandler();
-            } else {
-                (h.handler)();
-            }
-        } else {
+    let cause = xcause::read();
+
+    if cause.is_exception() {
+        ExceptionHandler(&*trap_frame)
+    } else if cause.code() < __INTERRUPTS.len() {
+        let h = &__INTERRUPTS[cause.code()];
+        if h.reserved == 0 {
             DefaultHandler();
+        } else {
+            (h.handler)();
         }
+    } else {
+        DefaultHandler();
     }
 }
 

From eef90a0f2552307f2c5e666508a4bd971dcb40a3 Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <me@gburghoorn.com>
Date: Fri, 22 Sep 2023 19:34:44 +0200
Subject: [PATCH 210/234] Implement r0 crate in assembly

This implements the `r0::init_data` and `r0::zero_bss` routines in
assembly. There is a generic implementation for `riscv32` and
`riscv64`, since `riscv64` deals with alignment problems. The routines
are kept at their old calling site so that only one hardware thread
calls them. Consequently they are also inlined into the `start_rust`
function.

[Issue #122]
---
 riscv-rt/Cargo.toml |  1 -
 riscv-rt/link.x     |  2 +-
 riscv-rt/src/lib.rs | 62 ++++++++++++++++++++++++++++++++++-----------
 3 files changed, 48 insertions(+), 17 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 719beb50..c65c24e5 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -15,7 +15,6 @@ s-mode = []
 single-hart = []
 
 [dependencies]
-r0 = "1.0.0"
 riscv = "0.10"
 riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index 57301e2c..deadea88 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -84,7 +84,7 @@ SECTIONS
     _edata = .;
   } > REGION_DATA AT > REGION_RODATA
 
-  .bss (NOLOAD) :
+  .bss (NOLOAD) : ALIGN(4)
   {
     _sbss = .;
     *(.sbss .sbss.* .bss .bss.*);
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index b96c4283..4eb2d609 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -366,6 +366,8 @@
 #[cfg(riscv)]
 mod asm;
 
+use core::sync::atomic::{compiler_fence, Ordering};
+
 #[cfg(feature = "s-mode")]
 use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};
 
@@ -378,19 +380,6 @@ pub use riscv_rt_macros::{entry, pre_init};
 #[doc(hidden)]
 pub static __ONCE__: () = ();
 
-extern "C" {
-    // Boundaries of the .bss section
-    static mut _ebss: u32;
-    static mut _sbss: u32;
-
-    // Boundaries of the .data section
-    static mut _edata: u32;
-    static mut _sdata: u32;
-
-    // Initial values of the .data section (stored in Flash)
-    static _sidata: u32;
-}
-
 /// Rust entry point (_start_rust)
 ///
 /// Zeros bss section, initializes data section and calls main. This function never returns.
@@ -424,8 +413,51 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
     if _mp_hook(hartid) {
         __pre_init();
 
-        r0::zero_bss(&mut _sbss, &mut _ebss);
-        r0::init_data(&mut _sdata, &mut _edata, &_sidata);
+        // Initialize RAM (32-bit version)
+        // 1. Copy over .data from flash to RAM
+        // 2. Zero out .bss
+        core::arch::asm!(
+            "
+                // Copy over .data
+                la      {start},_sdata
+                la      {end},_edata
+                la      {input},_sidata
+
+            1:
+            	addi    {a},{start},4
+            	bgeu    {a},{end},1f
+            	lw      {b},0({input})
+            	sw      {b},0({start})
+            	addi    {start},{start},4
+            	addi    {input},{input},4
+            	j       1b
+
+            1:
+                // Zero out .bss
+            	la      {start},_sbss
+            	la      {end},_ebss
+
+            2:
+            	addi    {a},{start},4
+            	bgeu    {a},{end},2f
+            	sw      zero,0({start})
+            	addi    {start},{start},4
+            	j       2b
+
+            2:
+
+                li      {start},0
+                li      {end},0
+                li      {input},0
+            ",
+            start = out(reg) _,
+            end = out(reg) _,
+            input = out(reg) _,
+            a = out(reg) _,
+            b = out(reg) _,
+        );
+
+        compiler_fence(Ordering::SeqCst);
     }
 
     // TODO: Enable FPU when available

From 1f29bd359522123c966949cd4fe8426ff87337ae Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <g.burghoorn@gmail.com>
Date: Thu, 28 Sep 2023 17:48:10 +0200
Subject: [PATCH 211/234] Impr: r0 loops to minimize instructions

---
 riscv-rt/src/lib.rs | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 4eb2d609..e0534140 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -413,7 +413,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
     if _mp_hook(hartid) {
         __pre_init();
 
-        // Initialize RAM (32-bit version)
+        // Initialize RAM
         // 1. Copy over .data from flash to RAM
         // 2. Zero out .bss
         core::arch::asm!(
@@ -423,29 +423,28 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
                 la      {end},_edata
                 la      {input},_sidata
 
+            	bgeu    {start},{end},2f
             1:
-            	addi    {a},{start},4
-            	bgeu    {a},{end},1f
-            	lw      {b},0({input})
-            	sw      {b},0({start})
-            	addi    {start},{start},4
+            	lw      {a},0({input})
             	addi    {input},{input},4
-            	j       1b
+            	sw      {a},0({start})
+            	addi    {start},{start},4
+            	bltu    {start},{end},1b
+
+            2:
+                li      {a},0
 
-            1:
                 // Zero out .bss
             	la      {start},_sbss
             	la      {end},_ebss
 
+            	bgeu    {start},{end},3f
             2:
-            	addi    {a},{start},4
-            	bgeu    {a},{end},2f
             	sw      zero,0({start})
             	addi    {start},{start},4
-            	j       2b
-
-            2:
+            	bltu    {start},{end},2b
 
+            3:
                 li      {start},0
                 li      {end},0
                 li      {input},0
@@ -454,7 +453,6 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             end = out(reg) _,
             input = out(reg) _,
             a = out(reg) _,
-            b = out(reg) _,
         );
 
         compiler_fence(Ordering::SeqCst);

From 6c517f26618f9f003be5b30a85541c369db1c68d Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <g.burghoorn@gmail.com>
Date: Fri, 29 Sep 2023 13:48:45 +0200
Subject: [PATCH 212/234] Impr: add rv64 version of r0 assembly

---
 riscv-rt/link.x     |  4 ++
 riscv-rt/src/lib.rs | 96 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 100 insertions(+)

diff --git a/riscv-rt/link.x b/riscv-rt/link.x
index deadea88..ebb55c15 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link.x
@@ -150,6 +150,10 @@ BUG(riscv-rt): .data is not 4-byte aligned");
 ASSERT(_sidata % 4 == 0, "
 BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
 
+/* Make sure that we can safely perform .data initialization on RV64 */ 
+ASSERT(_sidata % 8 == _sdata % 8, "
+BUG(riscv-rt): .data is not similarly 8-byte aligned to the LMA of .data");
+
 ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
 BUG(riscv-rt): .bss is not 4-byte aligned");
 
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index e0534140..325387b5 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -416,6 +416,8 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
         // Initialize RAM
         // 1. Copy over .data from flash to RAM
         // 2. Zero out .bss
+
+        #[cfg(target_arch = "riscv32")]
         core::arch::asm!(
             "
                 // Copy over .data
@@ -455,6 +457,100 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             a = out(reg) _,
         );
 
+        #[cfg(target_arch = "riscv64")]
+        core::arch::asm!(
+            "
+                // Copy over .data
+                la      {start},_sdata
+                la      {end},_edata
+                la      {input},_sidata
+
+                bgeu    {start},{end},3f
+
+                //    If _sdata and _sidata are not 8-byte aligned, we copy one word before the main loop. This way, in
+                //    the main loop, we are sure `start` and `input` are 8-byte aligned. This is needed to safely
+                //    perform load and store double instructions.
+                //
+                //    NOTE: We assert in the `link.x` file that _sdata and _sidata are similarly 8-byte aligned. This is
+                //          needed for the main loop here.
+                andi    {b},{start},4
+                beqz    {b},0f
+                lw      {a},0({input})
+                addi    {input},{input},4
+                sw      {a},0({start})
+                addi    {start},{start},4
+
+            0: // .data Main Loop Initialization
+                //    b = FLOOR_ALIGN(_edata, 4)
+                andi    {b},{end},4
+                sub     {b},{end},{b}
+
+            	bgeu    {start},{b},2f
+            1: // .data Main Loop
+            	ld      {a},0({input})
+            	addi    {input},{input},8
+            	sd      {a},0({start})
+            	addi    {start},{start},8
+            	bltu    {start},{b},1b
+            
+            2: // .data end align
+                //    If _edata is not 8-byte aligned, we copy one word after the main loop. This way we are sure we
+                //    copied all the data even if _edata is 4-byte aligned.
+                andi    {b},{end},4
+                beqz    {b},3f
+                lw      {a},0({input})
+                addi    {input},{input},4
+                sw      {a},0({start})
+                addi    {start},{start},4
+            
+            3: // .data zero registers
+                li      {a},0
+                li      {input},0
+
+            4: // zero out .bss start
+            	la      {start},_sbss
+            	la      {end},_ebss
+            
+                bgeu    {start},{end},8f
+
+                //    If _sbss is not 8-byte aligned, we zero one word before the main loop. This way, in the main
+                //    loop, we are sure `start` is 8-byte aligned. This is needed to safely perform store double
+                //    instruction.
+                andi    {b},{start},4
+                beqz    {b},5f
+            	sw      zero,0({start})
+            	addi    {start},{start},4
+
+            5: // .bss main loop initialization
+                //    b = FLOOR_ALIGN(_ebss, 4)
+                andi    {b},{end},4
+                sub     {b},{end},{b}
+
+            	bgeu    {start},{b},7f
+            6: // .bss main loop
+            	sd      zero,0({start})
+            	addi    {start},{start},8
+            	bltu    {start},{b},6b
+
+            7: // .bss end align
+                //    If _ebss is not 8-byte aligned, we need to zero more one word after the main loop.
+                andi    {b},{end},4
+                beqz    {b},8f
+            	sw      zero,0({start})
+
+            8: // .bss zero registers
+                //    Zero out used registers
+                li      {b},0
+                li      {start},0
+                li      {end},0
+        ",
+            start = out(reg) _,
+            end = out(reg) _,
+            input = out(reg) _,
+            a = out(reg) _,
+            b = out(reg) _,
+        );
+
         compiler_fence(Ordering::SeqCst);
     }
 

From 01711b7b210c95ba3b097ec4136ac7c0b71b0a79 Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <g.burghoorn@gmail.com>
Date: Fri, 29 Sep 2023 14:06:21 +0200
Subject: [PATCH 213/234] Doc: Adjust CHANGELOG.md

---
 riscv-rt/CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index ed532c57..b49b13c7 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
 - `start_trap_rust` is now marked as `unsafe`
+- Implement `r0` as inline assembly
 
 ## [v0.11.0] - 2023-01-18
 

From 56125182b03f33cfbfee20c9a7c1bfa16178ed21 Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <g.burghoorn@gmail.com>
Date: Mon, 2 Oct 2023 15:40:12 +0200
Subject: [PATCH 214/234] Fix: Add separate linkerscripts for rv32 and rv64

---
 riscv-rt/build.rs                |  17 +--
 riscv-rt/{link.x => link-rv32.x} |   4 -
 riscv-rt/link-rv64.x             | 174 +++++++++++++++++++++++++++++++
 riscv-rt/src/lib.rs              |  70 ++-----------
 4 files changed, 194 insertions(+), 71 deletions(-)
 rename riscv-rt/{link.x => link-rv32.x} (96%)
 create mode 100644 riscv-rt/link-rv64.x

diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 23177c28..c23da012 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -5,9 +5,17 @@ use std::env;
 use std::fs;
 use std::path::PathBuf;
 
+fn add_linker_script(bytes: &[u8]) {
+    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+
+    // Put the linker script somewhere the linker can find it
+    fs::write(out_dir.join("link.x"), bytes).unwrap();
+    println!("cargo:rustc-link-search={}", out_dir.display());
+    println!("cargo:rerun-if-changed=link.x");
+}
+
 fn main() {
     let target = env::var("TARGET").unwrap();
-    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
     let _name = env::var("CARGO_PKG_NAME").unwrap();
 
     // set configuration flags depending on the target
@@ -17,9 +25,11 @@ fn main() {
         match target.bits {
             32 => {
                 println!("cargo:rustc-cfg=riscv32");
+                add_linker_script(include_bytes!("link-rv32.x"));
             }
             64 => {
                 println!("cargo:rustc-cfg=riscv64");
+                add_linker_script(include_bytes!("link-rv64.x"));
             }
             _ => panic!("Unsupported bit width"),
         }
@@ -27,9 +37,4 @@ fn main() {
             println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
         }
     }
-
-    // Put the linker script somewhere the linker can find it
-    fs::write(out_dir.join("link.x"), include_bytes!("link.x")).unwrap();
-    println!("cargo:rustc-link-search={}", out_dir.display());
-    println!("cargo:rerun-if-changed=link.x");
 }
diff --git a/riscv-rt/link.x b/riscv-rt/link-rv32.x
similarity index 96%
rename from riscv-rt/link.x
rename to riscv-rt/link-rv32.x
index ebb55c15..deadea88 100644
--- a/riscv-rt/link.x
+++ b/riscv-rt/link-rv32.x
@@ -150,10 +150,6 @@ BUG(riscv-rt): .data is not 4-byte aligned");
 ASSERT(_sidata % 4 == 0, "
 BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
 
-/* Make sure that we can safely perform .data initialization on RV64 */ 
-ASSERT(_sidata % 8 == _sdata % 8, "
-BUG(riscv-rt): .data is not similarly 8-byte aligned to the LMA of .data");
-
 ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
 BUG(riscv-rt): .bss is not 4-byte aligned");
 
diff --git a/riscv-rt/link-rv64.x b/riscv-rt/link-rv64.x
new file mode 100644
index 00000000..8128eac7
--- /dev/null
+++ b/riscv-rt/link-rv64.x
@@ -0,0 +1,174 @@
+PROVIDE(_stext = ORIGIN(REGION_TEXT));
+PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
+PROVIDE(_max_hart_id = 0);
+PROVIDE(_hart_stack_size = 2K);
+PROVIDE(_heap_size = 0);
+
+PROVIDE(UserSoft = DefaultHandler);
+PROVIDE(SupervisorSoft = DefaultHandler);
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(UserTimer = DefaultHandler);
+PROVIDE(SupervisorTimer = DefaultHandler);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(UserExternal = DefaultHandler);
+PROVIDE(SupervisorExternal = DefaultHandler);
+PROVIDE(MachineExternal = DefaultHandler);
+
+PROVIDE(DefaultHandler = DefaultInterruptHandler);
+PROVIDE(ExceptionHandler = DefaultExceptionHandler);
+
+/* # Pre-initialization function */
+/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
+   then the function this points to will be called before the RAM is initialized. */
+PROVIDE(__pre_init = default_pre_init);
+
+/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
+PROVIDE(_setup_interrupts = default_setup_interrupts);
+
+/* # Multi-processing hook function
+   fn _mp_hook() -> bool;
+
+   This function is called from all the harts and must return true only for one hart,
+   which will perform memory initialization. For other harts it must return false
+   and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
+*/
+PROVIDE(_mp_hook = default_mp_hook);
+
+/* # Start trap function override
+  By default uses the riscv crates default trap handler
+  but by providing the `_start_trap` symbol external crates can override.
+*/
+PROVIDE(_start_trap = default_start_trap);
+
+SECTIONS
+{
+  .text.dummy (NOLOAD) :
+  {
+    /* This section is intended to make _stext address work */
+    . = ABSOLUTE(_stext);
+  } > REGION_TEXT
+
+  .text _stext :
+  {
+    /* Put reset handler first in .text section so it ends up as the entry */
+    /* point of the program. */
+    KEEP(*(.init));
+    KEEP(*(.init.rust));
+    . = ALIGN(4);
+    *(.trap);
+    *(.trap.rust);
+    *(.text.abort);
+    *(.text .text.*);
+  } > REGION_TEXT
+
+  .rodata : ALIGN(4)
+  {
+    *(.srodata .srodata.*);
+    *(.rodata .rodata.*);
+
+    /* 4-byte align the end (VMA) of this section.
+       This is required by LLD to ensure the LMA of the following .data
+       section will have the correct alignment. */
+    . = ALIGN(4);
+  } > REGION_RODATA
+
+  .data : ALIGN(8)
+  {
+    _sidata = LOADADDR(.data);
+    _sdata = .;
+    /* Must be called __global_pointer$ for linker relaxations to work. */
+    PROVIDE(__global_pointer$ = . + 0x800);
+    *(.sdata .sdata.* .sdata2 .sdata2.*);
+    *(.data .data.*);
+    . = ALIGN(8);
+    _edata = .;
+  } > REGION_DATA AT > REGION_RODATA
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    _sbss = .;
+    *(.sbss .sbss.* .bss .bss.*);
+    . = ALIGN(8);
+    _ebss = .;
+  } > REGION_BSS
+
+  /* fictitious region that represents the memory available for the heap */
+  .heap (NOLOAD) :
+  {
+    _sheap = .;
+    . += _heap_size;
+    . = ALIGN(4);
+    _eheap = .;
+  } > REGION_HEAP
+
+  /* fictitious region that represents the memory available for the stack */
+  .stack (NOLOAD) :
+  {
+    _estack = .;
+    . = ABSOLUTE(_stack_start);
+    _sstack = .;
+  } > REGION_STACK
+
+  /* fake output .got section */
+  /* Dynamic relocations are unsupported. This section is only used to detect
+     relocatable code in the input files and raise an error if relocatable code
+     is found */
+  .got (INFO) :
+  {
+    KEEP(*(.got .got.*));
+  }
+
+  .eh_frame (INFO) : { KEEP(*(.eh_frame)) }
+  .eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
+}
+
+/* Do not exceed this mark in the error messages above                                    | */
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_DATA) % 8 == 0, "
+ERROR(riscv-rt): the start of the REGION_DATA must be 8-byte aligned");
+
+ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
+
+ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
+ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
+
+ASSERT(_stext % 4 == 0, "
+ERROR(riscv-rt): `_stext` must be 4-byte aligned");
+
+ASSERT(_sdata % 8 == 0 && _edata % 8 == 0, "
+BUG(riscv-rt): .data is not 8-byte aligned");
+
+ASSERT(_sidata % 8 == 0, "
+BUG(riscv-rt): the LMA of .data is not 8-byte aligned");
+
+ASSERT(_sbss % 8 == 0 && _ebss % 8 == 0, "
+BUG(riscv-rt): .bss is not 8-byte aligned");
+
+ASSERT(_sheap % 4 == 0, "
+BUG(riscv-rt): start of .heap is not 4-byte aligned");
+
+ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
+ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
+Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
+
+ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
+ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
+Consider changing `_max_hart_id` or `_hart_stack_size`.");
+
+ASSERT(SIZEOF(.got) == 0, "
+.got section detected in the input files. Dynamic relocations are not
+supported. If you are linking to C code compiled using the `gcc` crate
+then modify your build script to compile the C code _without_ the
+-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
+details.");
+
+/* Do not exceed this mark in the error messages above                                    | */
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 325387b5..3e86c490 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -435,6 +435,7 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
 
             2:
                 li      {a},0
+                li      {input},0
 
                 // Zero out .bss
             	la      {start},_sbss
@@ -449,7 +450,6 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             3:
                 li      {start},0
                 li      {end},0
-                li      {input},0
             ",
             start = out(reg) _,
             end = out(reg) _,
@@ -465,82 +465,31 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
                 la      {end},_edata
                 la      {input},_sidata
 
-                bgeu    {start},{end},3f
-
-                //    If _sdata and _sidata are not 8-byte aligned, we copy one word before the main loop. This way, in
-                //    the main loop, we are sure `start` and `input` are 8-byte aligned. This is needed to safely
-                //    perform load and store double instructions.
-                //
-                //    NOTE: We assert in the `link.x` file that _sdata and _sidata are similarly 8-byte aligned. This is
-                //          needed for the main loop here.
-                andi    {b},{start},4
-                beqz    {b},0f
-                lw      {a},0({input})
-                addi    {input},{input},4
-                sw      {a},0({start})
-                addi    {start},{start},4
-
-            0: // .data Main Loop Initialization
-                //    b = FLOOR_ALIGN(_edata, 4)
-                andi    {b},{end},4
-                sub     {b},{end},{b}
-
-            	bgeu    {start},{b},2f
+                bgeu    {start},{end},2f
+
             1: // .data Main Loop
             	ld      {a},0({input})
             	addi    {input},{input},8
             	sd      {a},0({start})
             	addi    {start},{start},8
-            	bltu    {start},{b},1b
-            
-            2: // .data end align
-                //    If _edata is not 8-byte aligned, we copy one word after the main loop. This way we are sure we
-                //    copied all the data even if _edata is 4-byte aligned.
-                andi    {b},{end},4
-                beqz    {b},3f
-                lw      {a},0({input})
-                addi    {input},{input},4
-                sw      {a},0({start})
-                addi    {start},{start},4
+            	bltu    {start},{end},1b
             
-            3: // .data zero registers
+            2: // .data zero registers
                 li      {a},0
                 li      {input},0
 
-            4: // zero out .bss start
             	la      {start},_sbss
             	la      {end},_ebss
             
-                bgeu    {start},{end},8f
+                bgeu    {start},{end},4f
 
-                //    If _sbss is not 8-byte aligned, we zero one word before the main loop. This way, in the main
-                //    loop, we are sure `start` is 8-byte aligned. This is needed to safely perform store double
-                //    instruction.
-                andi    {b},{start},4
-                beqz    {b},5f
-            	sw      zero,0({start})
-            	addi    {start},{start},4
-
-            5: // .bss main loop initialization
-                //    b = FLOOR_ALIGN(_ebss, 4)
-                andi    {b},{end},4
-                sub     {b},{end},{b}
-
-            	bgeu    {start},{b},7f
-            6: // .bss main loop
+            3: // .bss main loop
             	sd      zero,0({start})
             	addi    {start},{start},8
-            	bltu    {start},{b},6b
-
-            7: // .bss end align
-                //    If _ebss is not 8-byte aligned, we need to zero more one word after the main loop.
-                andi    {b},{end},4
-                beqz    {b},8f
-            	sw      zero,0({start})
+            	bltu    {start},{end},3b
 
-            8: // .bss zero registers
+            4: // .bss zero registers
                 //    Zero out used registers
-                li      {b},0
                 li      {start},0
                 li      {end},0
         ",
@@ -548,7 +497,6 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
             end = out(reg) _,
             input = out(reg) _,
             a = out(reg) _,
-            b = out(reg) _,
         );
 
         compiler_fence(Ordering::SeqCst);

From 16d0a8190b380999a30dced97965bdd3eeaf306d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 11:05:32 +0200
Subject: [PATCH 215/234] Added GH Action to check CHANGELOG.md

---
 riscv-rt/.github/workflows/changelog.yaml | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 riscv-rt/.github/workflows/changelog.yaml

diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
new file mode 100644
index 00000000..e10f66bc
--- /dev/null
+++ b/riscv-rt/.github/workflows/changelog.yaml
@@ -0,0 +1,22 @@
+name: Check CHANGELOG.md
+
+on:
+  push:
+    branches: [ master, check-changelog ]
+  pull_request:
+  merge_group:
+
+jobs:
+  check_changelog:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v2
+
+      - name: Check for CHANGELOG.md
+        run: |
+          if ! git diff --name-only HEAD^ | grep -q "^CHANGELOG.md$"; then
+            echo "ERROR: CHANGELOG.md not modified in this pull request"
+            exit 1
+          fi

From b3d0c9c057c53cc51c886ac1af6991a4ab796212 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 11:08:59 +0200
Subject: [PATCH 216/234] ready for PR

---
 riscv-rt/.github/workflows/changelog.yaml | 4 ++--
 riscv-rt/CHANGELOG.md                     | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
index e10f66bc..8f828a1c 100644
--- a/riscv-rt/.github/workflows/changelog.yaml
+++ b/riscv-rt/.github/workflows/changelog.yaml
@@ -2,9 +2,9 @@ name: Check CHANGELOG.md
 
 on:
   push:
-    branches: [ master, check-changelog ]
+    branches: [ master ]
   pull_request:
-  merge_group:
+    branches: [ master ]
 
 jobs:
   check_changelog:
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index b49b13c7..ed8eaeac 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- New GitHub worklow for checking modifications on CHANGELOG.md
 - New GitHub workflow for checking clippy lints in PRs
 
 ### Changed

From 6b1a4d207460823d620ca31f58857b1d24d3b7cc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 11:22:27 +0200
Subject: [PATCH 217/234] trying to fix it

---
 riscv-rt/.github/workflows/changelog.yaml | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
index 8f828a1c..b453b02e 100644
--- a/riscv-rt/.github/workflows/changelog.yaml
+++ b/riscv-rt/.github/workflows/changelog.yaml
@@ -1,22 +1,18 @@
 name: Check CHANGELOG.md
 
 on:
-  push:
-    branches: [ master ]
   pull_request:
-    branches: [ master ]
+    types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
 
 jobs:
   check_changelog:
     runs-on: ubuntu-latest
-
     steps:
       - name: Checkout code
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4
 
       - name: Check for CHANGELOG.md
-        run: |
-          if ! git diff --name-only HEAD^ | grep -q "^CHANGELOG.md$"; then
-            echo "ERROR: CHANGELOG.md not modified in this pull request"
-            exit 1
-          fi
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
+

From 8c2058e11c04e8ca45f206610dfe306f0759534a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 11:48:56 +0200
Subject: [PATCH 218/234] add skip changelog label

---
 riscv-rt/.github/workflows/changelog.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
index b453b02e..52c7cff6 100644
--- a/riscv-rt/.github/workflows/changelog.yaml
+++ b/riscv-rt/.github/workflows/changelog.yaml
@@ -1,6 +1,7 @@
 name: Check CHANGELOG.md
 
 on:
+  merge_group:
   pull_request:
     types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
 
@@ -14,5 +15,6 @@ jobs:
       - name: Check for CHANGELOG.md
         uses: dangoslen/changelog-enforcer@v3
         with:
+          skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
 

From d9fb8e5f37926d13c062112885b11c79ba8394a6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 12:30:57 +0200
Subject: [PATCH 219/234] Added workflow to check invalid labels

---
 riscv-rt/.github/workflows/changelog.yaml |  2 +-
 riscv-rt/.github/workflows/gh_labels.yaml | 19 +++++++++++++++++++
 riscv-rt/CHANGELOG.md                     |  3 ++-
 3 files changed, 22 insertions(+), 2 deletions(-)
 create mode 100644 riscv-rt/.github/workflows/gh_labels.yaml

diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
index 52c7cff6..2ea7fb89 100644
--- a/riscv-rt/.github/workflows/changelog.yaml
+++ b/riscv-rt/.github/workflows/changelog.yaml
@@ -6,7 +6,7 @@ on:
     types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
 
 jobs:
-  check_changelog:
+  changelog-check:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout code
diff --git a/riscv-rt/.github/workflows/gh_labels.yaml b/riscv-rt/.github/workflows/gh_labels.yaml
new file mode 100644
index 00000000..65574d8b
--- /dev/null
+++ b/riscv-rt/.github/workflows/gh_labels.yaml
@@ -0,0 +1,19 @@
+name: Check Labels
+on:
+  merge_group:
+  pull_request:
+    types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
+
+jobs:
+  label:
+    runs-on: ubuntu-latest
+    steps:
+      - id: labels-check
+        uses: mheap/github-action-required-labels@v5
+        with:
+          mode: exactly
+          count: 0
+          labels: "work in progress, do not merge"
+          add_comment: true
+          message: "This PR is being prevented from merging because it presents one of the blocking labels: {{ provided }}."
+
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index ed8eaeac..1a681606 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -9,7 +9,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
-- New GitHub worklow for checking modifications on CHANGELOG.md
+- New GitHub workflow for checking invalid labels in PRs
+- New GitHub workflow for checking modifications on CHANGELOG.md
 - New GitHub workflow for checking clippy lints in PRs
 
 ### Changed

From 6d05bb6fbc90bf778357e93817391a1063293b48 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 12:32:28 +0200
Subject: [PATCH 220/234] minor changes

---
 riscv-rt/.github/workflows/gh_labels.yaml | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/.github/workflows/gh_labels.yaml b/riscv-rt/.github/workflows/gh_labels.yaml
index 65574d8b..0dbd81f2 100644
--- a/riscv-rt/.github/workflows/gh_labels.yaml
+++ b/riscv-rt/.github/workflows/gh_labels.yaml
@@ -5,11 +5,10 @@ on:
     types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
 
 jobs:
-  label:
+  label-check:
     runs-on: ubuntu-latest
     steps:
-      - id: labels-check
-        uses: mheap/github-action-required-labels@v5
+      - uses: mheap/github-action-required-labels@v5
         with:
           mode: exactly
           count: 0

From 26e2095f917ad95951a64fa4c76ebf62c306d1a0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?=
 <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 12:45:24 +0200
Subject: [PATCH 221/234] Update and rename gh_labels.yaml to label.yaml

---
 riscv-rt/.github/workflows/{gh_labels.yaml => label.yaml} | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename riscv-rt/.github/workflows/{gh_labels.yaml => label.yaml} (100%)

diff --git a/riscv-rt/.github/workflows/gh_labels.yaml b/riscv-rt/.github/workflows/label.yaml
similarity index 100%
rename from riscv-rt/.github/workflows/gh_labels.yaml
rename to riscv-rt/.github/workflows/label.yaml
index 0dbd81f2..d97ca295 100644
--- a/riscv-rt/.github/workflows/gh_labels.yaml
+++ b/riscv-rt/.github/workflows/label.yaml
@@ -1,4 +1,5 @@
 name: Check Labels
+
 on:
   merge_group:
   pull_request:
@@ -15,4 +16,3 @@ jobs:
           labels: "work in progress, do not merge"
           add_comment: true
           message: "This PR is being prevented from merging because it presents one of the blocking labels: {{ provided }}."
-

From 23387940ed8228bbca17d4ca4d690ac62e461924 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?=
 <rcardenas.rod@gmail.com>
Date: Tue, 3 Oct 2023 15:47:04 +0200
Subject: [PATCH 222/234] Remove label-check from merge_group

It seems that the action used to check forbidden labels only works for PRs. Removing it from merge_group.
---
 riscv-rt/.github/workflows/label.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/riscv-rt/.github/workflows/label.yaml b/riscv-rt/.github/workflows/label.yaml
index d97ca295..2709fdd7 100644
--- a/riscv-rt/.github/workflows/label.yaml
+++ b/riscv-rt/.github/workflows/label.yaml
@@ -1,7 +1,6 @@
 name: Check Labels
 
 on:
-  merge_group:
   pull_request:
     types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
 

From b84edd6b73cb79e44e8fce59b1ca1b8cdfa53e3e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Wed, 8 Nov 2023 17:26:09 +0100
Subject: [PATCH 223/234] build.rs now adapts link.x for the target arch

---
 riscv-rt/CHANGELOG.md               |   1 +
 riscv-rt/build.rs                   |  29 +++--
 riscv-rt/link-rv64.x                | 174 ----------------------------
 riscv-rt/{link-rv32.x => link.x.in} |  48 ++++++--
 4 files changed, 56 insertions(+), 196 deletions(-)
 delete mode 100644 riscv-rt/link-rv64.x
 rename riscv-rt/{link-rv32.x => link.x.in} (72%)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 1a681606..8761c3cc 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Removed bors in favor of GitHub Merge Queue
 - `start_trap_rust` is now marked as `unsafe`
 - Implement `r0` as inline assembly
+- Use `${ARCH_WIDTH}` in `link.x.in` to adapt to different archs
 
 ## [v0.11.0] - 2023-01-18
 
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index c23da012..e7c92126 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -1,17 +1,21 @@
 // NOTE: Adapted from cortex-m/build.rs
 
 use riscv_target::Target;
-use std::env;
-use std::fs;
-use std::path::PathBuf;
+use std::{env, fs, io, path::PathBuf};
+
+fn add_linker_script(arch_width: u32) -> io::Result<()> {
+    // Read the file to a string and replace all occurrences of ${ARCH_WIDTH} with the arch width
+    let mut content = fs::read_to_string("link.x.in")?;
+    content = content.replace("${ARCH_WIDTH}", &arch_width.to_string());
 
-fn add_linker_script(bytes: &[u8]) {
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
 
     // Put the linker script somewhere the linker can find it
-    fs::write(out_dir.join("link.x"), bytes).unwrap();
+    fs::write(out_dir.join("link.x"), content)?;
     println!("cargo:rustc-link-search={}", out_dir.display());
     println!("cargo:rerun-if-changed=link.x");
+
+    Ok(())
 }
 
 fn main() {
@@ -22,19 +26,24 @@ fn main() {
     if target.starts_with("riscv") {
         println!("cargo:rustc-cfg=riscv");
         let target = Target::from_target_str(&target);
-        match target.bits {
+
+        // generate the linker script
+        let arch_width = match target.bits {
             32 => {
                 println!("cargo:rustc-cfg=riscv32");
-                add_linker_script(include_bytes!("link-rv32.x"));
+                4
             }
             64 => {
                 println!("cargo:rustc-cfg=riscv64");
-                add_linker_script(include_bytes!("link-rv64.x"));
+                8
             }
             _ => panic!("Unsupported bit width"),
-        }
+        };
+        add_linker_script(arch_width).unwrap();
+
+        // expose the ISA extensions
         if target.has_extension('m') {
-            println!("cargo:rustc-cfg=riscvm"); // we can expose extensions this way
+            println!("cargo:rustc-cfg=riscvm");
         }
     }
 }
diff --git a/riscv-rt/link-rv64.x b/riscv-rt/link-rv64.x
deleted file mode 100644
index 8128eac7..00000000
--- a/riscv-rt/link-rv64.x
+++ /dev/null
@@ -1,174 +0,0 @@
-PROVIDE(_stext = ORIGIN(REGION_TEXT));
-PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
-PROVIDE(_max_hart_id = 0);
-PROVIDE(_hart_stack_size = 2K);
-PROVIDE(_heap_size = 0);
-
-PROVIDE(UserSoft = DefaultHandler);
-PROVIDE(SupervisorSoft = DefaultHandler);
-PROVIDE(MachineSoft = DefaultHandler);
-PROVIDE(UserTimer = DefaultHandler);
-PROVIDE(SupervisorTimer = DefaultHandler);
-PROVIDE(MachineTimer = DefaultHandler);
-PROVIDE(UserExternal = DefaultHandler);
-PROVIDE(SupervisorExternal = DefaultHandler);
-PROVIDE(MachineExternal = DefaultHandler);
-
-PROVIDE(DefaultHandler = DefaultInterruptHandler);
-PROVIDE(ExceptionHandler = DefaultExceptionHandler);
-
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
-
-/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
-PROVIDE(_setup_interrupts = default_setup_interrupts);
-
-/* # Multi-processing hook function
-   fn _mp_hook() -> bool;
-
-   This function is called from all the harts and must return true only for one hart,
-   which will perform memory initialization. For other harts it must return false
-   and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
-*/
-PROVIDE(_mp_hook = default_mp_hook);
-
-/* # Start trap function override
-  By default uses the riscv crates default trap handler
-  but by providing the `_start_trap` symbol external crates can override.
-*/
-PROVIDE(_start_trap = default_start_trap);
-
-SECTIONS
-{
-  .text.dummy (NOLOAD) :
-  {
-    /* This section is intended to make _stext address work */
-    . = ABSOLUTE(_stext);
-  } > REGION_TEXT
-
-  .text _stext :
-  {
-    /* Put reset handler first in .text section so it ends up as the entry */
-    /* point of the program. */
-    KEEP(*(.init));
-    KEEP(*(.init.rust));
-    . = ALIGN(4);
-    *(.trap);
-    *(.trap.rust);
-    *(.text.abort);
-    *(.text .text.*);
-  } > REGION_TEXT
-
-  .rodata : ALIGN(4)
-  {
-    *(.srodata .srodata.*);
-    *(.rodata .rodata.*);
-
-    /* 4-byte align the end (VMA) of this section.
-       This is required by LLD to ensure the LMA of the following .data
-       section will have the correct alignment. */
-    . = ALIGN(4);
-  } > REGION_RODATA
-
-  .data : ALIGN(8)
-  {
-    _sidata = LOADADDR(.data);
-    _sdata = .;
-    /* Must be called __global_pointer$ for linker relaxations to work. */
-    PROVIDE(__global_pointer$ = . + 0x800);
-    *(.sdata .sdata.* .sdata2 .sdata2.*);
-    *(.data .data.*);
-    . = ALIGN(8);
-    _edata = .;
-  } > REGION_DATA AT > REGION_RODATA
-
-  .bss (NOLOAD) : ALIGN(8)
-  {
-    _sbss = .;
-    *(.sbss .sbss.* .bss .bss.*);
-    . = ALIGN(8);
-    _ebss = .;
-  } > REGION_BSS
-
-  /* fictitious region that represents the memory available for the heap */
-  .heap (NOLOAD) :
-  {
-    _sheap = .;
-    . += _heap_size;
-    . = ALIGN(4);
-    _eheap = .;
-  } > REGION_HEAP
-
-  /* fictitious region that represents the memory available for the stack */
-  .stack (NOLOAD) :
-  {
-    _estack = .;
-    . = ABSOLUTE(_stack_start);
-    _sstack = .;
-  } > REGION_STACK
-
-  /* fake output .got section */
-  /* Dynamic relocations are unsupported. This section is only used to detect
-     relocatable code in the input files and raise an error if relocatable code
-     is found */
-  .got (INFO) :
-  {
-    KEEP(*(.got .got.*));
-  }
-
-  .eh_frame (INFO) : { KEEP(*(.eh_frame)) }
-  .eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
-}
-
-/* Do not exceed this mark in the error messages above                                    | */
-ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
-
-ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
-
-ASSERT(ORIGIN(REGION_DATA) % 8 == 0, "
-ERROR(riscv-rt): the start of the REGION_DATA must be 8-byte aligned");
-
-ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
-
-ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
-
-ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
-
-ASSERT(_stext % 4 == 0, "
-ERROR(riscv-rt): `_stext` must be 4-byte aligned");
-
-ASSERT(_sdata % 8 == 0 && _edata % 8 == 0, "
-BUG(riscv-rt): .data is not 8-byte aligned");
-
-ASSERT(_sidata % 8 == 0, "
-BUG(riscv-rt): the LMA of .data is not 8-byte aligned");
-
-ASSERT(_sbss % 8 == 0 && _ebss % 8 == 0, "
-BUG(riscv-rt): .bss is not 8-byte aligned");
-
-ASSERT(_sheap % 4 == 0, "
-BUG(riscv-rt): start of .heap is not 4-byte aligned");
-
-ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
-ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
-Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
-
-ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
-ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
-Consider changing `_max_hart_id` or `_hart_stack_size`.");
-
-ASSERT(SIZEOF(.got) == 0, "
-.got section detected in the input files. Dynamic relocations are not
-supported. If you are linking to C code compiled using the `gcc` crate
-then modify your build script to compile the C code _without_ the
--fPIC flag. See the documentation of the `gcc::Config.fpic` method for
-details.");
-
-/* Do not exceed this mark in the error messages above                                    | */
diff --git a/riscv-rt/link-rv32.x b/riscv-rt/link.x.in
similarity index 72%
rename from riscv-rt/link-rv32.x
rename to riscv-rt/link.x.in
index deadea88..0df3f2da 100644
--- a/riscv-rt/link-rv32.x
+++ b/riscv-rt/link.x.in
@@ -1,3 +1,27 @@
+/* # Developer notes
+
+- Symbols that start with a double underscore (__) are considered "private"
+
+- Symbols that start with a single underscore (_) are considered "semi-public"; they can be
+  overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" {
+  static mut _heap_size }`).
+
+- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a
+  symbol if not dropped if it appears in or near the front of the linker arguments and "it's not
+  needed" by any of the preceding objects (linker arguments)
+
+- `PROVIDE` is used to provide default values that can be overridden by a user linker script
+
+- In this linker script, you may find symbols that look like `${...}` (e.g., `${ARCH_WIDTH}`).
+  These are wildcards used by the `build.rs` script to adapt to different target particularities.
+  Check `build.rs` for more details about these symbols.
+
+- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and*
+  the LMA of .data are all `${ARCH_WIDTH}`-byte aligned. These alignments are assumed by the RAM
+  initialization routine. There's also a second benefit: `${ARCH_WIDTH}`-byte aligned boundaries
+  means that you won't see "Address (..) is out of bounds" in the disassembly produced by `objdump`.
+*/
+
 PROVIDE(_stext = ORIGIN(REGION_TEXT));
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
 PROVIDE(_max_hart_id = 0);
@@ -72,7 +96,7 @@ SECTIONS
     . = ALIGN(4);
   } > REGION_RODATA
 
-  .data : ALIGN(4)
+  .data : ALIGN(${ARCH_WIDTH})
   {
     _sidata = LOADADDR(.data);
     _sdata = .;
@@ -80,15 +104,15 @@ SECTIONS
     PROVIDE(__global_pointer$ = . + 0x800);
     *(.sdata .sdata.* .sdata2 .sdata2.*);
     *(.data .data.*);
-    . = ALIGN(4);
+    . = ALIGN(${ARCH_WIDTH});
     _edata = .;
   } > REGION_DATA AT > REGION_RODATA
 
-  .bss (NOLOAD) : ALIGN(4)
+  .bss (NOLOAD) : ALIGN(${ARCH_WIDTH})
   {
     _sbss = .;
     *(.sbss .sbss.* .bss .bss.*);
-    . = ALIGN(4);
+    . = ALIGN(${ARCH_WIDTH});
     _ebss = .;
   } > REGION_BSS
 
@@ -129,8 +153,8 @@ ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
 ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
 ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
 
-ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
-ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
+ASSERT(ORIGIN(REGION_DATA) % ${ARCH_WIDTH} == 0, "
+ERROR(riscv-rt): the start of the REGION_DATA must be ${ARCH_WIDTH}-byte aligned");
 
 ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
 ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
@@ -144,14 +168,14 @@ ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
 ASSERT(_stext % 4 == 0, "
 ERROR(riscv-rt): `_stext` must be 4-byte aligned");
 
-ASSERT(_sdata % 4 == 0 && _edata % 4 == 0, "
-BUG(riscv-rt): .data is not 4-byte aligned");
+ASSERT(_sdata % ${ARCH_WIDTH} == 0 && _edata % ${ARCH_WIDTH} == 0, "
+BUG(riscv-rt): .data is not ${ARCH_WIDTH}-byte aligned");
 
-ASSERT(_sidata % 4 == 0, "
-BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
+ASSERT(_sidata % ${ARCH_WIDTH} == 0, "
+BUG(riscv-rt): the LMA of .data is not ${ARCH_WIDTH}-byte aligned");
 
-ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
-BUG(riscv-rt): .bss is not 4-byte aligned");
+ASSERT(_sbss % ${ARCH_WIDTH} == 0 && _ebss % ${ARCH_WIDTH} == 0, "
+BUG(riscv-rt): .bss is not ${ARCH_WIDTH}-byte aligned");
 
 ASSERT(_sheap % 4 == 0, "
 BUG(riscv-rt): start of .heap is not 4-byte aligned");

From 0631b3a1668d88806ae12ebdf6c46c86a5eaf523 Mon Sep 17 00:00:00 2001
From: Kevin Vigor <kvigor@gmail.com>
Date: Thu, 2 Nov 2023 10:24:56 -0600
Subject: [PATCH 224/234] Ignore hartid in single-hart mode.

Don't bother checking hart ID on startup in single-hart mode. Allows
use of cores with unusual mhartid values and saves a few instructions.
---
 riscv-rt/CHANGELOG.md |  1 +
 riscv-rt/src/lib.rs   | 25 ++++++++++++++++++-------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 1a681606..c3557b38 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Removed bors in favor of GitHub Merge Queue
 - `start_trap_rust` is now marked as `unsafe`
 - Implement `r0` as inline assembly
+- mhartid CSR is no longer read in single-hart mode, assumed zero
 
 ## [v0.11.0] - 2023-01-18
 
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 3e86c490..422f3f2e 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -372,7 +372,10 @@ use core::sync::atomic::{compiler_fence, Ordering};
 use riscv::register::{scause as xcause, stvec as xtvec, stvec::TrapMode as xTrapMode};
 
 #[cfg(not(feature = "s-mode"))]
-use riscv::register::{mcause as xcause, mhartid, mtvec as xtvec, mtvec::TrapMode as xTrapMode};
+use riscv::register::{mcause as xcause, mtvec as xtvec, mtvec::TrapMode as xTrapMode};
+
+#[cfg(all(not(feature = "single-hart"), not(feature = "s-mode")))]
+use riscv::register::mhartid;
 
 pub use riscv_rt_macros::{entry, pre_init};
 
@@ -404,13 +407,20 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! {
         fn _mp_hook(hartid: usize) -> bool;
     }
 
-    // sbi passes hartid as first parameter (a0)
-    #[cfg(feature = "s-mode")]
-    let hartid = a0;
-    #[cfg(not(feature = "s-mode"))]
-    let hartid = mhartid::read();
+    #[cfg(not(feature = "single-hart"))]
+    let run_init = {
+        // sbi passes hartid as first parameter (a0)
+        #[cfg(feature = "s-mode")]
+        let hartid = a0;
+        #[cfg(not(feature = "s-mode"))]
+        let hartid = mhartid::read();
+
+        _mp_hook(hartid)
+    };
+    #[cfg(feature = "single-hart")]
+    let run_init = true;
 
-    if _mp_hook(hartid) {
+    if run_init {
         __pre_init();
 
         // Initialize RAM
@@ -661,6 +671,7 @@ pub unsafe extern "Rust" fn default_pre_init() {}
 #[doc(hidden)]
 #[no_mangle]
 #[rustfmt::skip]
+#[cfg(not(feature = "single-hart"))]
 pub extern "Rust" fn default_mp_hook(hartid: usize) -> bool {
     match hartid {
         0 => true,

From 1a22ec557b89d7b629583d6d3a4e76924c11e203 Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Fri, 10 Nov 2023 19:16:42 +0800
Subject: [PATCH 225/234] Fix setting incorrect sp if single-hart

If single-hart is enabled, the sp is set to _stack_start - _hart_stack_size,
rather than _stack_start. Fix this.

Fixes: e540f1e410d5 ("Add feature single-hart")
Signed-off-by: Chien Wong <m@xv97.com>
---
 riscv-rt/src/asm.rs | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index c29d9183..a0af873f 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -85,7 +85,8 @@ _abs_start:
     .option push
     .option norelax
     la gp, __global_pointer$
-    .option pop",
+    .option pop
+    // Allocate stacks",
     #[cfg(all(not(feature = "single-hart"), feature = "s-mode"))]
     "mv t2, a0 // the hartid is passed as parameter by SMODE",
     #[cfg(all(not(feature = "single-hart"), not(feature = "s-mode")))]
@@ -93,9 +94,7 @@ _abs_start:
     #[cfg(not(feature = "single-hart"))]
     "lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    bgtu t2, t0, abort",
-    "// Allocate stacks
-    la sp, _stack_start
+    bgtu t2, t0, abort
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)",
     #[cfg(all(not(feature = "single-hart"), riscvm))]
@@ -109,9 +108,10 @@ _abs_start:
     addi t1, t1, -1
     bnez t1, 1b
 2:  ",
-    "sub sp, sp, t0
-
-    // Set frame pointer
+    "la sp, _stack_start",
+    #[cfg(not(feature = "single-hart"))]
+    "sub sp, sp, t0",
+    "// Set frame pointer
     add s0, sp, zero
 
     jal zero, _start_rust

From 17185e9627d6f2906e82b1db4b51f3c44c1194e1 Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Fri, 10 Nov 2023 19:20:40 +0800
Subject: [PATCH 226/234] Add 'single-hart' changelog entry

Signed-off-by: Chien Wong <m@xv97.com>
---
 riscv-rt/CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index c3557b38..5e022be7 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New GitHub workflow for checking invalid labels in PRs
 - New GitHub workflow for checking modifications on CHANGELOG.md
 - New GitHub workflow for checking clippy lints in PRs
+- Optional cargo feature `single-hart` for single CPU targets
 
 ### Changed
 

From 408acae8a79c28b12273f2fdcc9607ffec4216dd Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Fri, 10 Nov 2023 19:23:53 +0800
Subject: [PATCH 227/234] Update doc on single-hart

Signed-off-by: Chien Wong <m@xv97.com>
---
 riscv-rt/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 422f3f2e..54e5c01c 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -327,7 +327,7 @@
 //!
 //! ## `single-hart`
 //!
-//! This feature saves a little code size by removing unnecessary stack space calculation if there is only one hart on the target.
+//! This feature saves a little code size if there is only one hart on the target.
 //!
 //! ## `s-mode`
 //!

From b7372080456d7d0d0ee514529fc37794f7d0968a Mon Sep 17 00:00:00 2001
From: Chien Wong <m@xv97.com>
Date: Fri, 10 Nov 2023 20:44:57 +0800
Subject: [PATCH 228/234] Ensure sp is 16-byte aligned

Signed-off-by: Chien Wong <m@xv97.com>
---
 riscv-rt/CHANGELOG.md | 1 +
 riscv-rt/src/asm.rs   | 9 ++++++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 5e022be7..70178bc2 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `start_trap_rust` is now marked as `unsafe`
 - Implement `r0` as inline assembly
 - mhartid CSR is no longer read in single-hart mode, assumed zero
+- Ensure stack pointer is 16-byte aligned before jumping to Rust entry point
 
 ## [v0.11.0] - 2023-01-18
 
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index a0af873f..0eedebe6 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -108,10 +108,11 @@ _abs_start:
     addi t1, t1, -1
     bnez t1, 1b
 2:  ",
-    "la sp, _stack_start",
+    "la t1, _stack_start",
     #[cfg(not(feature = "single-hart"))]
-    "sub sp, sp, t0",
-    "// Set frame pointer
+    "sub t1, t1, t0",
+    "andi sp, t1, -16 // Force 16-byte alignment
+    // Set frame pointer
     add s0, sp, zero
 
     jal zero, _start_rust
@@ -135,6 +136,8 @@ _abs_start:
 #[rustfmt::skip]
 macro_rules! trap_handler {
     ($STORE:ident, $LOAD:ident, $BYTES:literal, $TRAP_SIZE:literal, [$(($REG:ident, $LOCATION:literal)),*]) => {
+        // ensure we do not break that sp is 16-byte aligned
+        const _: () = assert!(($TRAP_SIZE * $BYTES) % 16 == 0);
         global_asm!(
         "
             .section .trap, \"ax\"

From cd474dda9cb4e493893c48e8c80f8a61d3319a7d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 17 Nov 2023 13:56:31 +0100
Subject: [PATCH 229/234] Setting CI (WIP)

---
 .github/workflows/build.yaml                  |  2 +-
 .github/workflows/changelog.yaml              | 10 +++++
 .github/workflows/clippy.yaml                 |  2 +-
 .../.github => .github}/workflows/label.yaml  |  0
 .github/workflows/rustfmt.yaml                |  2 +-
 Cargo.toml                                    |  1 +
 riscv-rt/.github/CODEOWNERS                   |  1 -
 riscv-rt/.github/workflows/changelog.yaml     | 20 ---------
 riscv-rt/.github/workflows/clippy.yaml        | 42 -------------------
 riscv-rt/.github/workflows/rustfmt.yaml       | 19 ---------
 riscv-rt/.gitignore                           |  7 ----
 riscv-rt/CODE_OF_CONDUCT.md                   | 37 ----------------
 riscv/README.md                               | 41 ++++++++++++++++++
 13 files changed, 55 insertions(+), 129 deletions(-)
 rename {riscv-rt/.github => .github}/workflows/label.yaml (100%)
 delete mode 100644 riscv-rt/.github/CODEOWNERS
 delete mode 100644 riscv-rt/.github/workflows/changelog.yaml
 delete mode 100644 riscv-rt/.github/workflows/clippy.yaml
 delete mode 100644 riscv-rt/.github/workflows/rustfmt.yaml
 delete mode 100644 riscv-rt/.gitignore
 delete mode 100644 riscv-rt/CODE_OF_CONDUCT.md
 create mode 100644 riscv/README.md

diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml
index 659723f3..40b05006 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/build.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ staging, trying, master ]
+    branches: [ master, add-riscv-rt ]
   pull_request:
   merge_group:
 
diff --git a/.github/workflows/changelog.yaml b/.github/workflows/changelog.yaml
index ad78b0a7..85ccda85 100644
--- a/.github/workflows/changelog.yaml
+++ b/.github/workflows/changelog.yaml
@@ -19,6 +19,8 @@ jobs:
           filters: |
             riscv:
               - 'riscv/**'
+            riscv-rt:
+              - 'riscv-rt/**'
 
       - name: Check for CHANGELOG.md (riscv)
         if: steps.changes.outputs.riscv == 'true'
@@ -27,3 +29,11 @@ jobs:
           changeLogPath: ./riscv/CHANGELOG.md
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'
+
+      - name: Check for CHANGELOG.md (riscv-rt)
+        if: steps.changes.outputs.riscv-rt == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: ./riscv-rt/CHANGELOG.md
+          skipLabels: 'skip changelog'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-rt/CHANGELOG.md file.'
diff --git a/.github/workflows/clippy.yaml b/.github/workflows/clippy.yaml
index 351e1b45..73e1f49a 100644
--- a/.github/workflows/clippy.yaml
+++ b/.github/workflows/clippy.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ staging, trying, master ]
+    branches: [ master, add-riscv-rt ]
   pull_request:
   merge_group:
 
diff --git a/riscv-rt/.github/workflows/label.yaml b/.github/workflows/label.yaml
similarity index 100%
rename from riscv-rt/.github/workflows/label.yaml
rename to .github/workflows/label.yaml
diff --git a/.github/workflows/rustfmt.yaml b/.github/workflows/rustfmt.yaml
index 72957ecb..6ee6b39b 100644
--- a/.github/workflows/rustfmt.yaml
+++ b/.github/workflows/rustfmt.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ staging, trying, master ]
+    branches: [ master, add-riscv-rt ]
   pull_request:
   merge_group:
 
diff --git a/Cargo.toml b/Cargo.toml
index 0b7406f5..4533b2e7 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -2,4 +2,5 @@
 resolver = "2"
 members = [
     "riscv",
+    "riscv-rt",
 ]
diff --git a/riscv-rt/.github/CODEOWNERS b/riscv-rt/.github/CODEOWNERS
deleted file mode 100644
index 87f6c03f..00000000
--- a/riscv-rt/.github/CODEOWNERS
+++ /dev/null
@@ -1 +0,0 @@
-* @rust-embedded/riscv
\ No newline at end of file
diff --git a/riscv-rt/.github/workflows/changelog.yaml b/riscv-rt/.github/workflows/changelog.yaml
deleted file mode 100644
index 2ea7fb89..00000000
--- a/riscv-rt/.github/workflows/changelog.yaml
+++ /dev/null
@@ -1,20 +0,0 @@
-name: Check CHANGELOG.md
-
-on:
-  merge_group:
-  pull_request:
-    types: [opened, synchronize, reopened, ready_for_review, labeled, unlabeled]
-
-jobs:
-  changelog-check:
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout code
-        uses: actions/checkout@v4
-
-      - name: Check for CHANGELOG.md
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          skipLabels: 'skip changelog'
-          missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
-
diff --git a/riscv-rt/.github/workflows/clippy.yaml b/riscv-rt/.github/workflows/clippy.yaml
deleted file mode 100644
index 7c0d5474..00000000
--- a/riscv-rt/.github/workflows/clippy.yaml
+++ /dev/null
@@ -1,42 +0,0 @@
-on:
-  push:
-    branches: [ master ]
-  pull_request:
-  merge_group:
-
-name: Lints compliance check
-
-env:
-  CLIPPY_PARAMS: -W clippy::all -W clippy::pedantic -W clippy::nursery -W clippy::cargo
-
-jobs:
-  clippy:
-    strategy:
-      matrix:
-        toolchain: [ stable, nightly ]
-        cargo_flags:
-          - "--no-default-features"
-          - "--all-features"
-        include:
-          # Nightly is only for reference and allowed to fail
-          - toolchain: nightly
-            experimental: true
-    runs-on: ubuntu-latest
-    continue-on-error: ${{ matrix.experimental || false }}
-    steps:
-      - uses: actions/checkout@v3
-      - uses: dtolnay/rust-toolchain@master
-        with:
-          toolchain: ${{ matrix.toolchain }}
-          components: clippy
-      - name: Run clippy
-        run: cargo clippy --all ${{ matrix.cargo_flags }} -- -D warnings
-
-   # Job to check that all the lint checks succeeded
-  clippy-check:
-    needs:
-    - clippy
-    runs-on: ubuntu-latest
-    if: always()
-    steps:
-      - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'
diff --git a/riscv-rt/.github/workflows/rustfmt.yaml b/riscv-rt/.github/workflows/rustfmt.yaml
deleted file mode 100644
index 72993e73..00000000
--- a/riscv-rt/.github/workflows/rustfmt.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-
-on:
-  push:
-    branches: [ master ]
-  pull_request:
-  merge_group:
-
-name: Code formatting check
-
-jobs:
-  rustfmt:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - uses: dtolnay/rust-toolchain@stable
-        with:
-          components: rustfmt
-      - name: Run Rustfmt
-        run: cargo fmt --all -- --check --verbose
diff --git a/riscv-rt/.gitignore b/riscv-rt/.gitignore
deleted file mode 100644
index 7f8712d0..00000000
--- a/riscv-rt/.gitignore
+++ /dev/null
@@ -1,7 +0,0 @@
-Cargo.lock
-target/
-bin/*.after
-bin/*.before
-bin/*.o
-
-.vscode/
\ No newline at end of file
diff --git a/riscv-rt/CODE_OF_CONDUCT.md b/riscv-rt/CODE_OF_CONDUCT.md
deleted file mode 100644
index fccadf9a..00000000
--- a/riscv-rt/CODE_OF_CONDUCT.md
+++ /dev/null
@@ -1,37 +0,0 @@
-# The Rust Code of Conduct
-
-## Conduct
-
-**Contact**: [RISC-V team](https://github.com/rust-embedded/wg#the-riscv-team)
-
-* We are committed to providing a friendly, safe and welcoming environment for all, regardless of level of experience, gender identity and expression, sexual orientation, disability, personal appearance, body size, race, ethnicity, age, religion, nationality, or other similar characteristic.
-* On IRC, please avoid using overtly sexual nicknames or other nicknames that might detract from a friendly, safe and welcoming environment for all.
-* Please be kind and courteous. There's no need to be mean or rude.
-* Respect that people have differences of opinion and that every design or implementation choice carries a trade-off and numerous costs. There is seldom a right answer.
-* Please keep unstructured critique to a minimum. If you have solid ideas you want to experiment with, make a fork and see how it works.
-* We will exclude you from interaction if you insult, demean or harass anyone. That is not welcome behavior. We interpret the term "harassment" as including the definition in the [Citizen Code of Conduct](http://citizencodeofconduct.org/); if you have any lack of clarity about what might be included in that concept, please read their definition. In particular, we don't tolerate behavior that excludes people in socially marginalized groups.
-* Private harassment is also unacceptable. No matter who you are, if you feel you have been or are being harassed or made uncomfortable by a community member, please contact one of the channel ops or any of the [RISC-V team][team] immediately. Whether you're a regular contributor or a newcomer, we care about making this community a safe place for you and we've got your back.
-* Likewise any spamming, trolling, flaming, baiting or other attention-stealing behavior is not welcome.
-
-## Moderation
-
-These are the policies for upholding our community's standards of conduct.
-
-1. Remarks that violate the Rust standards of conduct, including hateful, hurtful, oppressive, or exclusionary remarks, are not allowed. (Cursing is allowed, but never targeting another user, and never in a hateful manner.)
-2. Remarks that moderators find inappropriate, whether listed in the code of conduct or not, are also not allowed.
-3. Moderators will first respond to such remarks with a warning.
-4. If the warning is unheeded, the user will be "kicked," i.e., kicked out of the communication channel to cool off.
-5. If the user comes back and continues to make trouble, they will be banned, i.e., indefinitely excluded.
-6. Moderators may choose at their discretion to un-ban the user if it was a first offense and they offer the offended party a genuine apology.
-7. If a moderator bans someone and you think it was unjustified, please take it up with that moderator, or with a different moderator, **in private**. Complaints about bans in-channel are not allowed.
-8. Moderators are held to a higher standard than other community members. If a moderator creates an inappropriate situation, they should expect less leeway than others.
-
-In the Rust community we strive to go the extra step to look out for each other. Don't just aim to be technically unimpeachable, try to be your best self. In particular, avoid flirting with offensive or sensitive issues, particularly if they're off-topic; this all too often leads to unnecessary fights, hurt feelings, and damaged trust; worse, it can drive people away from the community entirely.
-
-And if someone takes issue with something you said or did, resist the urge to be defensive. Just stop doing what it was they complained about and apologize. Even if you feel you were misinterpreted or unfairly accused, chances are good there was something you could've communicated better — remember that it's your responsibility to make your fellow Rustaceans comfortable. Everyone wants to get along and we are all here first and foremost because we want to talk about cool technology. You will find that people will be eager to assume good intent and forgive as long as you earn their trust.
-
-The enforcement policies listed above apply to all official embedded WG venues; including official IRC channels (#rust-embedded); GitHub repositories under rust-embedded; and all forums under rust-embedded.org (forum.rust-embedded.org).
-
-*Adapted from the [Node.js Policy on Trolling](http://blog.izs.me/post/30036893703/policy-on-trolling) as well as the [Contributor Covenant v1.3.0](https://www.contributor-covenant.org/version/1/3/0/).*
-
-[team]: https://github.com/rust-embedded/wg#the-riscv-team
diff --git a/riscv/README.md b/riscv/README.md
new file mode 100644
index 00000000..490c8d54
--- /dev/null
+++ b/riscv/README.md
@@ -0,0 +1,41 @@
+[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv)
+[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv)
+[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv)
+
+# `riscv`
+
+> Low level access to RISC-V processors
+
+This project is developed and maintained by the [RISC-V team][team].
+
+## [Documentation](https://docs.rs/crate/riscv)
+
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
+compile with older versions but that may change in any new patch release.
+
+## License
+
+Copyright 2019-2022 [RISC-V team][team]
+
+Permission to use, copy, modify, and/or distribute this software for any purpose
+with or without fee is hereby granted, provided that the above copyright notice
+and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
+FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
+OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: CODE_OF_CONDUCT.md
+[team]: https://github.com/rust-embedded/wg#the-risc-v-team

From 612d58d4bbe0bc97f96fe152cfeba747154832aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 17 Nov 2023 14:52:40 +0100
Subject: [PATCH 230/234] fix build.yaml

---
 .github/workflows/build.yaml | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml
index 40b05006..44d88d22 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/build.yaml
@@ -13,6 +13,9 @@ jobs:
       matrix:
         # All generated code should be running on stable now, MRSV is 1.59.0
         toolchain: [ stable, nightly, 1.60.0 ]
+        package: 
+          - riscv
+          - riscv-rt
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf
@@ -24,6 +27,10 @@ jobs:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
             experimental: true
+          - package: riscv-rt
+            cargo_flags:
+              - "--features=s-mode"
+              - "--features=single-hart"
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:
@@ -33,7 +40,7 @@ jobs:
         toolchain: ${{ matrix.toolchain }}
         targets: ${{ matrix.target }}
     - name: Build library
-      run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
+      run: cargo build --package ${{ matrix.package }} --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
       
   # On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links.
   build-others:
@@ -43,13 +50,15 @@ jobs:
           - macos-latest
           - ubuntu-latest
           - windows-latest
+        package: 
+          - riscv
         cargo_flags: [ "--no-default-features", "--all-features" ]
     runs-on: ${{ matrix.os }}
     steps:
       - uses: actions/checkout@v3
       - uses: dtolnay/rust-toolchain@stable
       - name: Build crate for host OS
-        run: cargo build ${{ matrix.cargo_flags }}
+        run: cargo build --package ${{ matrix.package }} ${{ matrix.cargo_flags }}
   
   # Job to check that all the builds succeeded
   build-check:

From edf4dace0db0d9b41f8e260971a5a9ca0ac83ff3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Fri, 17 Nov 2023 15:07:36 +0100
Subject: [PATCH 231/234] separation of CI

---
 .github/workflows/clippy.yaml                 | 32 +++++++++++++----
 .../workflows/riscv-rt.yaml                   | 21 +++++++-----
 .github/workflows/{build.yaml => riscv.yaml}  | 34 +++++++------------
 .github/workflows/rustfmt.yaml                |  4 +--
 4 files changed, 51 insertions(+), 40 deletions(-)
 rename riscv-rt/.github/workflows/build.yaml => .github/workflows/riscv-rt.yaml (54%)
 rename .github/workflows/{build.yaml => riscv.yaml} (63%)

diff --git a/.github/workflows/clippy.yaml b/.github/workflows/clippy.yaml
index 73e1f49a..06afb85a 100644
--- a/.github/workflows/clippy.yaml
+++ b/.github/workflows/clippy.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, add-riscv-rt ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
@@ -14,9 +14,6 @@ jobs:
     strategy:
       matrix:
         toolchain: [ stable, nightly ]
-        cargo_flags:
-          - "--no-default-features"
-          - "--all-features"
         include:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
@@ -24,18 +21,39 @@ jobs:
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@master
         with:
           toolchain: ${{ matrix.toolchain }}
           components: clippy
-      - name: Run clippy
-        run: cargo clippy --all ${{ matrix.cargo_flags }} -- -D warnings
+      - name: Run clippy (no features)
+        run: cargo clippy --all --no-default-features -- -D warnings
+      - name: Run clippy (all features)
+        run: cargo clippy --all --all-features -- -D warnings
+  
+  # Additonal clippy checks for riscv-rt
+  clippy-riscv-rt:
+    strategy:
+      matrix:
+        toolchain: [ stable, nightly ]
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+      - uses: actions/checkout@v4
+      - uses: dtolnay/rust-toolchain@master
+        with:
+          toolchain: ${{ matrix.toolchain }}
+          components: clippy
+      - name: Run clippy (s-mode)
+        run: cargo clippy --package riscv-rt --all --features=s-mode -- -D warnings
+      - name: Run clippy (single-hart)
+        run: cargo clippy --package riscv-rt --all --features=single-hart -- -D warnings
 
    # Job to check that all the lint checks succeeded
   clippy-check:
     needs:
     - clippy
+    - clippy-riscv-rt
     runs-on: ubuntu-latest
     if: always()
     steps:
diff --git a/riscv-rt/.github/workflows/build.yaml b/.github/workflows/riscv-rt.yaml
similarity index 54%
rename from riscv-rt/.github/workflows/build.yaml
rename to .github/workflows/riscv-rt.yaml
index 4c95f06a..b1aeff5a 100644
--- a/riscv-rt/.github/workflows/build.yaml
+++ b/.github/workflows/riscv-rt.yaml
@@ -4,10 +4,10 @@ on:
   pull_request:
   merge_group:
 
-name: Build check
+name: Build check (riscv-rt)
 
 jobs:
-  build-riscv:
+  build:
     strategy:
       matrix:
         # All generated code should be running on stable now, MRSV is 1.59.0
@@ -21,7 +21,6 @@ jobs:
         example:
           - empty
           - multi_core
-        cargo_flags: [ "--no-default-features", "--all-features" ]
         include:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
@@ -29,20 +28,24 @@ jobs:
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@master
         with:
           toolchain: ${{ matrix.toolchain }}
           targets: ${{ matrix.target }}
-      - name: Build library
-        run: cargo build --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
-      - name: Build example
-        run: RUSTFLAGS="-C link-arg=-Texamples/device.x" cargo build --target ${{ matrix.target }} --example ${{ matrix.example }} ${{ matrix.cargo_flags }}
+      - name: Build (no features)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }}
+      - name : Build example (s-mode)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode
+      - name : Build example (single-hart)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
+      - name: Build example (all features)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
   
   # Job to check that all the builds succeeded
   build-check:
     needs:
-    - build-riscv
+    - build
     runs-on: ubuntu-latest
     if: always()
     steps:
diff --git a/.github/workflows/build.yaml b/.github/workflows/riscv.yaml
similarity index 63%
rename from .github/workflows/build.yaml
rename to .github/workflows/riscv.yaml
index 44d88d22..ec3984dc 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/riscv.yaml
@@ -1,10 +1,10 @@
 on:
   push:
-    branches: [ master, add-riscv-rt ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
-name: Build check
+name: Build check (riscv)
 
 jobs:
   # We check that the crate builds and links for all the toolchains and targets.
@@ -13,52 +13,42 @@ jobs:
       matrix:
         # All generated code should be running on stable now, MRSV is 1.59.0
         toolchain: [ stable, nightly, 1.60.0 ]
-        package: 
-          - riscv
-          - riscv-rt
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf
           - riscv32imac-unknown-none-elf
           - riscv64imac-unknown-none-elf
           - riscv64gc-unknown-none-elf
-        cargo_flags: [ "--no-default-features", "--all-features" ]
         include:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly
             experimental: true
-          - package: riscv-rt
-            cargo_flags:
-              - "--features=s-mode"
-              - "--features=single-hart"
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
     - uses: dtolnay/rust-toolchain@master
       with:
         toolchain: ${{ matrix.toolchain }}
         targets: ${{ matrix.target }}
-    - name: Build library
-      run: cargo build --package ${{ matrix.package }} --target ${{ matrix.target }} ${{ matrix.cargo_flags }}
+    - name: Build (no features)
+      run: cargo build --package riscv --target ${{ matrix.target }}
+    - name: Build (all features)
+      run: cargo build --package riscv --target ${{ matrix.target }} --all-features
       
   # On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links.
   build-others:
     strategy:
       matrix:
-        os:
-          - macos-latest
-          - ubuntu-latest
-          - windows-latest
-        package: 
-          - riscv
-        cargo_flags: [ "--no-default-features", "--all-features" ]
+        os: [ macos-latest, ubuntu-latest, windows-latest ]
     runs-on: ${{ matrix.os }}
     steps:
       - uses: actions/checkout@v3
       - uses: dtolnay/rust-toolchain@stable
-      - name: Build crate for host OS
-        run: cargo build --package ${{ matrix.package }} ${{ matrix.cargo_flags }}
+      - name: Build (no features)
+        run: cargo build --package riscv
+      - name: Build (all features)
+        run: cargo build --package riscv --all-features
   
   # Job to check that all the builds succeeded
   build-check:
diff --git a/.github/workflows/rustfmt.yaml b/.github/workflows/rustfmt.yaml
index 6ee6b39b..8b68d6e7 100644
--- a/.github/workflows/rustfmt.yaml
+++ b/.github/workflows/rustfmt.yaml
@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, add-riscv-rt ]
+    branches: [ master ]
   pull_request:
   merge_group:
 
@@ -10,7 +10,7 @@ jobs:
   rustfmt:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@stable
         with:
           components: rustfmt

From 3d39bbfaadc4e00885a2f3671422057ace61ddaf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Sat, 18 Nov 2023 20:26:13 +0100
Subject: [PATCH 232/234] changelog

---
 riscv-rt/CHANGELOG.md | 1 +
 riscv/CHANGELOG.md    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 051566f5..bcd96239 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Cargo workspace for riscv and riscv-rt
 - Use inline assembly instead of pre-compiled blobs
 - Removed bors in favor of GitHub Merge Queue
 - `start_trap_rust` is now marked as `unsafe`
diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index e1881c1f..e9ae972d 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -20,7 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
-- Transitioning to cargo workspace
+- Cargo workspace for riscv and riscv-rt
 - Update `embedded-hal` dependency to v1.0 (bumps MSRV to 1.60)
 - `misa::MXL` renamed to `misa::XLEN`
 - Removed `bit_field` dependency

From d7b4ae981dd3c2e04fa4d6aeb04bf1bc257b0ea3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Mon, 20 Nov 2023 14:14:19 +0100
Subject: [PATCH 233/234] update Cargo.toml

---
 riscv-rt/Cargo.toml | 7 ++++---
 riscv/Cargo.toml    | 1 +
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index c65c24e5..a368c68f 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -2,20 +2,21 @@
 name = "riscv-rt"
 version = "0.11.0"
 rust-version = "1.59"
-repository = "https://github.com/rust-embedded/riscv-rt"
+repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
+documentation = "https://docs.rs/riscv-rt"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
-edition = "2018"
+edition = "2021"
 
 [features]
 s-mode = []
 single-hart = []
 
 [dependencies]
-riscv = "0.10"
+riscv = {path = "../riscv", version = "0.10"}
 riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]
diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml
index 9606eac5..821ba0e5 100644
--- a/riscv/Cargo.toml
+++ b/riscv/Cargo.toml
@@ -7,6 +7,7 @@ repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
+documentation = "https://docs.rs/riscv"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 

From 5407f3826e34ffbdb55e59d231fa22637daaff38 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Mon, 27 Nov 2023 16:20:38 +0100
Subject: [PATCH 234/234] Addressing review

---
 README.md                  | 39 ++++++++++++--------------------------
 riscv-rt/README.md         |  1 -
 riscv-rt/macros/Cargo.toml |  2 +-
 riscv/README.md            |  1 -
 4 files changed, 13 insertions(+), 30 deletions(-)

diff --git a/README.md b/README.md
index 490c8d54..8d8459dd 100644
--- a/README.md
+++ b/README.md
@@ -1,35 +1,18 @@
-[![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv)
-[![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv)
-[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv)
+# RISC-V crates
 
-# `riscv`
+This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:
 
-> Low level access to RISC-V processors
+* [`riscv`]: CPU peripheral access and intrinsics
+* [`riscv-rt`]: Startup code and interrupt handling
 
-This project is developed and maintained by the [RISC-V team][team].
-
-## [Documentation](https://docs.rs/crate/riscv)
-
-## Minimum Supported Rust Version (MSRV)
-
-This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
-compile with older versions but that may change in any new patch release.
 
-## License
-
-Copyright 2019-2022 [RISC-V team][team]
+This project is developed and maintained by the [RISC-V team][team].
 
-Permission to use, copy, modify, and/or distribute this software for any purpose
-with or without fee is hereby granted, provided that the above copyright notice
-and this permission notice appear in all copies.
+### Contribution
 
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
-REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
-INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
-OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
-TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
-THIS SOFTWARE.
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the
+work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any
+additional terms or conditions.
 
 ## Code of Conduct
 
@@ -37,5 +20,7 @@ Contribution to this crate is organized under the terms of the [Rust Code of
 Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
-[CoC]: CODE_OF_CONDUCT.md
+[`riscv`]: https://crates.io/crates/riscv
+[`riscv-rt`]: https://crates.io/crates/riscv-rt
 [team]: https://github.com/rust-embedded/wg#the-risc-v-team
+[CoC]: CODE_OF_CONDUCT.md
diff --git a/riscv-rt/README.md b/riscv-rt/README.md
index 6db52456..0f7ed012 100644
--- a/riscv-rt/README.md
+++ b/riscv-rt/README.md
@@ -1,6 +1,5 @@
 [![crates.io](https://img.shields.io/crates/d/riscv-rt.svg)](https://crates.io/crates/riscv-rt)
 [![crates.io](https://img.shields.io/crates/v/riscv-rt.svg)](https://crates.io/crates/riscv-rt)
-[![Build Status](https://travis-ci.org/rust-embedded/riscv-rt.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv-rt)
 
 # `riscv-rt`
 
diff --git a/riscv-rt/macros/Cargo.toml b/riscv-rt/macros/Cargo.toml
index 8c2d9c13..8ae2e353 100644
--- a/riscv-rt/macros/Cargo.toml
+++ b/riscv-rt/macros/Cargo.toml
@@ -9,7 +9,7 @@ documentation = "https://docs.rs/riscv-rt"
 keywords = ["riscv", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "riscv-rt-macros"
-repository = "https://github.com/rust-embedded/riscv-rt"
+repository = "https://github.com/rust-embedded/riscv"
 version = "0.2.0"
 
 [lib]
diff --git a/riscv/README.md b/riscv/README.md
index 490c8d54..f67ac78c 100644
--- a/riscv/README.md
+++ b/riscv/README.md
@@ -1,6 +1,5 @@
 [![crates.io](https://img.shields.io/crates/d/riscv.svg)](https://crates.io/crates/riscv)
 [![crates.io](https://img.shields.io/crates/v/riscv.svg)](https://crates.io/crates/riscv)
-[![Build Status](https://travis-ci.org/rust-embedded/riscv.svg?branch=master)](https://travis-ci.org/rust-embedded/riscv)
 
 # `riscv`