From d4371d4af3258058dee1607a0ce9918c869f68ff Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 29 Aug 2024 11:31:10 -0700 Subject: [PATCH] Only implement one solution for native triggers. When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777. --- riscv/csr_init.cc | 4 +++- riscv/triggers.cc | 38 +++++++++++++++++++++++++------------- riscv/triggers.h | 2 +- 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/riscv/csr_init.cc b/riscv/csr_init.cc index d72c925041..06d9d7df2a 100644 --- a/riscv/csr_init.cc +++ b/riscv/csr_init.cc @@ -205,7 +205,9 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa) add_csr(CSR_TDATA2, tdata2 = std::make_shared(proc, CSR_TDATA2)); add_csr(CSR_TDATA3, std::make_shared(proc, CSR_TDATA3)); add_csr(CSR_TINFO, std::make_shared(proc, CSR_TINFO)); - add_csr(CSR_TCONTROL, tcontrol = std::make_shared(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0)); + if (!proc->extension_enabled_const('S')) { + add_csr(CSR_TCONTROL, tcontrol = std::make_shared(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0)); + } } else { add_csr(CSR_TDATA1, std::make_shared(proc, CSR_TDATA1, 0)); add_csr(CSR_TDATA2, tdata2 = std::make_shared(proc, CSR_TDATA2, 0)); diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 452b656455..7fb20b6471 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -110,17 +110,29 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept return true; } -bool trigger_t::allow_action(const state_t * const state) const +bool trigger_t::allow_action(processor_t * const proc) const { + const state_t *state = proc->get_state(); if (get_action() == ACTION_DEBUG_EXCEPTION) { - const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE; - const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE; - const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE; - const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1; - const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1; - return (state->prv != PRV_M || mstatus_mie) && - (state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) && - (state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie); + if (proc->extension_enabled('S')) { + // The hardware prevents triggers with action=0 from matching or firing + // while in M-mode and while MIE in mstatus is 0. If medeleg [3]=1 then it + // prevents triggers with action=0 from matching or firing while in S-mode + // and while SIE in sstatus is 0. If medeleg [3]=1 and hedeleg [3]=1 then + // it prevents triggers with action=0 from matching or firing while in + // VS-mode and while SIE in vstatus is 0. + const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE; + const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE; + const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE; + const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1; + const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1; + return (state->prv != PRV_M || mstatus_mie) && + (state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) && + (state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie); + } else { + // mte and mpte in tcontrol is implemented. medeleg [3] is hard-wired to 0. + return (state->prv != PRV_M) || (state->tcontrol->read() & CSR_TCONTROL_MTE); + } } return true; } @@ -235,7 +247,7 @@ std::optional mcontrol_common_t::detect_memory_access_match(proc value &= 0xffffffff; } - if (simple_match(xlen, value) && allow_action(proc->get_state())) { + if (simple_match(xlen, value) && allow_action(proc)) { /* This is OK because this function is only called if the trigger was not * inhibited by the previous trigger in the chain. */ set_hit(timing ? HIT_IMMEDIATELY_AFTER : HIT_BEFORE); @@ -324,7 +336,7 @@ void mcontrol6_t::tdata1_write(processor_t * const proc, const reg_t val, const std::optional icount_t::detect_icount_fire(processor_t * const proc) noexcept { - if (!common_match(proc) || !allow_action(proc->get_state())) + if (!common_match(proc) || !allow_action(proc)) return std::nullopt; std::optional ret = std::nullopt; @@ -339,7 +351,7 @@ std::optional icount_t::detect_icount_fire(processor_t * const p void icount_t::detect_icount_decrement(processor_t * const proc) noexcept { - if (!common_match(proc) || !allow_action(proc->get_state())) + if (!common_match(proc) || !allow_action(proc)) return; if (count >= 1) { @@ -431,7 +443,7 @@ std::optional trap_common_t::detect_trap_match(processor_t * con bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0; reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1)); assert(bit < xlen); - if (simple_match(interrupt, bit) && allow_action(proc->get_state())) { + if (simple_match(interrupt, bit) && allow_action(proc)) { hit = true; return match_result_t(TIMING_AFTER, action); } diff --git a/riscv/triggers.h b/riscv/triggers.h index d88678defa..880e5c945f 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -99,7 +99,7 @@ class trigger_t { protected: static action_t legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept; bool common_match(processor_t * const proc, bool use_prev_prv = false) const noexcept; - bool allow_action(const state_t * const state) const; + bool allow_action(processor_t * const proc) const; reg_t tdata2; bool vs = false;