Hardware based computational threats (deviations from the specified functional or physical behavior) come from a variety of sources (e.g. imperfections of processes and materials as well as from environmental factors) during:
- design,
- manufacturing, or
- field operation of computing systems.
Such deviations are known to jeopardize the correctness and stability of the operation of computing systems. Despite the acknowledged reality of these challenges throughout all eras of computing, consensus on key and even basic terms and definitions evades us and consequently limits cooperation and understanding among researchers and practitioners working at different layers of the computing system stack or different application domains.
The RAS Terms & Definitions TG of RISC-V International will deliver a RAS Architecture Overview document that will establish a framework of terms and definitions (starting from common ones from research and development domains and adapting them as needed) for:
- physical mechanisms and processes that generate the threats,
- models that bound/frame them,
- their effects and manifestations through all hardware and software layers of the computing stack,
- means for their effects prediction, avoidance, and recovery.
The terms and definitions will be applicable to RAS interactions to all application domains and system architectures of the RISC-V ecosystem and when necessary, connections (translations'') will be provided to equivalent terms and definitions frequently used in different contexts (debug, safety, etc.). Related RISC-V specifications would incorporate the RAS terms for consistency.