From c07f1a48040717976e7e8f59a09800042c4a22f7 Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Tue, 14 Dec 2021 18:05:00 +0530 Subject: [PATCH 1/3] Added code for decoding instructions in internaldecoder.py Updated unsgn_rs1 and unsgn_rs2 lists with bitmanip instructions in coverage.py --- riscv_isac/coverage.py | 13 +- riscv_isac/plugins/internaldecoder.py | 428 +++++++++++++++++++------- 2 files changed, 320 insertions(+), 121 deletions(-) diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py index 97d823a..16de7d9 100644 --- a/riscv_isac/coverage.py +++ b/riscv_isac/coverage.py @@ -23,23 +23,26 @@ from collections.abc import MutableMapping -unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd'\ +unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\ 'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\ 'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\ 'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\ 'sha256sum0','sha256sum1','sha256sig0','sha256sig1','sha512sig0',\ 'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig0l','sha512sig1h','sha512sig0h',\ 'sha512sig1','sha512sum0','sha512sum1','sm3p0','sm3p1','aes64im',\ - 'sm4ed','sm4ks','ror','rol','rori','rorw','rolw','roriw','clmul','clmulh',\ + 'sm4ed','sm4ks','ror','rol','rori','rorw','rolw','roriw','clmul','clmulh','clmulr',\ 'andn','orn','xnor','pack','packh','packu','packuw','packw',\ 'xperm.n','xperm.b','grevi','aes64ks1i', 'shfli', 'unshfli', \ - 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi'] + 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\ + 'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\ + 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8'] unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\ 'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\ 'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\ - 'clmulh','andn','orn','xnor','pack','packh','packu','packuw','packw',\ + 'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\ 'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\ - 'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h'] + 'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\ + 'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw'] class cross(): diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py index fb9d793..b9995ad 100644 --- a/riscv_isac/plugins/internaldecoder.py +++ b/riscv_isac/plugins/internaldecoder.py @@ -1,111 +1,111 @@ -import riscv_isac.plugins as plugins - -class disassembler(): - - def __init__(self): - OPCODES = { - 0b0110111: self.lui, - 0b0010111: self.auipc, - 0b1101111: self.jal, - 0b1100111: self.jalr, - 0b1100011: self.branch_ops, - 0b0000011: self.load_ops, - 0b0100011: self.store_ops, - 0b0010011: self.arithi_ops, - 0b0110011: self.arith_ops, - 0b0001111: self.fence_ops, - 0b1110011: self.priviledged_ops, - 0b0011011: self.rv64i_arithi_ops, - 0b0111011: self.rv64i_arith_ops, - 0b0101111: self.rv64_rv32_atomic_ops, - 0b0000111: self.flw_fld, - 0b0100111: self.fsw_fsd, - 0b1000011: self.fmadd, - 0b1000111: self.fmsub, - 0b1001011: self.fnmsub, - 0b1001111: self.fnmadd, - 0b1010011: self.rv32_rv64_float_ops - } - """ Instruction Op-Codes dict for 32-bit instructions """ - - C_OPCODES = { - 0b00: self.quad0, - 0b01: self.quad1, - 0b10: self.quad2 - } - """ Instruction OP-CODES dict for 16-bit instructions """ - self.C_OPCODES = C_OPCODES - self.OPCODES = OPCODES - - @plugins.decoderHookImpl - def setup(self, arch): - self.arch = arch - - FIRST2_MASK = 0x00000003 - OPCODE_MASK = 0x0000007f - FUNCT3_MASK = 0x00007000 - FUNCT6_MASK = 0x3F000000 - FUNCT4_MASK = 0x3e000000 - - RD_MASK = 0x00000f80 - RS1_MASK = 0x000f8000 - RS2_MASK = 0x01f00000 - RS3_MASK = 0xf8000000 - BS_MASK = 0xc0000000 - - def extractOpcode(self, instr): - return self.OPCODE_MASK & instr - - ''' Processing Instr from OPCODES ''' - def twos_comp(self, val, bits): - if (val & (1 << (bits - 1))) != 0: - val = val - (1 << bits) - return val - - def lui(self, instrObj): - instr = instrObj.instr - imm = instr >> 12 - rd = ((instr & self.RD_MASK) >> 7, 'x') - instrObj.rd = rd - instrObj.imm = imm - instrObj.instr_name = "lui" - return instrObj - - def auipc(self, instrObj): - instr = instrObj.instr - imm = instr >> 12 - rd = ((instr & self.RD_MASK) >> 7, 'x') - instrObj.rd = rd - instrObj.imm = imm - instrObj.instr_name = "auipc" - return instrObj - - def jal(self, instrObj): - instr = instrObj.instr - imm_10_1 = (instr >> 21) & 0x000003ff - imm_11 = (instr >> 10) & 0x00000400 - imm_19_12 = (instr & 0x000ff000) >> 1 - imm_20 = (instr >> 31) << 19 - imm = imm_20 + imm_19_12 + imm_11 + imm_10_1 - imm = self.twos_comp(imm, 20) - rd = ((instr & self.RD_MASK) >> 7, 'x') - instrObj.imm = imm - instrObj.rd = rd - instrObj.instr_name = "jal" - return instrObj - - def jalr(self, instrObj): - instr = instrObj.instr - rd = ((instr & self.RD_MASK) >> 7, 'x') - rs1 = ((instr & self.RS1_MASK) >> 15, 'x') - imm_11_0 = instr >> 20 - imm = self.twos_comp(imm_11_0, 12) - instrObj.rd = rd - instrObj.rs1 = rs1 - instrObj.imm = imm - instrObj.instr_name = "jalr" - return instrObj - +import riscv_isac.plugins as plugins + +class disassembler(): + + def __init__(self): + OPCODES = { + 0b0110111: self.lui, + 0b0010111: self.auipc, + 0b1101111: self.jal, + 0b1100111: self.jalr, + 0b1100011: self.branch_ops, + 0b0000011: self.load_ops, + 0b0100011: self.store_ops, + 0b0010011: self.arithi_ops, + 0b0110011: self.arith_ops, + 0b0001111: self.fence_ops, + 0b1110011: self.priviledged_ops, + 0b0011011: self.rv64i_arithi_ops, + 0b0111011: self.rv64i_arith_ops, + 0b0101111: self.rv64_rv32_atomic_ops, + 0b0000111: self.flw_fld, + 0b0100111: self.fsw_fsd, + 0b1000011: self.fmadd, + 0b1000111: self.fmsub, + 0b1001011: self.fnmsub, + 0b1001111: self.fnmadd, + 0b1010011: self.rv32_rv64_float_ops + } + """ Instruction Op-Codes dict for 32-bit instructions """ + + C_OPCODES = { + 0b00: self.quad0, + 0b01: self.quad1, + 0b10: self.quad2 + } + """ Instruction OP-CODES dict for 16-bit instructions """ + self.C_OPCODES = C_OPCODES + self.OPCODES = OPCODES + + @plugins.decoderHookImpl + def setup(self, arch): + self.arch = arch + + FIRST2_MASK = 0x00000003 + OPCODE_MASK = 0x0000007f + FUNCT3_MASK = 0x00007000 + FUNCT6_MASK = 0x3F000000 + FUNCT4_MASK = 0x3e000000 + + RD_MASK = 0x00000f80 + RS1_MASK = 0x000f8000 + RS2_MASK = 0x01f00000 + RS3_MASK = 0xf8000000 + BS_MASK = 0xc0000000 + + def extractOpcode(self, instr): + return self.OPCODE_MASK & instr + + ''' Processing Instr from OPCODES ''' + def twos_comp(self, val, bits): + if (val & (1 << (bits - 1))) != 0: + val = val - (1 << bits) + return val + + def lui(self, instrObj): + instr = instrObj.instr + imm = instr >> 12 + rd = ((instr & self.RD_MASK) >> 7, 'x') + instrObj.rd = rd + instrObj.imm = imm + instrObj.instr_name = "lui" + return instrObj + + def auipc(self, instrObj): + instr = instrObj.instr + imm = instr >> 12 + rd = ((instr & self.RD_MASK) >> 7, 'x') + instrObj.rd = rd + instrObj.imm = imm + instrObj.instr_name = "auipc" + return instrObj + + def jal(self, instrObj): + instr = instrObj.instr + imm_10_1 = (instr >> 21) & 0x000003ff + imm_11 = (instr >> 10) & 0x00000400 + imm_19_12 = (instr & 0x000ff000) >> 1 + imm_20 = (instr >> 31) << 19 + imm = imm_20 + imm_19_12 + imm_11 + imm_10_1 + imm = self.twos_comp(imm, 20) + rd = ((instr & self.RD_MASK) >> 7, 'x') + instrObj.imm = imm + instrObj.rd = rd + instrObj.instr_name = "jal" + return instrObj + + def jalr(self, instrObj): + instr = instrObj.instr + rd = ((instr & self.RD_MASK) >> 7, 'x') + rs1 = ((instr & self.RS1_MASK) >> 15, 'x') + imm_11_0 = instr >> 20 + imm = self.twos_comp(imm_11_0, 12) + instrObj.rd = rd + instrObj.rs1 = rs1 + instrObj.imm = imm + instrObj.instr_name = "jalr" + return instrObj + def branch_ops(self, instrObj): instr = instrObj.instr funct3 = (instr & self.FUNCT3_MASK) >> 12 @@ -195,6 +195,7 @@ def arithi_ops(self, instrObj): funct3 = (instr & self.FUNCT3_MASK) >> 12 funct4 = (instr & self.FUNCT4_MASK) >> 25 funct6 = (instr & self.FUNCT6_MASK) >> 26 + funct7 = (instr >> 25) rd = ((instr & self.RD_MASK) >> 7, 'x') rs1 = ((instr & self.RS1_MASK) >> 15, 'x') rs2 = ((instr & self.RS2_MASK) >> 20, 'x') @@ -202,6 +203,12 @@ def arithi_ops(self, instrObj): imm = (instr >> 20) imm_val = self.twos_comp(imm, 12) bs = (instr & self.BS_MASK) >> 30 + if self.arch == 'rv32': + sbi = (instr & 0xf8000000) >> 25 + shamt = (instr & 0x1f00000) >> 20 + elif self.arch == 'rv64': + sbi = (instr & 0xfc000000) >> 26 + shamt = (instr & 0x3f00000) >> 20 instrObj.rd = rd instrObj.rs1 = rs1 @@ -222,7 +229,27 @@ def arithi_ops(self, instrObj): instrObj.instr_name = 'andi' if funct3 == 0b001: - if funct6 == 0b000010: + if funct7 == 0b0000100: + if instrObj.arch == 'rv32': + instrObj.instr_name = 'zip' + instrObj.rs1= rs1 + instrObj.rd = rd + elif sbi == 0b0100100 or sbi == 0b010010: + instrObj.rs1 = rs1 + instrObj.rd = rd + instrObj.shamt = shamt + instrObj.instr_name = 'bclri' + elif sbi == 0b0110100 or sbi == 0b011010: + instrObj.rs1 = rs1 + instrObj.rd = rd + instrObj.shamt = shamt + instrObj.instr_name = 'binvi' + elif sbi == 0b0010100 or sbi == 0b001010: + instrObj.rs1 = rs1 + instrObj.rd = rd + instrObj.shamt = shamt + instrObj.instr_name = 'bseti' + elif funct6 == 0b000010: imm = (instr & 0x03F00000)>>20 instrObj.rs1 = rs1 instrObj.rd = rd @@ -292,6 +319,28 @@ def arithi_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rd = rd instrObj.imm = bs + elif funct4 == 0b10000: + if rs2[0] == 0b00000: + instrObj.instr_name = 'clz' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif rs2[0] == 0b00010: + instrObj.instr_name = 'cpop' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif rs2[0] == 0b00001: + instrObj.instr_name = 'ctz' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif rs2[0] == 0b00100: + instrObj.instr_name = 'sext.b' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif rs2[0] == 0b00101: + instrObj.instr_name = 'sext.h' + instrObj.rs1 = rs1 + instrObj.rd = rd + else: instrObj.instr_name = 'slli' instrObj.imm = None @@ -302,7 +351,29 @@ def arithi_ops(self, instrObj): instrObj.shamt = shamt if funct3 == 0b101: - if funct6 == 0b000010: + if funct7 == 0b0000100: + if instrObj.arch == 'rv32': + instrObj.instr_name = 'unzip' + instrObj.rs1= rs1 + instrObj.rd = rd + elif (instr >> 20) == 0x6B8 or (instr >> 20) == 0x698 : + instrObj.instr_name = 'rev8' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif (instr >> 20) == 0x687: + instrObj.instr_name = 'brev8' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif (instr >> 20) == 0x287: + instrObj.instr_name = 'orc.b' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif sbi == 0b0100100 or sbi == 0b010010: + instrObj.rs1 = rs1 + instrObj.rd = rd + instrObj.shamt = shamt + instrObj.instr_name = 'bexti' + elif funct6 == 0b000010: imm = (instr & 0x03F00000)>>20 instrObj.rs1 = rs1 instrObj.rd = rd @@ -511,6 +582,21 @@ def arith_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + elif funct7 == 0b0100100: + instrObj.instr_name = 'bclr' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0110100: + instrObj.instr_name = 'binv' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0010100: + instrObj.instr_name = 'bset' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd else: instrObj.instr_name = 'sll' @@ -520,6 +606,21 @@ def arith_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + if funct7 == 0b0010000: + instrObj.instr_name = 'sh1add' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0000101: + instrObj.instr_name = 'clmulr' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0010100: + instrObj.instr_name = 'xperm4' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd else: instrObj.instr_name = 'slt' @@ -539,10 +640,31 @@ def arith_ops(self, instrObj): instrObj.rs2 = rs2 instrObj.rd = rd elif funct7 == 0b0000100: - instrObj.instr_name = 'pack' + if rs2[0] == 0b0: + instrObj.instr_name = 'zext.h' + instrObj.rs1 = rs1 + instrObj.rd = rd + else: + instrObj.instr_name = 'pack' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0000101: + instrObj.instr_name = 'min' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0010000: + instrObj.instr_name = 'sh2add' instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + elif funct7 == 0b0010100: + instrObj.instr_name = 'xperm8' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + # elif funct7 == 0b0100100: # instrObj.instr_name = 'packu' # instrObj.rs1 = rs1 @@ -566,6 +688,17 @@ def arith_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + elif funct7 == 0b0000101: + instrObj.instr_name = 'minu' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0100100: + instrObj.instr_name = 'bext' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + if funct3 == 0b110: if funct7 == 0b0100000: @@ -573,6 +706,16 @@ def arith_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + elif funct7 == 0b0010000: + instrObj.instr_name = 'sh3add' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0000101: + instrObj.instr_name = 'max' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd else: instrObj.instr_name = 'or' @@ -587,11 +730,16 @@ def arith_ops(self, instrObj): instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd + elif funct7 == 0b0000101: + instrObj.instr_name = 'maxu' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd else: instrObj.instr_name = 'and' return instrObj - + def fence_ops(self, instrObj): instr = instrObj.instr funct3 = (instr & self.FUNCT3_MASK) >> 12 @@ -658,6 +806,7 @@ def rv64i_arithi_ops(self, instrObj): funct3 = (instr & self.FUNCT3_MASK) >> 12 funct7 = (instr >> 25) + funct7a = (instr >> 26) # for slli.uw rd = ((instr & self.RD_MASK) >> 7, 'x') rs1 = ((instr & self.RS1_MASK) >> 15, 'x') imm = ((instr & self.RS2_MASK) >> 20) @@ -675,8 +824,28 @@ def rv64i_arithi_ops(self, instrObj): instrObj.shamt = shamt if funct3 == 0b001: - instrObj.instr_name = 'slliw' - if funct3 == 0b101: + if funct7a == 0b000010: + print("instr is slli.uw") + instrObj.instr_name = 'slli.uw' + instrObj.rs1 = rs1 + instrObj.rd = rd + instrObj.shamt = imm + elif funct7 == 0b0110000: + if imm == 0b00000: + instrObj.instr_name = 'clzw' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif imm == 0b00001: + instrObj.instr_name = 'ctzw' + instrObj.rs1 = rs1 + instrObj.rd = rd + elif imm == 0b00010: + instrObj.instr_name = 'cpopw' + instrObj.rs1 = rs1 + instrObj.rd = rd + else: + instrObj.instr_name = 'slliw' + elif funct3 == 0b101: if funct7 == 0b0110000: instrObj.instr_name = 'roriw' instrObj.rs1 = rs1 @@ -737,6 +906,8 @@ def rv64i_arith_ops(self, instrObj): if funct3 == 0b000: if funct7 == 0b0000000: instrObj.instr_name = 'addw' + if funct7 == 0b0000100: + instrObj.instr_name = 'add.uw' if funct7 == 0b0100000: instrObj.instr_name = 'subw' @@ -749,9 +920,26 @@ def rv64i_arith_ops(self, instrObj): else: instrObj.instr_name = 'sllw' + if funct3 == 0b010: + if funct7 == 0b0010000: + instrObj.instr_name = 'sh1add.uw' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + if funct3 == 0b100: if funct7 == 0b0000100: - instrObj.instr_name = 'packw' + if rs2[0] == 0b0: + instrObj.instr_name = 'zext.h' + instrObj.rs1 = rs1 + instrObj.rd = rd + else: + instrObj.instr_name = 'packw' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + elif funct7 == 0b0010000: + instrObj.instr_name = 'sh2add.uw' instrObj.rs1 = rs1 instrObj.rs2 = rs2 instrObj.rd = rd @@ -772,8 +960,16 @@ def rv64i_arith_ops(self, instrObj): instrObj.rs2 = rs2 instrObj.rd = rd - return instrObj + if funct3 == 0b110: + if funct7 == 0b0010000: + instrObj.instr_name = 'sh3add.uw' + instrObj.rs1 = rs1 + instrObj.rs2 = rs2 + instrObj.rd = rd + + return instrObj + rv32a_instr_names = { 0b00010: 'lr.w', 0b00011: 'sc.w', From 7bdd7fdb6dda1e7f0f72b88ab86f9f4eec47e347 Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Mon, 24 Jan 2022 15:06:30 +0530 Subject: [PATCH 2/3] updates to zba, zbb instructions --- riscv_isac/coverage.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py index 58666be..bf27d9f 100644 --- a/riscv_isac/coverage.py +++ b/riscv_isac/coverage.py @@ -35,7 +35,8 @@ 'xperm.n','xperm.b','grevi','aes64ks1i', 'shfli', 'unshfli', \ 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\ 'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\ - 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8'] + 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\ + 'bclri','bexti','binvi','bseti'] unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\ 'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\ 'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\ From eae42303110c8156cfe2f9959728e43fe5cb62ee Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Thu, 27 Jan 2022 10:32:47 +0530 Subject: [PATCH 3/3] =?UTF-8?q?Bump=20version:=200.9.0=20=E2=86=92=200.10.?= =?UTF-8?q?0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 4 ++++ riscv_isac/__init__.py | 2 +- setup.cfg | 2 +- setup.py | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 30cb4f8..e42aae3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,10 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [0.10.0] - 2022-01-27 +- Added support for instructions from B extension. +- Bug fix for bgeu instruction. + ## [0.9.0] - 2022-01-07 - Added support for P extension cover point generation and instruction decoding. - Allowed an instruction to generate results in multiple registers. diff --git a/riscv_isac/__init__.py b/riscv_isac/__init__.py index 2125ef5..d269694 100644 --- a/riscv_isac/__init__.py +++ b/riscv_isac/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'info@incoresemi.com' -__version__ = '0.9.0' +__version__ = '0.10.0' diff --git a/setup.cfg b/setup.cfg index 5b03c59..193b68f 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.9.0 +current_version = 0.10.0 commit = True tag = True diff --git a/setup.py b/setup.py index bc393ce..4505fd5 100644 --- a/setup.py +++ b/setup.py @@ -26,7 +26,7 @@ def read_requires(): setup( name='riscv_isac', - version='0.9.0', + version='0.10.0', description="RISC-V ISAC", long_description=readme + '\n\n', classifiers=[